diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 47 |
1 files changed, 29 insertions, 18 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7ec8b488bb1d..769b864465a9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -5815,7 +5815,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) | |||
5815 | uint16_t postoff = 0; | 5815 | uint16_t postoff = 0; |
5816 | 5816 | ||
5817 | if (intel_crtc->config.limited_color_range) | 5817 | if (intel_crtc->config.limited_color_range) |
5818 | postoff = (16 * (1 << 13) / 255) & 0x1fff; | 5818 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
5819 | 5819 | ||
5820 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | 5820 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
5821 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | 5821 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
@@ -6303,7 +6303,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) | |||
6303 | uint32_t val; | 6303 | uint32_t val; |
6304 | 6304 | ||
6305 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | 6305 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6306 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", | 6306 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
6307 | pipe_name(crtc->pipe)); | 6307 | pipe_name(crtc->pipe)); |
6308 | 6308 | ||
6309 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | 6309 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
@@ -6402,7 +6402,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |||
6402 | 6402 | ||
6403 | /* Make sure we're not on PC8 state before disabling PC8, otherwise | 6403 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6404 | * we'll hang the machine! */ | 6404 | * we'll hang the machine! */ |
6405 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | 6405 | gen6_gt_force_wake_get(dev_priv); |
6406 | 6406 | ||
6407 | if (val & LCPLL_POWER_DOWN_ALLOW) { | 6407 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6408 | val &= ~LCPLL_POWER_DOWN_ALLOW; | 6408 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
@@ -6436,7 +6436,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |||
6436 | DRM_ERROR("Switching back to LCPLL failed\n"); | 6436 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6437 | } | 6437 | } |
6438 | 6438 | ||
6439 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | 6439 | gen6_gt_force_wake_put(dev_priv); |
6440 | } | 6440 | } |
6441 | 6441 | ||
6442 | void hsw_enable_pc8_work(struct work_struct *__work) | 6442 | void hsw_enable_pc8_work(struct work_struct *__work) |
@@ -8354,7 +8354,8 @@ static int intel_gen7_queue_flip(struct drm_device *dev, | |||
8354 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | 8354 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
8355 | DERRMR_PIPEB_PRI_FLIP_DONE | | 8355 | DERRMR_PIPEB_PRI_FLIP_DONE | |
8356 | DERRMR_PIPEC_PRI_FLIP_DONE)); | 8356 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
8357 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); | 8357 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8358 | MI_SRM_LRM_GLOBAL_GTT); | ||
8358 | intel_ring_emit(ring, DERRMR); | 8359 | intel_ring_emit(ring, DERRMR); |
8359 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | 8360 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
8360 | } | 8361 | } |
@@ -9134,7 +9135,7 @@ intel_pipe_config_compare(struct drm_device *dev, | |||
9134 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) | 9135 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9135 | PIPE_CONF_CHECK_I(pipe_bpp); | 9136 | PIPE_CONF_CHECK_I(pipe_bpp); |
9136 | 9137 | ||
9137 | if (!IS_HASWELL(dev)) { | 9138 | if (!HAS_DDI(dev)) { |
9138 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); | 9139 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9139 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | 9140 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
9140 | } | 9141 | } |
@@ -10049,7 +10050,7 @@ static void intel_setup_outputs(struct drm_device *dev) | |||
10049 | intel_ddi_init(dev, PORT_D); | 10050 | intel_ddi_init(dev, PORT_D); |
10050 | } else if (HAS_PCH_SPLIT(dev)) { | 10051 | } else if (HAS_PCH_SPLIT(dev)) { |
10051 | int found; | 10052 | int found; |
10052 | dpd_is_edp = intel_dpd_is_edp(dev); | 10053 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
10053 | 10054 | ||
10054 | if (has_edp_a(dev)) | 10055 | if (has_edp_a(dev)) |
10055 | intel_dp_init(dev, DP_A, PORT_A); | 10056 | intel_dp_init(dev, DP_A, PORT_A); |
@@ -10086,8 +10087,7 @@ static void intel_setup_outputs(struct drm_device *dev) | |||
10086 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | 10087 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
10087 | PORT_C); | 10088 | PORT_C); |
10088 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | 10089 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
10089 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, | 10090 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
10090 | PORT_C); | ||
10091 | } | 10091 | } |
10092 | 10092 | ||
10093 | intel_dsi_init(dev); | 10093 | intel_dsi_init(dev); |
@@ -10541,11 +10541,20 @@ static struct intel_quirk intel_quirks[] = { | |||
10541 | /* Sony Vaio Y cannot use SSC on LVDS */ | 10541 | /* Sony Vaio Y cannot use SSC on LVDS */ |
10542 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | 10542 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
10543 | 10543 | ||
10544 | /* | 10544 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10545 | * All GM45 Acer (and its brands eMachines and Packard Bell) laptops | 10545 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
10546 | * seem to use inverted backlight PWM. | 10546 | |
10547 | */ | 10547 | /* Acer/eMachines G725 */ |
10548 | { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness }, | 10548 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
10549 | |||
10550 | /* Acer/eMachines e725 */ | ||
10551 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | ||
10552 | |||
10553 | /* Acer/Packard Bell NCL20 */ | ||
10554 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | ||
10555 | |||
10556 | /* Acer Aspire 4736Z */ | ||
10557 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | ||
10549 | 10558 | ||
10550 | /* Dell XPS13 HD Sandy Bridge */ | 10559 | /* Dell XPS13 HD Sandy Bridge */ |
10551 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, | 10560 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, |
@@ -11036,8 +11045,6 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, | |||
11036 | } | 11045 | } |
11037 | 11046 | ||
11038 | intel_modeset_check_state(dev); | 11047 | intel_modeset_check_state(dev); |
11039 | |||
11040 | drm_mode_config_reset(dev); | ||
11041 | } | 11048 | } |
11042 | 11049 | ||
11043 | void intel_modeset_gem_init(struct drm_device *dev) | 11050 | void intel_modeset_gem_init(struct drm_device *dev) |
@@ -11046,7 +11053,10 @@ void intel_modeset_gem_init(struct drm_device *dev) | |||
11046 | 11053 | ||
11047 | intel_setup_overlay(dev); | 11054 | intel_setup_overlay(dev); |
11048 | 11055 | ||
11056 | drm_modeset_lock_all(dev); | ||
11057 | drm_mode_config_reset(dev); | ||
11049 | intel_modeset_setup_hw_state(dev, false); | 11058 | intel_modeset_setup_hw_state(dev, false); |
11059 | drm_modeset_unlock_all(dev); | ||
11050 | } | 11060 | } |
11051 | 11061 | ||
11052 | void intel_modeset_cleanup(struct drm_device *dev) | 11062 | void intel_modeset_cleanup(struct drm_device *dev) |
@@ -11125,14 +11135,15 @@ void intel_connector_attach_encoder(struct intel_connector *connector, | |||
11125 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | 11135 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
11126 | { | 11136 | { |
11127 | struct drm_i915_private *dev_priv = dev->dev_private; | 11137 | struct drm_i915_private *dev_priv = dev->dev_private; |
11138 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; | ||
11128 | u16 gmch_ctrl; | 11139 | u16 gmch_ctrl; |
11129 | 11140 | ||
11130 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | 11141 | pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl); |
11131 | if (state) | 11142 | if (state) |
11132 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | 11143 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
11133 | else | 11144 | else |
11134 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | 11145 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
11135 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | 11146 | pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl); |
11136 | return 0; | 11147 | return 0; |
11137 | } | 11148 | } |
11138 | 11149 | ||