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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c26
1 files changed, 17 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 234a77d0ee4e..b8d7ad6cab91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4696,7 +4696,6 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4696 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 4696 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4697 struct drm_display_mode *adjusted_mode = 4697 struct drm_display_mode *adjusted_mode =
4698 &intel_crtc->config.adjusted_mode; 4698 &intel_crtc->config.adjusted_mode;
4699 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4700 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; 4699 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4701 4700
4702 /* We need to be careful not to changed the adjusted mode, for otherwise 4701 /* We need to be careful not to changed the adjusted mode, for otherwise
@@ -4749,7 +4748,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4749 * always be the user's requested size. 4748 * always be the user's requested size.
4750 */ 4749 */
4751 I915_WRITE(PIPESRC(pipe), 4750 I915_WRITE(PIPESRC(pipe),
4752 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 4751 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4752 (intel_crtc->config.pipe_src_h - 1));
4753} 4753}
4754 4754
4755static void intel_get_pipe_timings(struct intel_crtc *crtc, 4755static void intel_get_pipe_timings(struct intel_crtc *crtc,
@@ -4787,8 +4787,11 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
4787 } 4787 }
4788 4788
4789 tmp = I915_READ(PIPESRC(crtc->pipe)); 4789 tmp = I915_READ(PIPESRC(crtc->pipe));
4790 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; 4790 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4791 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; 4791 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4792
4793 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4794 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4792} 4795}
4793 4796
4794static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, 4797static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
@@ -4884,7 +4887,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4884 struct drm_device *dev = crtc->dev; 4887 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private; 4888 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4888 int pipe = intel_crtc->pipe; 4890 int pipe = intel_crtc->pipe;
4889 int plane = intel_crtc->plane; 4891 int plane = intel_crtc->plane;
4890 int refclk, num_connectors = 0; 4892 int refclk, num_connectors = 0;
@@ -4983,8 +4985,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4983 * which should always be the user's requested size. 4985 * which should always be the user's requested size.
4984 */ 4986 */
4985 I915_WRITE(DSPSIZE(plane), 4987 I915_WRITE(DSPSIZE(plane),
4986 ((mode->vdisplay - 1) << 16) | 4988 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4987 (mode->hdisplay - 1)); 4989 (intel_crtc->config.pipe_src_w - 1));
4988 I915_WRITE(DSPPOS(plane), 0); 4990 I915_WRITE(DSPPOS(plane), 0);
4989 4991
4990 i9xx_set_pipeconf(intel_crtc); 4992 i9xx_set_pipeconf(intel_crtc);
@@ -8349,6 +8351,8 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
8349 DRM_DEBUG_KMS("adjusted mode:\n"); 8351 DRM_DEBUG_KMS("adjusted mode:\n");
8350 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); 8352 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8351 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); 8353 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8354 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8355 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8352 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 8356 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8353 pipe_config->gmch_pfit.control, 8357 pipe_config->gmch_pfit.control,
8354 pipe_config->gmch_pfit.pgm_ratios, 8358 pipe_config->gmch_pfit.pgm_ratios,
@@ -8400,6 +8404,10 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
8400 8404
8401 drm_mode_copy(&pipe_config->adjusted_mode, mode); 8405 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8402 drm_mode_copy(&pipe_config->requested_mode, mode); 8406 drm_mode_copy(&pipe_config->requested_mode, mode);
8407
8408 pipe_config->pipe_src_w = mode->hdisplay;
8409 pipe_config->pipe_src_h = mode->vdisplay;
8410
8403 pipe_config->cpu_transcoder = 8411 pipe_config->cpu_transcoder =
8404 (enum transcoder) to_intel_crtc(crtc)->pipe; 8412 (enum transcoder) to_intel_crtc(crtc)->pipe;
8405 pipe_config->shared_dpll = DPLL_ID_PRIVATE; 8413 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
@@ -8756,8 +8764,8 @@ intel_pipe_config_compare(struct drm_device *dev,
8756 DRM_MODE_FLAG_NVSYNC); 8764 DRM_MODE_FLAG_NVSYNC);
8757 } 8765 }
8758 8766
8759 PIPE_CONF_CHECK_I(requested_mode.hdisplay); 8767 PIPE_CONF_CHECK_I(pipe_src_w);
8760 PIPE_CONF_CHECK_I(requested_mode.vdisplay); 8768 PIPE_CONF_CHECK_I(pipe_src_h);
8761 8769
8762 PIPE_CONF_CHECK_I(gmch_pfit.control); 8770 PIPE_CONF_CHECK_I(gmch_pfit.control);
8763 /* pfit ratios are autocomputed by the hw on gen4+ */ 8771 /* pfit ratios are autocomputed by the hw on gen4+ */