aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_display.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ca8592e73644..0b327ebb2d9e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1342,6 +1342,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1342 } 1342 }
1343} 1343}
1344 1344
1345static void assert_vblank_disabled(struct drm_crtc *crtc)
1346{
1347 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1348 drm_crtc_vblank_put(crtc);
1349}
1350
1345static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1351static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1346{ 1352{
1347 u32 val; 1353 u32 val;
@@ -3891,6 +3897,8 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3892 int pipe = intel_crtc->pipe; 3898 int pipe = intel_crtc->pipe;
3893 3899
3900 assert_vblank_disabled(crtc);
3901
3894 drm_vblank_on(dev, pipe); 3902 drm_vblank_on(dev, pipe);
3895 3903
3896 intel_enable_primary_hw_plane(crtc->primary, crtc); 3904 intel_enable_primary_hw_plane(crtc->primary, crtc);
@@ -3940,6 +3948,8 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3940 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); 3948 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3941 3949
3942 drm_vblank_off(dev, pipe); 3950 drm_vblank_off(dev, pipe);
3951
3952 assert_vblank_disabled(crtc);
3943} 3953}
3944 3954
3945static void ironlake_crtc_enable(struct drm_crtc *crtc) 3955static void ironlake_crtc_enable(struct drm_crtc *crtc)
@@ -12766,9 +12776,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
12766 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 12776 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12767 12777
12768 /* restore vblank interrupts to correct state */ 12778 /* restore vblank interrupts to correct state */
12769 if (crtc->active) 12779 if (crtc->active) {
12780 update_scanline_offset(crtc);
12770 drm_vblank_on(dev, crtc->pipe); 12781 drm_vblank_on(dev, crtc->pipe);
12771 else 12782 } else
12772 drm_vblank_off(dev, crtc->pipe); 12783 drm_vblank_off(dev, crtc->pipe);
12773 12784
12774 /* We need to sanitize the plane -> pipe mapping first because this will 12785 /* We need to sanitize the plane -> pipe mapping first because this will
@@ -12867,8 +12878,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
12867 */ 12878 */
12868 crtc->cpu_fifo_underrun_disabled = true; 12879 crtc->cpu_fifo_underrun_disabled = true;
12869 crtc->pch_fifo_underrun_disabled = true; 12880 crtc->pch_fifo_underrun_disabled = true;
12870
12871 update_scanline_offset(crtc);
12872 } 12881 }
12873} 12882}
12874 12883