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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c3130
1 files changed, 1819 insertions, 1311 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 56746dcac40f..85f3eb74d2b7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -46,18 +46,6 @@ static void intel_increase_pllclock(struct drm_crtc *crtc);
46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47 47
48typedef struct { 48typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58} intel_clock_t;
59
60typedef struct {
61 int min, max; 49 int min, max;
62} intel_range_t; 50} intel_range_t;
63 51
@@ -71,24 +59,6 @@ typedef struct intel_limit intel_limit_t;
71struct intel_limit { 59struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1; 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2; 61 intel_p2_t p2;
74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92}; 62};
93 63
94/* FDI */ 64/* FDI */
@@ -104,29 +74,6 @@ intel_pch_rawclk(struct drm_device *dev)
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; 74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105} 75}
106 76
107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
120static bool
121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
124
125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
130static inline u32 /* units of 100MHz */ 77static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev) 78intel_fdi_link_freq(struct drm_device *dev)
132{ 79{
@@ -148,7 +95,6 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
148 .p1 = { .min = 2, .max = 33 }, 95 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000, 96 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 }, 97 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
152}; 98};
153 99
154static const intel_limit_t intel_limits_i8xx_lvds = { 100static const intel_limit_t intel_limits_i8xx_lvds = {
@@ -162,7 +108,6 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
162 .p1 = { .min = 1, .max = 6 }, 108 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000, 109 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 }, 110 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166}; 111};
167 112
168static const intel_limit_t intel_limits_i9xx_sdvo = { 113static const intel_limit_t intel_limits_i9xx_sdvo = {
@@ -176,7 +121,6 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
176 .p1 = { .min = 1, .max = 8 }, 121 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000, 122 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 }, 123 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
180}; 124};
181 125
182static const intel_limit_t intel_limits_i9xx_lvds = { 126static const intel_limit_t intel_limits_i9xx_lvds = {
@@ -190,7 +134,6 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
190 .p1 = { .min = 1, .max = 8 }, 134 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000, 135 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 }, 136 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
194}; 137};
195 138
196 139
@@ -207,7 +150,6 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
207 .p2_slow = 10, 150 .p2_slow = 10,
208 .p2_fast = 10 151 .p2_fast = 10
209 }, 152 },
210 .find_pll = intel_g4x_find_best_PLL,
211}; 153};
212 154
213static const intel_limit_t intel_limits_g4x_hdmi = { 155static const intel_limit_t intel_limits_g4x_hdmi = {
@@ -221,7 +163,6 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
221 .p1 = { .min = 1, .max = 8}, 163 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000, 164 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 }, 165 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
225}; 166};
226 167
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
@@ -236,7 +177,6 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
236 .p2 = { .dot_limit = 0, 177 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14 178 .p2_slow = 14, .p2_fast = 14
238 }, 179 },
239 .find_pll = intel_g4x_find_best_PLL,
240}; 180};
241 181
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
@@ -251,21 +191,6 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
251 .p2 = { .dot_limit = 0, 191 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7 192 .p2_slow = 7, .p2_fast = 7
253 }, 193 },
254 .find_pll = intel_g4x_find_best_PLL,
255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
269}; 194};
270 195
271static const intel_limit_t intel_limits_pineview_sdvo = { 196static const intel_limit_t intel_limits_pineview_sdvo = {
@@ -281,7 +206,6 @@ static const intel_limit_t intel_limits_pineview_sdvo = {
281 .p1 = { .min = 1, .max = 8 }, 206 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000, 207 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 }, 208 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
285}; 209};
286 210
287static const intel_limit_t intel_limits_pineview_lvds = { 211static const intel_limit_t intel_limits_pineview_lvds = {
@@ -295,7 +219,6 @@ static const intel_limit_t intel_limits_pineview_lvds = {
295 .p1 = { .min = 1, .max = 8 }, 219 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000, 220 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 }, 221 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
299}; 222};
300 223
301/* Ironlake / Sandybridge 224/* Ironlake / Sandybridge
@@ -314,7 +237,6 @@ static const intel_limit_t intel_limits_ironlake_dac = {
314 .p1 = { .min = 1, .max = 8 }, 237 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000, 238 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 }, 239 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
318}; 240};
319 241
320static const intel_limit_t intel_limits_ironlake_single_lvds = { 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
@@ -328,7 +250,6 @@ static const intel_limit_t intel_limits_ironlake_single_lvds = {
328 .p1 = { .min = 2, .max = 8 }, 250 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000, 251 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 }, 252 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332}; 253};
333 254
334static const intel_limit_t intel_limits_ironlake_dual_lvds = { 255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
@@ -342,7 +263,6 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds = {
342 .p1 = { .min = 2, .max = 8 }, 263 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000, 264 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 }, 265 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346}; 266};
347 267
348/* LVDS 100mhz refclk limits. */ 268/* LVDS 100mhz refclk limits. */
@@ -357,7 +277,6 @@ static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
357 .p1 = { .min = 2, .max = 8 }, 277 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000, 278 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 }, 279 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
361}; 280};
362 281
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
@@ -371,21 +290,6 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
371 .p1 = { .min = 2, .max = 6 }, 290 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000, 291 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 }, 292 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
389}; 293};
390 294
391static const intel_limit_t intel_limits_vlv_dac = { 295static const intel_limit_t intel_limits_vlv_dac = {
@@ -396,15 +300,14 @@ static const intel_limit_t intel_limits_vlv_dac = {
396 .m1 = { .min = 2, .max = 3 }, 300 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 }, 301 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 }, 302 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 }, 303 .p1 = { .min = 1, .max = 3 },
400 .p2 = { .dot_limit = 270000, 304 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 }, 305 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403}; 306};
404 307
405static const intel_limit_t intel_limits_vlv_hdmi = { 308static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 }, 309 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 5994000}, 310 .vco = { .min = 4000000, .max = 6000000 },
408 .n = { .min = 1, .max = 7 }, 311 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */ 312 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 }, 313 .m1 = { .min = 2, .max = 3 },
@@ -413,7 +316,6 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
413 .p1 = { .min = 2, .max = 3 }, 316 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000, 317 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 }, 318 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417}; 319};
418 320
419static const intel_limit_t intel_limits_vlv_dp = { 321static const intel_limit_t intel_limits_vlv_dp = {
@@ -424,61 +326,11 @@ static const intel_limit_t intel_limits_vlv_dp = {
424 .m1 = { .min = 2, .max = 3 }, 326 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 }, 327 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 }, 328 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 }, 329 .p1 = { .min = 1, .max = 3 },
428 .p2 = { .dot_limit = 270000, 330 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 }, 331 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431}; 332};
432 333
433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
436
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
439 return 0;
440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
447 return 0;
448 }
449
450 return I915_READ(DPIO_DATA);
451}
452
453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
457
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
460 return;
461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
469}
470
471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk) 335 int refclk)
484{ 336{
@@ -497,10 +349,7 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
497 else 349 else
498 limit = &intel_limits_ironlake_single_lvds; 350 limit = &intel_limits_ironlake_single_lvds;
499 } 351 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 352 } else
501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
502 limit = &intel_limits_ironlake_display_port;
503 else
504 limit = &intel_limits_ironlake_dac; 353 limit = &intel_limits_ironlake_dac;
505 354
506 return limit; 355 return limit;
@@ -521,8 +370,6 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
521 limit = &intel_limits_g4x_hdmi; 370 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo; 372 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */ 373 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo; 374 limit = &intel_limits_i9xx_sdvo;
528 375
@@ -573,13 +420,14 @@ static void pineview_clock(int refclk, intel_clock_t *clock)
573 clock->dot = clock->vco / clock->p; 420 clock->dot = clock->vco / clock->p;
574} 421}
575 422
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
577{ 424{
578 if (IS_PINEVIEW(dev)) { 425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
579 pineview_clock(refclk, clock); 426}
580 return; 427
581 } 428static void i9xx_clock(int refclk, intel_clock_t *clock)
582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 429{
430 clock->m = i9xx_dpll_compute_m(clock);
583 clock->p = clock->p1 * clock->p2; 431 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2); 432 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p; 433 clock->dot = clock->vco / clock->p;
@@ -636,10 +484,9 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
636} 484}
637 485
638static bool 486static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
640 int target, int refclk, intel_clock_t *match_clock, 488 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock) 489 intel_clock_t *best_clock)
642
643{ 490{
644 struct drm_device *dev = crtc->dev; 491 struct drm_device *dev = crtc->dev;
645 intel_clock_t clock; 492 intel_clock_t clock;
@@ -668,8 +515,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
668 clock.m1++) { 515 clock.m1++) {
669 for (clock.m2 = limit->m2.min; 516 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) { 517 clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in Pineview */ 518 if (clock.m2 >= clock.m1)
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
673 break; 519 break;
674 for (clock.n = limit->n.min; 520 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) { 521 clock.n <= limit->n.max; clock.n++) {
@@ -677,7 +523,66 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
677 clock.p1 <= limit->p1.max; clock.p1++) { 523 clock.p1 <= limit->p1.max; clock.p1++) {
678 int this_err; 524 int this_err;
679 525
680 intel_clock(dev, refclk, &clock); 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
551{
552 struct drm_device *dev = crtc->dev;
553 intel_clock_t clock;
554 int err = target;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 /*
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
561 */
562 if (intel_is_dual_link_lvds(dev))
563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
573 memset(best_clock, 0, sizeof(*best_clock));
574
575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
583 int this_err;
584
585 pineview_clock(refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit, 586 if (!intel_PLL_is_valid(dev, limit,
682 &clock)) 587 &clock))
683 continue; 588 continue;
@@ -699,9 +604,9 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
699} 604}
700 605
701static bool 606static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
703 int target, int refclk, intel_clock_t *match_clock, 608 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock) 609 intel_clock_t *best_clock)
705{ 610{
706 struct drm_device *dev = crtc->dev; 611 struct drm_device *dev = crtc->dev;
707 intel_clock_t clock; 612 intel_clock_t clock;
@@ -712,12 +617,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
712 found = false; 617 found = false;
713 618
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
715 int lvds_reg;
716
717 if (HAS_PCH_SPLIT(dev))
718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
721 if (intel_is_dual_link_lvds(dev)) 620 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast; 621 clock.p2 = limit->p2.p2_fast;
723 else 622 else
@@ -742,13 +641,10 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 clock.p1 >= limit->p1.min; clock.p1--) { 641 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err; 642 int this_err;
744 643
745 intel_clock(dev, refclk, &clock); 644 i9xx_clock(refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit, 645 if (!intel_PLL_is_valid(dev, limit,
747 &clock)) 646 &clock))
748 continue; 647 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752 648
753 this_err = abs(clock.dot - target); 649 this_err = abs(clock.dot - target);
754 if (this_err < err_most) { 650 if (this_err < err_most) {
@@ -765,62 +661,9 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
765} 661}
766 662
767static bool 663static bool
768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
769 int target, int refclk, intel_clock_t *match_clock, 665 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock) 666 intel_clock_t *best_clock)
771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
774
775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
798{
799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
819}
820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{ 667{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; 668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk; 669 u32 m, n, fastclk;
@@ -1066,14 +909,24 @@ static void assert_pll(struct drm_i915_private *dev_priv,
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true) 909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false) 910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068 911
912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
917 if (crtc->config.shared_dpll < 0)
918 return NULL;
919
920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
921}
922
1069/* For ILK+ */ 923/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv, 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
1071 struct intel_pch_pll *pll, 925 struct intel_shared_dpll *pll,
1072 struct intel_crtc *crtc, 926 bool state)
1073 bool state)
1074{ 927{
1075 u32 val;
1076 bool cur_state; 928 bool cur_state;
929 struct intel_dpll_hw_state hw_state;
1077 930
1078 if (HAS_PCH_LPT(dev_priv->dev)) { 931 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); 932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
@@ -1081,36 +934,16 @@ static void assert_pch_pll(struct drm_i915_private *dev_priv,
1081 } 934 }
1082 935
1083 if (WARN (!pll, 936 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state))) 937 "asserting DPLL %s with no DPLL\n", state_string(state)))
1085 return; 938 return;
1086 939
1087 val = I915_READ(pll->pll_reg); 940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state, 941 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", 942 "%s assertion failure (expected %s, current %s)\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val); 943 pll->name, state_string(state), state_string(cur_state));
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
1110 }
1111} 944}
1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) 945#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) 946#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1114 947
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv, 948static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state) 949 enum pipe pipe, bool state)
@@ -1227,8 +1060,8 @@ void assert_pipe(struct drm_i915_private *dev_priv,
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true; 1061 state = true;
1229 1062
1230 if (!intel_using_power_well(dev_priv->dev) && 1063 if (!intel_display_power_enabled(dev_priv->dev,
1231 cpu_transcoder != TRANSCODER_EDP) { 1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232 cur_state = false; 1065 cur_state = false;
1233 } else { 1066 } else {
1234 reg = PIPECONF(cpu_transcoder); 1067 reg = PIPECONF(cpu_transcoder);
@@ -1262,12 +1095,13 @@ static void assert_plane(struct drm_i915_private *dev_priv,
1262static void assert_planes_disabled(struct drm_i915_private *dev_priv, 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe) 1096 enum pipe pipe)
1264{ 1097{
1098 struct drm_device *dev = dev_priv->dev;
1265 int reg, i; 1099 int reg, i;
1266 u32 val; 1100 u32 val;
1267 int cur_pipe; 1101 int cur_pipe;
1268 1102
1269 /* Planes are fixed to pipes on ILK+ */ 1103 /* Primary planes are fixed to pipes on gen4+ */
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) { 1104 if (INTEL_INFO(dev)->gen >= 4) {
1271 reg = DSPCNTR(pipe); 1105 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg); 1106 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE), 1107 WARN((val & DISPLAY_PLANE_ENABLE),
@@ -1277,7 +1111,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1277 } 1111 }
1278 1112
1279 /* Need to check both planes against the pipe */ 1113 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) { 1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1281 reg = DSPCNTR(i); 1115 reg = DSPCNTR(i);
1282 val = I915_READ(reg); 1116 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
@@ -1291,19 +1125,30 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1291static void assert_sprites_disabled(struct drm_i915_private *dev_priv, 1125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe) 1126 enum pipe pipe)
1293{ 1127{
1128 struct drm_device *dev = dev_priv->dev;
1294 int reg, i; 1129 int reg, i;
1295 u32 val; 1130 u32 val;
1296 1131
1297 if (!IS_VALLEYVIEW(dev_priv->dev)) 1132 if (IS_VALLEYVIEW(dev)) {
1298 return; 1133 for (i = 0; i < dev_priv->num_plane; i++) {
1299 1134 reg = SPCNTR(pipe, i);
1300 /* Need to check both planes against the pipe */ 1135 val = I915_READ(reg);
1301 for (i = 0; i < dev_priv->num_plane; i++) { 1136 WARN((val & SP_ENABLE),
1302 reg = SPCNTR(pipe, i); 1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
1303 val = I915_READ(reg); 1142 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE), 1143 WARN((val & SPRITE_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n", 1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe)); 1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DVS_ENABLE),
1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151 plane_name(pipe), pipe_name(pipe));
1307 } 1152 }
1308} 1153}
1309 1154
@@ -1323,14 +1168,14 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); 1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324} 1169}
1325 1170
1326static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, 1171static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe) 1172 enum pipe pipe)
1328{ 1173{
1329 int reg; 1174 int reg;
1330 u32 val; 1175 u32 val;
1331 bool enabled; 1176 bool enabled;
1332 1177
1333 reg = TRANSCONF(pipe); 1178 reg = PCH_TRANSCONF(pipe);
1334 val = I915_READ(reg); 1179 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE); 1180 enabled = !!(val & TRANS_ENABLE);
1336 WARN(enabled, 1181 WARN(enabled,
@@ -1474,6 +1319,8 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1474 int reg; 1319 int reg;
1475 u32 val; 1320 u32 val;
1476 1321
1322 assert_pipe_disabled(dev_priv, pipe);
1323
1477 /* No really, not for ILK+ */ 1324 /* No really, not for ILK+ */
1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); 1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1479 1326
@@ -1525,156 +1372,86 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1525 POSTING_READ(reg); 1372 POSTING_READ(reg);
1526} 1373}
1527 1374
1528/* SBI access */ 1375void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1529static void
1530intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
1532{ 1376{
1533 u32 tmp; 1377 u32 port_mask;
1534 1378
1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 1379 if (!port)
1536 1380 port_mask = DPLL_PORTB_READY_MASK;
1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
1540 return;
1541 }
1542
1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else 1381 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; 1382 port_mask = DPLL_PORTC_READY_MASK;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1551 1383
1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, 1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1553 100)) { 1385 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); 1386 'B' + port, I915_READ(DPLL(0)));
1555 return;
1556 }
1557}
1558
1559static u32
1560intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
1562{
1563 u32 value = 0;
1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1565
1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
1569 return 0;
1570 }
1571
1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1579
1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1583 return 0;
1584 }
1585
1586 return I915_READ(SBI_DATA);
1587} 1387}
1588 1388
1589/** 1389/**
1590 * ironlake_enable_pch_pll - enable PCH PLL 1390 * ironlake_enable_shared_dpll - enable PCH PLL
1591 * @dev_priv: i915 private structure 1391 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable 1392 * @pipe: pipe PLL to enable
1593 * 1393 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock. 1395 * drives the transcoder clock.
1596 */ 1396 */
1597static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) 1397static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1598{ 1398{
1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1600 struct intel_pch_pll *pll; 1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1601 int reg;
1602 u32 val;
1603 1401
1604 /* PCH PLLs only available on ILK, SNB and IVB */ 1402 /* PCH PLLs only available on ILK, SNB and IVB */
1605 BUG_ON(dev_priv->info->gen < 5); 1403 BUG_ON(dev_priv->info->gen < 5);
1606 pll = intel_crtc->pch_pll; 1404 if (WARN_ON(pll == NULL))
1607 if (pll == NULL)
1608 return; 1405 return;
1609 1406
1610 if (WARN_ON(pll->refcount == 0)) 1407 if (WARN_ON(pll->refcount == 0))
1611 return; 1408 return;
1612 1409
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", 1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on, 1411 pll->name, pll->active, pll->on,
1615 intel_crtc->base.base.id); 1412 crtc->base.base.id);
1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619 1413
1620 if (pll->active++ && pll->on) { 1414 if (pll->active++) {
1621 assert_pch_pll_enabled(dev_priv, pll, NULL); 1415 WARN_ON(!pll->on);
1416 assert_shared_dpll_enabled(dev_priv, pll);
1622 return; 1417 return;
1623 } 1418 }
1419 WARN_ON(pll->on);
1624 1420
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); 1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1626 1422 pll->enable(dev_priv, pll);
1627 reg = pll->pll_reg;
1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
1633
1634 pll->on = true; 1423 pll->on = true;
1635} 1424}
1636 1425
1637static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) 1426static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1638{ 1427{
1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll; 1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1641 int reg;
1642 u32 val;
1643 1430
1644 /* PCH only available on ILK+ */ 1431 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5); 1432 BUG_ON(dev_priv->info->gen < 5);
1646 if (pll == NULL) 1433 if (WARN_ON(pll == NULL))
1647 return; 1434 return;
1648 1435
1649 if (WARN_ON(pll->refcount == 0)) 1436 if (WARN_ON(pll->refcount == 0))
1650 return; 1437 return;
1651 1438
1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", 1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on, 1440 pll->name, pll->active, pll->on,
1654 intel_crtc->base.base.id); 1441 crtc->base.base.id);
1655 1442
1656 if (WARN_ON(pll->active == 0)) { 1443 if (WARN_ON(pll->active == 0)) {
1657 assert_pch_pll_disabled(dev_priv, pll, NULL); 1444 assert_shared_dpll_disabled(dev_priv, pll);
1658 return; 1445 return;
1659 } 1446 }
1660 1447
1661 if (--pll->active) { 1448 assert_shared_dpll_enabled(dev_priv, pll);
1662 assert_pch_pll_enabled(dev_priv, pll, NULL); 1449 WARN_ON(!pll->on);
1450 if (--pll->active)
1663 return; 1451 return;
1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1670
1671 reg = pll->pll_reg;
1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
1677 1452
1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1454 pll->disable(dev_priv, pll);
1678 pll->on = false; 1455 pll->on = false;
1679} 1456}
1680 1457
@@ -1683,15 +1460,15 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1683{ 1460{
1684 struct drm_device *dev = dev_priv->dev; 1461 struct drm_device *dev = dev_priv->dev;
1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1686 uint32_t reg, val, pipeconf_val; 1464 uint32_t reg, val, pipeconf_val;
1687 1465
1688 /* PCH only available on ILK+ */ 1466 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5); 1467 BUG_ON(dev_priv->info->gen < 5);
1690 1468
1691 /* Make sure PCH DPLL is enabled */ 1469 /* Make sure PCH DPLL is enabled */
1692 assert_pch_pll_enabled(dev_priv, 1470 assert_shared_dpll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll, 1471 intel_crtc_to_shared_dpll(intel_crtc));
1694 to_intel_crtc(crtc));
1695 1472
1696 /* FDI must be feeding us bits for PCH ports */ 1473 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe); 1474 assert_fdi_tx_enabled(dev_priv, pipe);
@@ -1706,7 +1483,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1706 I915_WRITE(reg, val); 1483 I915_WRITE(reg, val);
1707 } 1484 }
1708 1485
1709 reg = TRANSCONF(pipe); 1486 reg = PCH_TRANSCONF(pipe);
1710 val = I915_READ(reg); 1487 val = I915_READ(reg);
1711 pipeconf_val = I915_READ(PIPECONF(pipe)); 1488 pipeconf_val = I915_READ(PIPECONF(pipe));
1712 1489
@@ -1731,7 +1508,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1731 1508
1732 I915_WRITE(reg, val | TRANS_ENABLE); 1509 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) 1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe); 1511 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1735} 1512}
1736 1513
1737static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1514static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
@@ -1760,8 +1537,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1760 else 1537 else
1761 val |= TRANS_PROGRESSIVE; 1538 val |= TRANS_PROGRESSIVE;
1762 1539
1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val); 1540 I915_WRITE(LPT_TRANSCONF, val);
1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) 1541 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n"); 1542 DRM_ERROR("Failed to enable PCH transcoder\n");
1766} 1543}
1767 1544
@@ -1778,13 +1555,13 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1778 /* Ports must be off as well */ 1555 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe); 1556 assert_pch_ports_disabled(dev_priv, pipe);
1780 1557
1781 reg = TRANSCONF(pipe); 1558 reg = PCH_TRANSCONF(pipe);
1782 val = I915_READ(reg); 1559 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE; 1560 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val); 1561 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */ 1562 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) 1563 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787 DRM_ERROR("failed to disable transcoder %d\n", pipe); 1564 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1788 1565
1789 if (!HAS_PCH_IBX(dev)) { 1566 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */ 1567 /* Workaround: Clear the timing override chicken bit again. */
@@ -1799,11 +1576,11 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1799{ 1576{
1800 u32 val; 1577 u32 val;
1801 1578
1802 val = I915_READ(_TRANSACONF); 1579 val = I915_READ(LPT_TRANSCONF);
1803 val &= ~TRANS_ENABLE; 1580 val &= ~TRANS_ENABLE;
1804 I915_WRITE(_TRANSACONF, val); 1581 I915_WRITE(LPT_TRANSCONF, val);
1805 /* wait for PCH transcoder off, transcoder state */ 1582 /* wait for PCH transcoder off, transcoder state */
1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) 1583 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n"); 1584 DRM_ERROR("Failed to disable PCH transcoder\n");
1808 1585
1809 /* Workaround: clear timing override bit. */ 1586 /* Workaround: clear timing override bit. */
@@ -1835,6 +1612,9 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1835 int reg; 1612 int reg;
1836 u32 val; 1613 u32 val;
1837 1614
1615 assert_planes_disabled(dev_priv, pipe);
1616 assert_sprites_disabled(dev_priv, pipe);
1617
1838 if (HAS_PCH_LPT(dev_priv->dev)) 1618 if (HAS_PCH_LPT(dev_priv->dev))
1839 pch_transcoder = TRANSCODER_A; 1619 pch_transcoder = TRANSCODER_A;
1840 else 1620 else
@@ -2096,7 +1876,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2096 case 1: 1876 case 1:
2097 break; 1877 break;
2098 default: 1878 default:
2099 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 1879 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2100 return -EINVAL; 1880 return -EINVAL;
2101 } 1881 }
2102 1882
@@ -2145,6 +1925,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2145 dspcntr &= ~DISPPLANE_TILED; 1925 dspcntr &= ~DISPPLANE_TILED;
2146 } 1926 }
2147 1927
1928 if (IS_G4X(dev))
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
2148 I915_WRITE(reg, dspcntr); 1931 I915_WRITE(reg, dspcntr);
2149 1932
2150 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
@@ -2193,7 +1976,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
2193 case 2: 1976 case 2:
2194 break; 1977 break;
2195 default: 1978 default:
2196 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2197 return -EINVAL; 1980 return -EINVAL;
2198 } 1981 }
2199 1982
@@ -2384,9 +2167,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2384 } 2167 }
2385 2168
2386 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { 2169 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2387 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", 2170 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2388 intel_crtc->plane, 2171 plane_name(intel_crtc->plane),
2389 INTEL_INFO(dev)->num_pipes); 2172 INTEL_INFO(dev)->num_pipes);
2390 return -EINVAL; 2173 return -EINVAL;
2391 } 2174 }
2392 2175
@@ -2414,7 +2197,8 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2414 crtc->y = y; 2197 crtc->y = y;
2415 2198
2416 if (old_fb) { 2199 if (old_fb) {
2417 intel_wait_for_vblank(dev, intel_crtc->pipe); 2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
2418 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); 2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2419 } 2203 }
2420 2204
@@ -2467,6 +2251,11 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
2467 FDI_FE_ERRC_ENABLE); 2251 FDI_FE_ERRC_ENABLE);
2468} 2252}
2469 2253
2254static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255{
2256 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257}
2258
2470static void ivb_modeset_global_resources(struct drm_device *dev) 2259static void ivb_modeset_global_resources(struct drm_device *dev)
2471{ 2260{
2472 struct drm_i915_private *dev_priv = dev->dev_private; 2261 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2476,10 +2265,13 @@ static void ivb_modeset_global_resources(struct drm_device *dev)
2476 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); 2265 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2477 uint32_t temp; 2266 uint32_t temp;
2478 2267
2479 /* When everything is off disable fdi C so that we could enable fdi B 2268 /*
2480 * with all lanes. XXX: This misses the case where a pipe is not using 2269 * When everything is off disable fdi C so that we could enable fdi B
2481 * any pch resources and so doesn't need any fdi lanes. */ 2270 * with all lanes. Note that we don't care about enabled pipes without
2482 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) { 2271 * an enabled pch encoder.
2272 */
2273 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274 !pipe_has_enabled_pch(pipe_C_crtc)) {
2483 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); 2275 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); 2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2485 2277
@@ -2517,8 +2309,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2517 /* enable CPU FDI TX and PCH FDI RX */ 2309 /* enable CPU FDI TX and PCH FDI RX */
2518 reg = FDI_TX_CTL(pipe); 2310 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg); 2311 temp = I915_READ(reg);
2520 temp &= ~(7 << 19); 2312 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2313 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2522 temp &= ~FDI_LINK_TRAIN_NONE; 2314 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1; 2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
@@ -2615,8 +2407,8 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2615 /* enable CPU FDI TX and PCH FDI RX */ 2407 /* enable CPU FDI TX and PCH FDI RX */
2616 reg = FDI_TX_CTL(pipe); 2408 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg); 2409 temp = I915_READ(reg);
2618 temp &= ~(7 << 19); 2410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2619 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2620 temp &= ~FDI_LINK_TRAIN_NONE; 2412 temp &= ~FDI_LINK_TRAIN_NONE;
2621 temp |= FDI_LINK_TRAIN_PATTERN_1; 2413 temp |= FDI_LINK_TRAIN_PATTERN_1;
2622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2750,8 +2542,8 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2750 /* enable CPU FDI TX and PCH FDI RX */ 2542 /* enable CPU FDI TX and PCH FDI RX */
2751 reg = FDI_TX_CTL(pipe); 2543 reg = FDI_TX_CTL(pipe);
2752 temp = I915_READ(reg); 2544 temp = I915_READ(reg);
2753 temp &= ~(7 << 19); 2545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2754 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2755 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 2547 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2756 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 2548 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2852,8 +2644,8 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2852 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 2644 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2853 reg = FDI_RX_CTL(pipe); 2645 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg); 2646 temp = I915_READ(reg);
2855 temp &= ~((0x7 << 19) | (0x7 << 16)); 2647 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2856 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 2649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2858 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 2650 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2859 2651
@@ -3085,6 +2877,30 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
3085 mutex_unlock(&dev_priv->dpio_lock); 2877 mutex_unlock(&dev_priv->dpio_lock);
3086} 2878}
3087 2879
2880static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881 enum pipe pch_transcoder)
2882{
2883 struct drm_device *dev = crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888 I915_READ(HTOTAL(cpu_transcoder)));
2889 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890 I915_READ(HBLANK(cpu_transcoder)));
2891 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892 I915_READ(HSYNC(cpu_transcoder)));
2893
2894 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895 I915_READ(VTOTAL(cpu_transcoder)));
2896 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897 I915_READ(VBLANK(cpu_transcoder)));
2898 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899 I915_READ(VSYNC(cpu_transcoder)));
2900 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902}
2903
3088/* 2904/*
3089 * Enable PCH resources required for PCH ports: 2905 * Enable PCH resources required for PCH ports:
3090 * - PCH PLLs 2906 * - PCH PLLs
@@ -3101,7 +2917,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
3101 int pipe = intel_crtc->pipe; 2917 int pipe = intel_crtc->pipe;
3102 u32 reg, temp; 2918 u32 reg, temp;
3103 2919
3104 assert_transcoder_disabled(dev_priv, pipe); 2920 assert_pch_transcoder_disabled(dev_priv, pipe);
3105 2921
3106 /* Write the TU size bits before fdi link training, so that error 2922 /* Write the TU size bits before fdi link training, so that error
3107 * detection works. */ 2923 * detection works. */
@@ -3115,31 +2931,18 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
3115 * transcoder, and we actually should do this to not upset any PCH 2931 * transcoder, and we actually should do this to not upset any PCH
3116 * transcoder that already use the clock when we share it. 2932 * transcoder that already use the clock when we share it.
3117 * 2933 *
3118 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll 2934 * Note that enable_shared_dpll tries to do the right thing, but
3119 * unconditionally resets the pll - we need that to have the right LVDS 2935 * get_shared_dpll unconditionally resets the pll - we need that to have
3120 * enable sequence. */ 2936 * the right LVDS enable sequence. */
3121 ironlake_enable_pch_pll(intel_crtc); 2937 ironlake_enable_shared_dpll(intel_crtc);
3122 2938
3123 if (HAS_PCH_CPT(dev)) { 2939 if (HAS_PCH_CPT(dev)) {
3124 u32 sel; 2940 u32 sel;
3125 2941
3126 temp = I915_READ(PCH_DPLL_SEL); 2942 temp = I915_READ(PCH_DPLL_SEL);
3127 switch (pipe) { 2943 temp |= TRANS_DPLL_ENABLE(pipe);
3128 default: 2944 sel = TRANS_DPLLB_SEL(pipe);
3129 case 0: 2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3130 temp |= TRANSA_DPLL_ENABLE;
3131 sel = TRANSA_DPLLB_SEL;
3132 break;
3133 case 1:
3134 temp |= TRANSB_DPLL_ENABLE;
3135 sel = TRANSB_DPLLB_SEL;
3136 break;
3137 case 2:
3138 temp |= TRANSC_DPLL_ENABLE;
3139 sel = TRANSC_DPLLB_SEL;
3140 break;
3141 }
3142 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3143 temp |= sel; 2946 temp |= sel;
3144 else 2947 else
3145 temp &= ~sel; 2948 temp &= ~sel;
@@ -3148,14 +2951,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
3148 2951
3149 /* set transcoder timing, panel must allow it */ 2952 /* set transcoder timing, panel must allow it */
3150 assert_panel_unlocked(dev_priv, pipe); 2953 assert_panel_unlocked(dev_priv, pipe);
3151 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); 2954 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3152 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3153 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3154
3155 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3156 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3157 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3158 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3159 2955
3160 intel_fdi_normal_train(crtc); 2956 intel_fdi_normal_train(crtc);
3161 2957
@@ -3205,86 +3001,82 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
3205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3206 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 3002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3207 3003
3208 assert_transcoder_disabled(dev_priv, TRANSCODER_A); 3004 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3209 3005
3210 lpt_program_iclkip(crtc); 3006 lpt_program_iclkip(crtc);
3211 3007
3212 /* Set transcoder timing. */ 3008 /* Set transcoder timing. */
3213 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder))); 3009 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3214 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3215 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3216
3217 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3218 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3219 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3220 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3221 3010
3222 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3223} 3012}
3224 3013
3225static void intel_put_pch_pll(struct intel_crtc *intel_crtc) 3014static void intel_put_shared_dpll(struct intel_crtc *crtc)
3226{ 3015{
3227 struct intel_pch_pll *pll = intel_crtc->pch_pll; 3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3228 3017
3229 if (pll == NULL) 3018 if (pll == NULL)
3230 return; 3019 return;
3231 3020
3232 if (pll->refcount == 0) { 3021 if (pll->refcount == 0) {
3233 WARN(1, "bad PCH PLL refcount\n"); 3022 WARN(1, "bad %s refcount\n", pll->name);
3234 return; 3023 return;
3235 } 3024 }
3236 3025
3237 --pll->refcount; 3026 if (--pll->refcount == 0) {
3238 intel_crtc->pch_pll = NULL; 3027 WARN_ON(pll->on);
3028 WARN_ON(pll->active);
3029 }
3030
3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3239} 3032}
3240 3033
3241static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) 3034static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3242{ 3035{
3243 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3244 struct intel_pch_pll *pll; 3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3245 int i; 3038 enum intel_dpll_id i;
3246 3039
3247 pll = intel_crtc->pch_pll;
3248 if (pll) { 3040 if (pll) {
3249 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", 3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3250 intel_crtc->base.base.id, pll->pll_reg); 3042 crtc->base.base.id, pll->name);
3251 goto prepare; 3043 intel_put_shared_dpll(crtc);
3252 } 3044 }
3253 3045
3254 if (HAS_PCH_IBX(dev_priv->dev)) { 3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3255 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ 3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3256 i = intel_crtc->pipe; 3048 i = crtc->pipe;
3257 pll = &dev_priv->pch_plls[i]; 3049 pll = &dev_priv->shared_dplls[i];
3258 3050
3259 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", 3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3260 intel_crtc->base.base.id, pll->pll_reg); 3052 crtc->base.base.id, pll->name);
3261 3053
3262 goto found; 3054 goto found;
3263 } 3055 }
3264 3056
3265 for (i = 0; i < dev_priv->num_pch_pll; i++) { 3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3266 pll = &dev_priv->pch_plls[i]; 3058 pll = &dev_priv->shared_dplls[i];
3267 3059
3268 /* Only want to check enabled timings first */ 3060 /* Only want to check enabled timings first */
3269 if (pll->refcount == 0) 3061 if (pll->refcount == 0)
3270 continue; 3062 continue;
3271 3063
3272 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && 3064 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3273 fp == I915_READ(pll->fp0_reg)) { 3065 fp == I915_READ(PCH_FP0(pll->id))) {
3274 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", 3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3275 intel_crtc->base.base.id, 3067 crtc->base.base.id,
3276 pll->pll_reg, pll->refcount, pll->active); 3068 pll->name, pll->refcount, pll->active);
3277 3069
3278 goto found; 3070 goto found;
3279 } 3071 }
3280 } 3072 }
3281 3073
3282 /* Ok no matching timings, maybe there's a free one? */ 3074 /* Ok no matching timings, maybe there's a free one? */
3283 for (i = 0; i < dev_priv->num_pch_pll; i++) { 3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3284 pll = &dev_priv->pch_plls[i]; 3076 pll = &dev_priv->shared_dplls[i];
3285 if (pll->refcount == 0) { 3077 if (pll->refcount == 0) {
3286 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", 3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3287 intel_crtc->base.base.id, pll->pll_reg); 3079 crtc->base.base.id, pll->name);
3288 goto found; 3080 goto found;
3289 } 3081 }
3290 } 3082 }
@@ -3292,24 +3084,32 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
3292 return NULL; 3084 return NULL;
3293 3085
3294found: 3086found:
3295 intel_crtc->pch_pll = pll; 3087 crtc->config.shared_dpll = i;
3296 pll->refcount++; 3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3297 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); 3089 pipe_name(crtc->pipe));
3298prepare: /* separate function? */
3299 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3300 3090
3301 /* Wait for the clocks to stabilize before rewriting the regs */ 3091 if (pll->active == 0) {
3302 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); 3092 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3303 POSTING_READ(pll->pll_reg); 3093 sizeof(pll->hw_state));
3304 udelay(150); 3094
3095 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3096 WARN_ON(pll->on);
3097 assert_shared_dpll_disabled(dev_priv, pll);
3098
3099 /* Wait for the clocks to stabilize before rewriting the regs */
3100 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101 POSTING_READ(PCH_DPLL(pll->id));
3102 udelay(150);
3103
3104 I915_WRITE(PCH_FP0(pll->id), fp);
3105 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3106 }
3107 pll->refcount++;
3305 3108
3306 I915_WRITE(pll->fp0_reg, fp);
3307 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3308 pll->on = false;
3309 return pll; 3109 return pll;
3310} 3110}
3311 3111
3312void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) 3112static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3313{ 3113{
3314 struct drm_i915_private *dev_priv = dev->dev_private; 3114 struct drm_i915_private *dev_priv = dev->dev_private;
3315 int dslreg = PIPEDSL(pipe); 3115 int dslreg = PIPEDSL(pipe);
@@ -3319,10 +3119,53 @@ void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3319 udelay(500); 3119 udelay(500);
3320 if (wait_for(I915_READ(dslreg) != temp, 5)) { 3120 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3321 if (wait_for(I915_READ(dslreg) != temp, 5)) 3121 if (wait_for(I915_READ(dslreg) != temp, 5))
3322 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); 3122 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3123 }
3124}
3125
3126static void ironlake_pfit_enable(struct intel_crtc *crtc)
3127{
3128 struct drm_device *dev = crtc->base.dev;
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 int pipe = crtc->pipe;
3131
3132 if (crtc->config.pch_pfit.size) {
3133 /* Force use of hard-coded filter coefficients
3134 * as some pre-programmed values are broken,
3135 * e.g. x201.
3136 */
3137 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3138 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3139 PF_PIPE_SEL_IVB(pipe));
3140 else
3141 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3142 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3143 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3323 } 3144 }
3324} 3145}
3325 3146
3147static void intel_enable_planes(struct drm_crtc *crtc)
3148{
3149 struct drm_device *dev = crtc->dev;
3150 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151 struct intel_plane *intel_plane;
3152
3153 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154 if (intel_plane->pipe == pipe)
3155 intel_plane_restore(&intel_plane->base);
3156}
3157
3158static void intel_disable_planes(struct drm_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->dev;
3161 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162 struct intel_plane *intel_plane;
3163
3164 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165 if (intel_plane->pipe == pipe)
3166 intel_plane_disable(&intel_plane->base);
3167}
3168
3326static void ironlake_crtc_enable(struct drm_crtc *crtc) 3169static void ironlake_crtc_enable(struct drm_crtc *crtc)
3327{ 3170{
3328 struct drm_device *dev = crtc->dev; 3171 struct drm_device *dev = crtc->dev;
@@ -3339,6 +3182,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3339 return; 3182 return;
3340 3183
3341 intel_crtc->active = true; 3184 intel_crtc->active = true;
3185
3186 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3187 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3188
3342 intel_update_watermarks(dev); 3189 intel_update_watermarks(dev);
3343 3190
3344 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 3191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@@ -3362,22 +3209,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3362 if (encoder->pre_enable) 3209 if (encoder->pre_enable)
3363 encoder->pre_enable(encoder); 3210 encoder->pre_enable(encoder);
3364 3211
3365 /* Enable panel fitting for LVDS */ 3212 ironlake_pfit_enable(intel_crtc);
3366 if (dev_priv->pch_pf_size &&
3367 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3368 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3369 /* Force use of hard-coded filter coefficients
3370 * as some pre-programmed values are broken,
3371 * e.g. x201.
3372 */
3373 if (IS_IVYBRIDGE(dev))
3374 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3375 PF_PIPE_SEL_IVB(pipe));
3376 else
3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3378 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3379 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3380 }
3381 3213
3382 /* 3214 /*
3383 * On ILK+ LUT must be loaded before the pipe is running but with 3215 * On ILK+ LUT must be loaded before the pipe is running but with
@@ -3388,6 +3220,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3388 intel_enable_pipe(dev_priv, pipe, 3220 intel_enable_pipe(dev_priv, pipe,
3389 intel_crtc->config.has_pch_encoder); 3221 intel_crtc->config.has_pch_encoder);
3390 intel_enable_plane(dev_priv, plane, pipe); 3222 intel_enable_plane(dev_priv, plane, pipe);
3223 intel_enable_planes(crtc);
3224 intel_crtc_update_cursor(crtc, true);
3391 3225
3392 if (intel_crtc->config.has_pch_encoder) 3226 if (intel_crtc->config.has_pch_encoder)
3393 ironlake_pch_enable(crtc); 3227 ironlake_pch_enable(crtc);
@@ -3396,13 +3230,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3396 intel_update_fbc(dev); 3230 intel_update_fbc(dev);
3397 mutex_unlock(&dev->struct_mutex); 3231 mutex_unlock(&dev->struct_mutex);
3398 3232
3399 intel_crtc_update_cursor(crtc, true);
3400
3401 for_each_encoder_on_crtc(dev, crtc, encoder) 3233 for_each_encoder_on_crtc(dev, crtc, encoder)
3402 encoder->enable(encoder); 3234 encoder->enable(encoder);
3403 3235
3404 if (HAS_PCH_CPT(dev)) 3236 if (HAS_PCH_CPT(dev))
3405 intel_cpt_verify_modeset(dev, intel_crtc->pipe); 3237 cpt_verify_modeset(dev, intel_crtc->pipe);
3406 3238
3407 /* 3239 /*
3408 * There seems to be a race in PCH platform hw (at least on some 3240 * There seems to be a race in PCH platform hw (at least on some
@@ -3415,6 +3247,42 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3415 intel_wait_for_vblank(dev, intel_crtc->pipe); 3247 intel_wait_for_vblank(dev, intel_crtc->pipe);
3416} 3248}
3417 3249
3250/* IPS only exists on ULT machines and is tied to pipe A. */
3251static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3252{
3253 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3254}
3255
3256static void hsw_enable_ips(struct intel_crtc *crtc)
3257{
3258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3259
3260 if (!crtc->config.ips_enabled)
3261 return;
3262
3263 /* We can only enable IPS after we enable a plane and wait for a vblank.
3264 * We guarantee that the plane is enabled by calling intel_enable_ips
3265 * only after intel_enable_plane. And intel_enable_plane already waits
3266 * for a vblank, so all we need to do here is to enable the IPS bit. */
3267 assert_plane_enabled(dev_priv, crtc->plane);
3268 I915_WRITE(IPS_CTL, IPS_ENABLE);
3269}
3270
3271static void hsw_disable_ips(struct intel_crtc *crtc)
3272{
3273 struct drm_device *dev = crtc->base.dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275
3276 if (!crtc->config.ips_enabled)
3277 return;
3278
3279 assert_plane_enabled(dev_priv, crtc->plane);
3280 I915_WRITE(IPS_CTL, 0);
3281
3282 /* We need to wait for a vblank before we can disable the plane. */
3283 intel_wait_for_vblank(dev, crtc->pipe);
3284}
3285
3418static void haswell_crtc_enable(struct drm_crtc *crtc) 3286static void haswell_crtc_enable(struct drm_crtc *crtc)
3419{ 3287{
3420 struct drm_device *dev = crtc->dev; 3288 struct drm_device *dev = crtc->dev;
@@ -3430,6 +3298,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3430 return; 3298 return;
3431 3299
3432 intel_crtc->active = true; 3300 intel_crtc->active = true;
3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 if (intel_crtc->config.has_pch_encoder)
3304 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3305
3433 intel_update_watermarks(dev); 3306 intel_update_watermarks(dev);
3434 3307
3435 if (intel_crtc->config.has_pch_encoder) 3308 if (intel_crtc->config.has_pch_encoder)
@@ -3441,18 +3314,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3441 3314
3442 intel_ddi_enable_pipe_clock(intel_crtc); 3315 intel_ddi_enable_pipe_clock(intel_crtc);
3443 3316
3444 /* Enable panel fitting for eDP */ 3317 ironlake_pfit_enable(intel_crtc);
3445 if (dev_priv->pch_pf_size &&
3446 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3447 /* Force use of hard-coded filter coefficients
3448 * as some pre-programmed values are broken,
3449 * e.g. x201.
3450 */
3451 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3452 PF_PIPE_SEL_IVB(pipe));
3453 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3454 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3455 }
3456 3318
3457 /* 3319 /*
3458 * On ILK+ LUT must be loaded before the pipe is running but with 3320 * On ILK+ LUT must be loaded before the pipe is running but with
@@ -3466,6 +3328,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3466 intel_enable_pipe(dev_priv, pipe, 3328 intel_enable_pipe(dev_priv, pipe,
3467 intel_crtc->config.has_pch_encoder); 3329 intel_crtc->config.has_pch_encoder);
3468 intel_enable_plane(dev_priv, plane, pipe); 3330 intel_enable_plane(dev_priv, plane, pipe);
3331 intel_enable_planes(crtc);
3332 intel_crtc_update_cursor(crtc, true);
3333
3334 hsw_enable_ips(intel_crtc);
3469 3335
3470 if (intel_crtc->config.has_pch_encoder) 3336 if (intel_crtc->config.has_pch_encoder)
3471 lpt_pch_enable(crtc); 3337 lpt_pch_enable(crtc);
@@ -3474,8 +3340,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3474 intel_update_fbc(dev); 3340 intel_update_fbc(dev);
3475 mutex_unlock(&dev->struct_mutex); 3341 mutex_unlock(&dev->struct_mutex);
3476 3342
3477 intel_crtc_update_cursor(crtc, true);
3478
3479 for_each_encoder_on_crtc(dev, crtc, encoder) 3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3480 encoder->enable(encoder); 3344 encoder->enable(encoder);
3481 3345
@@ -3490,6 +3354,21 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3490 intel_wait_for_vblank(dev, intel_crtc->pipe); 3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
3491} 3355}
3492 3356
3357static void ironlake_pfit_disable(struct intel_crtc *crtc)
3358{
3359 struct drm_device *dev = crtc->base.dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int pipe = crtc->pipe;
3362
3363 /* To avoid upsetting the power well on haswell only disable the pfit if
3364 * it's in use. The hw state code will make sure we get this right. */
3365 if (crtc->config.pch_pfit.size) {
3366 I915_WRITE(PF_CTL(pipe), 0);
3367 I915_WRITE(PF_WIN_POS(pipe), 0);
3368 I915_WRITE(PF_WIN_SZ(pipe), 0);
3369 }
3370}
3371
3493static void ironlake_crtc_disable(struct drm_crtc *crtc) 3372static void ironlake_crtc_disable(struct drm_crtc *crtc)
3494{ 3373{
3495 struct drm_device *dev = crtc->dev; 3374 struct drm_device *dev = crtc->dev;
@@ -3509,58 +3388,51 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
3509 3388
3510 intel_crtc_wait_for_pending_flips(crtc); 3389 intel_crtc_wait_for_pending_flips(crtc);
3511 drm_vblank_off(dev, pipe); 3390 drm_vblank_off(dev, pipe);
3512 intel_crtc_update_cursor(crtc, false);
3513
3514 intel_disable_plane(dev_priv, plane, pipe);
3515 3391
3516 if (dev_priv->cfb_plane == plane) 3392 if (dev_priv->cfb_plane == plane)
3517 intel_disable_fbc(dev); 3393 intel_disable_fbc(dev);
3518 3394
3395 intel_crtc_update_cursor(crtc, false);
3396 intel_disable_planes(crtc);
3397 intel_disable_plane(dev_priv, plane, pipe);
3398
3399 if (intel_crtc->config.has_pch_encoder)
3400 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3401
3519 intel_disable_pipe(dev_priv, pipe); 3402 intel_disable_pipe(dev_priv, pipe);
3520 3403
3521 /* Disable PF */ 3404 ironlake_pfit_disable(intel_crtc);
3522 I915_WRITE(PF_CTL(pipe), 0);
3523 I915_WRITE(PF_WIN_SZ(pipe), 0);
3524 3405
3525 for_each_encoder_on_crtc(dev, crtc, encoder) 3406 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 if (encoder->post_disable) 3407 if (encoder->post_disable)
3527 encoder->post_disable(encoder); 3408 encoder->post_disable(encoder);
3528 3409
3529 ironlake_fdi_disable(crtc); 3410 if (intel_crtc->config.has_pch_encoder) {
3411 ironlake_fdi_disable(crtc);
3530 3412
3531 ironlake_disable_pch_transcoder(dev_priv, pipe); 3413 ironlake_disable_pch_transcoder(dev_priv, pipe);
3414 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3532 3415
3533 if (HAS_PCH_CPT(dev)) { 3416 if (HAS_PCH_CPT(dev)) {
3534 /* disable TRANS_DP_CTL */ 3417 /* disable TRANS_DP_CTL */
3535 reg = TRANS_DP_CTL(pipe); 3418 reg = TRANS_DP_CTL(pipe);
3536 temp = I915_READ(reg); 3419 temp = I915_READ(reg);
3537 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); 3420 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3538 temp |= TRANS_DP_PORT_SEL_NONE; 3421 TRANS_DP_PORT_SEL_MASK);
3539 I915_WRITE(reg, temp); 3422 temp |= TRANS_DP_PORT_SEL_NONE;
3540 3423 I915_WRITE(reg, temp);
3541 /* disable DPLL_SEL */ 3424
3542 temp = I915_READ(PCH_DPLL_SEL); 3425 /* disable DPLL_SEL */
3543 switch (pipe) { 3426 temp = I915_READ(PCH_DPLL_SEL);
3544 case 0: 3427 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3545 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 3428 I915_WRITE(PCH_DPLL_SEL, temp);
3546 break;
3547 case 1:
3548 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3549 break;
3550 case 2:
3551 /* C shares PLL A or B */
3552 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3553 break;
3554 default:
3555 BUG(); /* wtf */
3556 } 3429 }
3557 I915_WRITE(PCH_DPLL_SEL, temp);
3558 }
3559 3430
3560 /* disable PCH DPLL */ 3431 /* disable PCH DPLL */
3561 intel_disable_pch_pll(intel_crtc); 3432 intel_disable_shared_dpll(intel_crtc);
3562 3433
3563 ironlake_fdi_pll_disable(intel_crtc); 3434 ironlake_fdi_pll_disable(intel_crtc);
3435 }
3564 3436
3565 intel_crtc->active = false; 3437 intel_crtc->active = false;
3566 intel_update_watermarks(dev); 3438 intel_update_watermarks(dev);
@@ -3588,24 +3460,24 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
3588 3460
3589 intel_crtc_wait_for_pending_flips(crtc); 3461 intel_crtc_wait_for_pending_flips(crtc);
3590 drm_vblank_off(dev, pipe); 3462 drm_vblank_off(dev, pipe);
3591 intel_crtc_update_cursor(crtc, false);
3592
3593 intel_disable_plane(dev_priv, plane, pipe);
3594 3463
3464 /* FBC must be disabled before disabling the plane on HSW. */
3595 if (dev_priv->cfb_plane == plane) 3465 if (dev_priv->cfb_plane == plane)
3596 intel_disable_fbc(dev); 3466 intel_disable_fbc(dev);
3597 3467
3468 hsw_disable_ips(intel_crtc);
3469
3470 intel_crtc_update_cursor(crtc, false);
3471 intel_disable_planes(crtc);
3472 intel_disable_plane(dev_priv, plane, pipe);
3473
3474 if (intel_crtc->config.has_pch_encoder)
3475 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3598 intel_disable_pipe(dev_priv, pipe); 3476 intel_disable_pipe(dev_priv, pipe);
3599 3477
3600 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); 3478 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3601 3479
3602 /* XXX: Once we have proper panel fitter state tracking implemented with 3480 ironlake_pfit_disable(intel_crtc);
3603 * hardware state read/check support we should switch to only disable
3604 * the panel fitter when we know it's used. */
3605 if (intel_using_power_well(dev)) {
3606 I915_WRITE(PF_CTL(pipe), 0);
3607 I915_WRITE(PF_WIN_SZ(pipe), 0);
3608 }
3609 3481
3610 intel_ddi_disable_pipe_clock(intel_crtc); 3482 intel_ddi_disable_pipe_clock(intel_crtc);
3611 3483
@@ -3615,6 +3487,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
3615 3487
3616 if (intel_crtc->config.has_pch_encoder) { 3488 if (intel_crtc->config.has_pch_encoder) {
3617 lpt_disable_pch_transcoder(dev_priv); 3489 lpt_disable_pch_transcoder(dev_priv);
3490 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3618 intel_ddi_fdi_disable(crtc); 3491 intel_ddi_fdi_disable(crtc);
3619 } 3492 }
3620 3493
@@ -3629,17 +3502,11 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
3629static void ironlake_crtc_off(struct drm_crtc *crtc) 3502static void ironlake_crtc_off(struct drm_crtc *crtc)
3630{ 3503{
3631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632 intel_put_pch_pll(intel_crtc); 3505 intel_put_shared_dpll(intel_crtc);
3633} 3506}
3634 3507
3635static void haswell_crtc_off(struct drm_crtc *crtc) 3508static void haswell_crtc_off(struct drm_crtc *crtc)
3636{ 3509{
3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638
3639 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3640 * start using it. */
3641 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3642
3643 intel_ddi_put_crtc_pll(crtc); 3510 intel_ddi_put_crtc_pll(crtc);
3644} 3511}
3645 3512
@@ -3685,6 +3552,77 @@ g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3685 } 3552 }
3686} 3553}
3687 3554
3555static void i9xx_pfit_enable(struct intel_crtc *crtc)
3556{
3557 struct drm_device *dev = crtc->base.dev;
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559 struct intel_crtc_config *pipe_config = &crtc->config;
3560
3561 if (!crtc->config.gmch_pfit.control)
3562 return;
3563
3564 /*
3565 * The panel fitter should only be adjusted whilst the pipe is disabled,
3566 * according to register description and PRM.
3567 */
3568 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3569 assert_pipe_disabled(dev_priv, crtc->pipe);
3570
3571 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3572 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3573
3574 /* Border color in case we don't scale up to the full screen. Black by
3575 * default, change to something else for debugging. */
3576 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3577}
3578
3579static void valleyview_crtc_enable(struct drm_crtc *crtc)
3580{
3581 struct drm_device *dev = crtc->dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3584 struct intel_encoder *encoder;
3585 int pipe = intel_crtc->pipe;
3586 int plane = intel_crtc->plane;
3587
3588 WARN_ON(!crtc->enabled);
3589
3590 if (intel_crtc->active)
3591 return;
3592
3593 intel_crtc->active = true;
3594 intel_update_watermarks(dev);
3595
3596 mutex_lock(&dev_priv->dpio_lock);
3597
3598 for_each_encoder_on_crtc(dev, crtc, encoder)
3599 if (encoder->pre_pll_enable)
3600 encoder->pre_pll_enable(encoder);
3601
3602 intel_enable_pll(dev_priv, pipe);
3603
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_enable)
3606 encoder->pre_enable(encoder);
3607
3608 /* VLV wants encoder enabling _before_ the pipe is up. */
3609 for_each_encoder_on_crtc(dev, crtc, encoder)
3610 encoder->enable(encoder);
3611
3612 i9xx_pfit_enable(intel_crtc);
3613
3614 intel_crtc_load_lut(crtc);
3615
3616 intel_enable_pipe(dev_priv, pipe, false);
3617 intel_enable_plane(dev_priv, plane, pipe);
3618 intel_enable_planes(crtc);
3619 intel_crtc_update_cursor(crtc, true);
3620
3621 intel_update_fbc(dev);
3622
3623 mutex_unlock(&dev_priv->dpio_lock);
3624}
3625
3688static void i9xx_crtc_enable(struct drm_crtc *crtc) 3626static void i9xx_crtc_enable(struct drm_crtc *crtc)
3689{ 3627{
3690 struct drm_device *dev = crtc->dev; 3628 struct drm_device *dev = crtc->dev;
@@ -3708,17 +3646,22 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
3708 if (encoder->pre_enable) 3646 if (encoder->pre_enable)
3709 encoder->pre_enable(encoder); 3647 encoder->pre_enable(encoder);
3710 3648
3649 i9xx_pfit_enable(intel_crtc);
3650
3651 intel_crtc_load_lut(crtc);
3652
3711 intel_enable_pipe(dev_priv, pipe, false); 3653 intel_enable_pipe(dev_priv, pipe, false);
3712 intel_enable_plane(dev_priv, plane, pipe); 3654 intel_enable_plane(dev_priv, plane, pipe);
3655 intel_enable_planes(crtc);
3656 /* The fixup needs to happen before cursor is enabled */
3713 if (IS_G4X(dev)) 3657 if (IS_G4X(dev))
3714 g4x_fixup_plane(dev_priv, pipe); 3658 g4x_fixup_plane(dev_priv, pipe);
3715 3659 intel_crtc_update_cursor(crtc, true);
3716 intel_crtc_load_lut(crtc);
3717 intel_update_fbc(dev);
3718 3660
3719 /* Give the overlay scaler a chance to enable if it's on this pipe */ 3661 /* Give the overlay scaler a chance to enable if it's on this pipe */
3720 intel_crtc_dpms_overlay(intel_crtc, true); 3662 intel_crtc_dpms_overlay(intel_crtc, true);
3721 intel_crtc_update_cursor(crtc, true); 3663
3664 intel_update_fbc(dev);
3722 3665
3723 for_each_encoder_on_crtc(dev, crtc, encoder) 3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->enable(encoder); 3667 encoder->enable(encoder);
@@ -3728,20 +3671,15 @@ static void i9xx_pfit_disable(struct intel_crtc *crtc)
3728{ 3671{
3729 struct drm_device *dev = crtc->base.dev; 3672 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private; 3673 struct drm_i915_private *dev_priv = dev->dev_private;
3731 enum pipe pipe;
3732 uint32_t pctl = I915_READ(PFIT_CONTROL);
3733 3674
3734 assert_pipe_disabled(dev_priv, crtc->pipe); 3675 if (!crtc->config.gmch_pfit.control)
3676 return;
3735 3677
3736 if (INTEL_INFO(dev)->gen >= 4) 3678 assert_pipe_disabled(dev_priv, crtc->pipe);
3737 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3738 else
3739 pipe = PIPE_B;
3740 3679
3741 if (pipe == crtc->pipe) { 3680 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3742 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl); 3681 I915_READ(PFIT_CONTROL));
3743 I915_WRITE(PFIT_CONTROL, 0); 3682 I915_WRITE(PFIT_CONTROL, 0);
3744 }
3745} 3683}
3746 3684
3747static void i9xx_crtc_disable(struct drm_crtc *crtc) 3685static void i9xx_crtc_disable(struct drm_crtc *crtc)
@@ -3762,17 +3700,23 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
3762 /* Give the overlay scaler a chance to disable if it's on this pipe */ 3700 /* Give the overlay scaler a chance to disable if it's on this pipe */
3763 intel_crtc_wait_for_pending_flips(crtc); 3701 intel_crtc_wait_for_pending_flips(crtc);
3764 drm_vblank_off(dev, pipe); 3702 drm_vblank_off(dev, pipe);
3765 intel_crtc_dpms_overlay(intel_crtc, false);
3766 intel_crtc_update_cursor(crtc, false);
3767 3703
3768 if (dev_priv->cfb_plane == plane) 3704 if (dev_priv->cfb_plane == plane)
3769 intel_disable_fbc(dev); 3705 intel_disable_fbc(dev);
3770 3706
3707 intel_crtc_dpms_overlay(intel_crtc, false);
3708 intel_crtc_update_cursor(crtc, false);
3709 intel_disable_planes(crtc);
3771 intel_disable_plane(dev_priv, plane, pipe); 3710 intel_disable_plane(dev_priv, plane, pipe);
3711
3772 intel_disable_pipe(dev_priv, pipe); 3712 intel_disable_pipe(dev_priv, pipe);
3773 3713
3774 i9xx_pfit_disable(intel_crtc); 3714 i9xx_pfit_disable(intel_crtc);
3775 3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->post_disable)
3718 encoder->post_disable(encoder);
3719
3776 intel_disable_pll(dev_priv, pipe); 3720 intel_disable_pll(dev_priv, pipe);
3777 3721
3778 intel_crtc->active = false; 3722 intel_crtc->active = false;
@@ -3845,8 +3789,8 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
3845 /* crtc should still be enabled when we disable it. */ 3789 /* crtc should still be enabled when we disable it. */
3846 WARN_ON(!crtc->enabled); 3790 WARN_ON(!crtc->enabled);
3847 3791
3848 intel_crtc->eld_vld = false;
3849 dev_priv->display.crtc_disable(crtc); 3792 dev_priv->display.crtc_disable(crtc);
3793 intel_crtc->eld_vld = false;
3850 intel_crtc_update_sarea(crtc, false); 3794 intel_crtc_update_sarea(crtc, false);
3851 dev_priv->display.off(crtc); 3795 dev_priv->display.off(crtc);
3852 3796
@@ -3977,17 +3921,131 @@ bool intel_connector_get_hw_state(struct intel_connector *connector)
3977 return encoder->get_hw_state(encoder, &pipe); 3921 return encoder->get_hw_state(encoder, &pipe);
3978} 3922}
3979 3923
3980static bool intel_crtc_compute_config(struct drm_crtc *crtc, 3924static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3981 struct intel_crtc_config *pipe_config) 3925 struct intel_crtc_config *pipe_config)
3982{ 3926{
3983 struct drm_device *dev = crtc->dev; 3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *pipe_B_crtc =
3929 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3930
3931 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3932 pipe_name(pipe), pipe_config->fdi_lanes);
3933 if (pipe_config->fdi_lanes > 4) {
3934 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3935 pipe_name(pipe), pipe_config->fdi_lanes);
3936 return false;
3937 }
3938
3939 if (IS_HASWELL(dev)) {
3940 if (pipe_config->fdi_lanes > 2) {
3941 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3942 pipe_config->fdi_lanes);
3943 return false;
3944 } else {
3945 return true;
3946 }
3947 }
3948
3949 if (INTEL_INFO(dev)->num_pipes == 2)
3950 return true;
3951
3952 /* Ivybridge 3 pipe is really complicated */
3953 switch (pipe) {
3954 case PIPE_A:
3955 return true;
3956 case PIPE_B:
3957 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3958 pipe_config->fdi_lanes > 2) {
3959 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3960 pipe_name(pipe), pipe_config->fdi_lanes);
3961 return false;
3962 }
3963 return true;
3964 case PIPE_C:
3965 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3966 pipe_B_crtc->config.fdi_lanes <= 2) {
3967 if (pipe_config->fdi_lanes > 2) {
3968 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3969 pipe_name(pipe), pipe_config->fdi_lanes);
3970 return false;
3971 }
3972 } else {
3973 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3974 return false;
3975 }
3976 return true;
3977 default:
3978 BUG();
3979 }
3980}
3981
3982#define RETRY 1
3983static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3984 struct intel_crtc_config *pipe_config)
3985{
3986 struct drm_device *dev = intel_crtc->base.dev;
3987 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3988 int lane, link_bw, fdi_dotclock;
3989 bool setup_ok, needs_recompute = false;
3990
3991retry:
3992 /* FDI is a binary signal running at ~2.7GHz, encoding
3993 * each output octet as 10 bits. The actual frequency
3994 * is stored as a divider into a 100MHz clock, and the
3995 * mode pixel clock is stored in units of 1KHz.
3996 * Hence the bw of each lane in terms of the mode signal
3997 * is:
3998 */
3999 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4000
4001 fdi_dotclock = adjusted_mode->clock;
4002 fdi_dotclock /= pipe_config->pixel_multiplier;
4003
4004 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4005 pipe_config->pipe_bpp);
4006
4007 pipe_config->fdi_lanes = lane;
4008
4009 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4010 link_bw, &pipe_config->fdi_m_n);
4011
4012 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4013 intel_crtc->pipe, pipe_config);
4014 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4015 pipe_config->pipe_bpp -= 2*3;
4016 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4017 pipe_config->pipe_bpp);
4018 needs_recompute = true;
4019 pipe_config->bw_constrained = true;
4020
4021 goto retry;
4022 }
4023
4024 if (needs_recompute)
4025 return RETRY;
4026
4027 return setup_ok ? 0 : -EINVAL;
4028}
4029
4030static void hsw_compute_ips_config(struct intel_crtc *crtc,
4031 struct intel_crtc_config *pipe_config)
4032{
4033 pipe_config->ips_enabled = i915_enable_ips &&
4034 hsw_crtc_supports_ips(crtc) &&
4035 pipe_config->pipe_bpp == 24;
4036}
4037
4038static int intel_crtc_compute_config(struct intel_crtc *crtc,
4039 struct intel_crtc_config *pipe_config)
4040{
4041 struct drm_device *dev = crtc->base.dev;
3984 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3985 4043
3986 if (HAS_PCH_SPLIT(dev)) { 4044 if (HAS_PCH_SPLIT(dev)) {
3987 /* FDI link clock is fixed at 2.7G */ 4045 /* FDI link clock is fixed at 2.7G */
3988 if (pipe_config->requested_mode.clock * 3 4046 if (pipe_config->requested_mode.clock * 3
3989 > IRONLAKE_FDI_FREQ * 4) 4047 > IRONLAKE_FDI_FREQ * 4)
3990 return false; 4048 return -EINVAL;
3991 } 4049 }
3992 4050
3993 /* All interlaced capable intel hw wants timings in frames. Note though 4051 /* All interlaced capable intel hw wants timings in frames. Note though
@@ -3996,12 +4054,12 @@ static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3996 if (!pipe_config->timings_set) 4054 if (!pipe_config->timings_set)
3997 drm_mode_set_crtcinfo(adjusted_mode, 0); 4055 drm_mode_set_crtcinfo(adjusted_mode, 0);
3998 4056
3999 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes 4057 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4000 * with a hsync front porch of 0. 4058 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4001 */ 4059 */
4002 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && 4060 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4003 adjusted_mode->hsync_start == adjusted_mode->hdisplay) 4061 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4004 return false; 4062 return -EINVAL;
4005 4063
4006 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { 4064 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4007 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ 4065 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
@@ -4011,7 +4069,18 @@ static bool intel_crtc_compute_config(struct drm_crtc *crtc,
4011 pipe_config->pipe_bpp = 8*3; 4069 pipe_config->pipe_bpp = 8*3;
4012 } 4070 }
4013 4071
4014 return true; 4072 if (HAS_IPS(dev))
4073 hsw_compute_ips_config(crtc, pipe_config);
4074
4075 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4076 * clock survives for now. */
4077 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4078 pipe_config->shared_dpll = crtc->config.shared_dpll;
4079
4080 if (pipe_config->has_pch_encoder)
4081 return ironlake_fdi_compute_config(crtc, pipe_config);
4082
4083 return 0;
4015} 4084}
4016 4085
4017static int valleyview_get_display_clock_speed(struct drm_device *dev) 4086static int valleyview_get_display_clock_speed(struct drm_device *dev)
@@ -4120,7 +4189,7 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4120{ 4189{
4121 if (i915_panel_use_ssc >= 0) 4190 if (i915_panel_use_ssc >= 0)
4122 return i915_panel_use_ssc != 0; 4191 return i915_panel_use_ssc != 0;
4123 return dev_priv->lvds_use_ssc 4192 return dev_priv->vbt.lvds_use_ssc
4124 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 4193 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4125} 4194}
4126 4195
@@ -4156,7 +4225,7 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4156 refclk = vlv_get_refclk(crtc); 4225 refclk = vlv_get_refclk(crtc);
4157 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4158 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 4227 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4159 refclk = dev_priv->lvds_ssc_freq * 1000; 4228 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4160 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 4229 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4161 refclk / 1000); 4230 refclk / 1000);
4162 } else if (!IS_GEN2(dev)) { 4231 } else if (!IS_GEN2(dev)) {
@@ -4168,28 +4237,14 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4168 return refclk; 4237 return refclk;
4169} 4238}
4170 4239
4171static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc) 4240static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4172{ 4241{
4173 unsigned dotclock = crtc->config.adjusted_mode.clock; 4242 return (1 << dpll->n) << 16 | dpll->m2;
4174 struct dpll *clock = &crtc->config.dpll; 4243}
4175
4176 /* SDVO TV has fixed PLL values depend on its clock range,
4177 this mirrors vbios setting. */
4178 if (dotclock >= 100000 && dotclock < 140500) {
4179 clock->p1 = 2;
4180 clock->p2 = 10;
4181 clock->n = 3;
4182 clock->m1 = 16;
4183 clock->m2 = 8;
4184 } else if (dotclock >= 140500 && dotclock <= 200000) {
4185 clock->p1 = 1;
4186 clock->p2 = 10;
4187 clock->n = 6;
4188 clock->m1 = 12;
4189 clock->m2 = 8;
4190 }
4191 4244
4192 crtc->config.clock_set = true; 4245static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4246{
4247 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4193} 4248}
4194 4249
4195static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 4250static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
@@ -4199,18 +4254,15 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4199 struct drm_i915_private *dev_priv = dev->dev_private; 4254 struct drm_i915_private *dev_priv = dev->dev_private;
4200 int pipe = crtc->pipe; 4255 int pipe = crtc->pipe;
4201 u32 fp, fp2 = 0; 4256 u32 fp, fp2 = 0;
4202 struct dpll *clock = &crtc->config.dpll;
4203 4257
4204 if (IS_PINEVIEW(dev)) { 4258 if (IS_PINEVIEW(dev)) {
4205 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; 4259 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4206 if (reduced_clock) 4260 if (reduced_clock)
4207 fp2 = (1 << reduced_clock->n) << 16 | 4261 fp2 = pnv_dpll_compute_fp(reduced_clock);
4208 reduced_clock->m1 << 8 | reduced_clock->m2;
4209 } else { 4262 } else {
4210 fp = clock->n << 16 | clock->m1 << 8 | clock->m2; 4263 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4211 if (reduced_clock) 4264 if (reduced_clock)
4212 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | 4265 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4213 reduced_clock->m2;
4214 } 4266 }
4215 4267
4216 I915_WRITE(FP0(pipe), fp); 4268 I915_WRITE(FP0(pipe), fp);
@@ -4225,6 +4277,68 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4225 } 4277 }
4226} 4278}
4227 4279
4280static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4281{
4282 u32 reg_val;
4283
4284 /*
4285 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4286 * and set it to a reasonable value instead.
4287 */
4288 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4289 reg_val &= 0xffffff00;
4290 reg_val |= 0x00000030;
4291 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4292
4293 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4294 reg_val &= 0x8cffffff;
4295 reg_val = 0x8c000000;
4296 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4297
4298 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4299 reg_val &= 0xffffff00;
4300 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4301
4302 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4303 reg_val &= 0x00ffffff;
4304 reg_val |= 0xb0000000;
4305 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4306}
4307
4308static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4309 struct intel_link_m_n *m_n)
4310{
4311 struct drm_device *dev = crtc->base.dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe = crtc->pipe;
4314
4315 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4316 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4317 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4318 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4319}
4320
4321static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4322 struct intel_link_m_n *m_n)
4323{
4324 struct drm_device *dev = crtc->base.dev;
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 int pipe = crtc->pipe;
4327 enum transcoder transcoder = crtc->config.cpu_transcoder;
4328
4329 if (INTEL_INFO(dev)->gen >= 5) {
4330 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4331 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4332 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4333 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4334 } else {
4335 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4336 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4337 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4338 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4339 }
4340}
4341
4228static void intel_dp_set_m_n(struct intel_crtc *crtc) 4342static void intel_dp_set_m_n(struct intel_crtc *crtc)
4229{ 4343{
4230 if (crtc->config.has_pch_encoder) 4344 if (crtc->config.has_pch_encoder)
@@ -4237,24 +4351,16 @@ static void vlv_update_pll(struct intel_crtc *crtc)
4237{ 4351{
4238 struct drm_device *dev = crtc->base.dev; 4352 struct drm_device *dev = crtc->base.dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private; 4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct intel_encoder *encoder;
4240 int pipe = crtc->pipe; 4355 int pipe = crtc->pipe;
4241 u32 dpll, mdiv, pdiv; 4356 u32 dpll, mdiv;
4242 u32 bestn, bestm1, bestm2, bestp1, bestp2; 4357 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4243 bool is_sdvo; 4358 bool is_hdmi;
4244 u32 temp; 4359 u32 coreclk, reg_val, dpll_md;
4245 4360
4246 mutex_lock(&dev_priv->dpio_lock); 4361 mutex_lock(&dev_priv->dpio_lock);
4247 4362
4248 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || 4363 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4249 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4250
4251 dpll = DPLL_VGA_MODE_DIS;
4252 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4253 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4254 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4255
4256 I915_WRITE(DPLL(pipe), dpll);
4257 POSTING_READ(DPLL(pipe));
4258 4364
4259 bestn = crtc->config.dpll.n; 4365 bestn = crtc->config.dpll.n;
4260 bestm1 = crtc->config.dpll.m1; 4366 bestm1 = crtc->config.dpll.m1;
@@ -4262,72 +4368,104 @@ static void vlv_update_pll(struct intel_crtc *crtc)
4262 bestp1 = crtc->config.dpll.p1; 4368 bestp1 = crtc->config.dpll.p1;
4263 bestp2 = crtc->config.dpll.p2; 4369 bestp2 = crtc->config.dpll.p2;
4264 4370
4265 /* 4371 /* See eDP HDMI DPIO driver vbios notes doc */
4266 * In Valleyview PLL and program lane counter registers are exposed 4372
4267 * through DPIO interface 4373 /* PLL B needs special handling */
4268 */ 4374 if (pipe)
4375 vlv_pllb_recal_opamp(dev_priv);
4376
4377 /* Set up Tx target for periodic Rcomp update */
4378 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4379
4380 /* Disable target IRef on PLL */
4381 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4382 reg_val &= 0x00ffffff;
4383 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4384
4385 /* Disable fast lock */
4386 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4387
4388 /* Set idtafcrecal before PLL is enabled */
4269 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 4389 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4270 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 4390 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4271 mdiv |= ((bestn << DPIO_N_SHIFT)); 4391 mdiv |= ((bestn << DPIO_N_SHIFT));
4272 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4273 mdiv |= (1 << DPIO_K_SHIFT); 4392 mdiv |= (1 << DPIO_K_SHIFT);
4393
4394 /*
4395 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4396 * but we don't support that).
4397 * Note: don't use the DAC post divider as it seems unstable.
4398 */
4399 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4400 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4401
4274 mdiv |= DPIO_ENABLE_CALIBRATION; 4402 mdiv |= DPIO_ENABLE_CALIBRATION;
4275 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); 4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4404
4405 /* Set HBR and RBR LPF coefficients */
4406 if (crtc->config.port_clock == 162000 ||
4407 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4408 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4409 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4410 0x005f0021);
4411 else
4412 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4413 0x00d0000f);
4414
4415 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4416 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4417 /* Use SSC source */
4418 if (!pipe)
4419 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4420 0x0df40000);
4421 else
4422 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4423 0x0df70000);
4424 } else { /* HDMI or VGA */
4425 /* Use bend source */
4426 if (!pipe)
4427 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4428 0x0df70000);
4429 else
4430 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4431 0x0df40000);
4432 }
4276 4433
4277 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); 4434 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4435 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4436 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4437 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4438 coreclk |= 0x01000000;
4439 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4278 4440
4279 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) | 4441 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4280 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4281 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4282 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4283 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4284 4442
4285 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); 4443 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4444 if (encoder->pre_pll_enable)
4445 encoder->pre_pll_enable(encoder);
4446
4447 /* Enable DPIO clock input */
4448 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4449 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4450 if (pipe)
4451 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4286 4452
4287 dpll |= DPLL_VCO_ENABLE; 4453 dpll |= DPLL_VCO_ENABLE;
4288 I915_WRITE(DPLL(pipe), dpll); 4454 I915_WRITE(DPLL(pipe), dpll);
4289 POSTING_READ(DPLL(pipe)); 4455 POSTING_READ(DPLL(pipe));
4456 udelay(150);
4457
4290 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) 4458 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4291 DRM_ERROR("DPLL %d failed to lock\n", pipe); 4459 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4292 4460
4293 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); 4461 dpll_md = (crtc->config.pixel_multiplier - 1)
4462 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4463 I915_WRITE(DPLL_MD(pipe), dpll_md);
4464 POSTING_READ(DPLL_MD(pipe));
4294 4465
4295 if (crtc->config.has_dp_encoder) 4466 if (crtc->config.has_dp_encoder)
4296 intel_dp_set_m_n(crtc); 4467 intel_dp_set_m_n(crtc);
4297 4468
4298 I915_WRITE(DPLL(pipe), dpll);
4299
4300 /* Wait for the clocks to stabilize. */
4301 POSTING_READ(DPLL(pipe));
4302 udelay(150);
4303
4304 temp = 0;
4305 if (is_sdvo) {
4306 temp = 0;
4307 if (crtc->config.pixel_multiplier > 1) {
4308 temp = (crtc->config.pixel_multiplier - 1)
4309 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4310 }
4311 }
4312 I915_WRITE(DPLL_MD(pipe), temp);
4313 POSTING_READ(DPLL_MD(pipe));
4314
4315 /* Now program lane control registers */
4316 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4317 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
4318 temp = 0x1000C4;
4319 if(pipe == 1)
4320 temp |= (1 << 21);
4321 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4322 }
4323
4324 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
4325 temp = 0x1000C4;
4326 if(pipe == 1)
4327 temp |= (1 << 21);
4328 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4329 }
4330
4331 mutex_unlock(&dev_priv->dpio_lock); 4469 mutex_unlock(&dev_priv->dpio_lock);
4332} 4470}
4333 4471
@@ -4355,14 +4493,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
4355 else 4493 else
4356 dpll |= DPLLB_MODE_DAC_SERIAL; 4494 dpll |= DPLLB_MODE_DAC_SERIAL;
4357 4495
4358 if (is_sdvo) { 4496 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4359 if ((crtc->config.pixel_multiplier > 1) && 4497 dpll |= (crtc->config.pixel_multiplier - 1)
4360 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) { 4498 << SDVO_MULTIPLIER_SHIFT_HIRES;
4361 dpll |= (crtc->config.pixel_multiplier - 1)
4362 << SDVO_MULTIPLIER_SHIFT_HIRES;
4363 }
4364 dpll |= DPLL_DVO_HIGH_SPEED;
4365 } 4499 }
4500
4501 if (is_sdvo)
4502 dpll |= DPLL_DVO_HIGH_SPEED;
4503
4366 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) 4504 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4367 dpll |= DPLL_DVO_HIGH_SPEED; 4505 dpll |= DPLL_DVO_HIGH_SPEED;
4368 4506
@@ -4391,12 +4529,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
4391 if (INTEL_INFO(dev)->gen >= 4) 4529 if (INTEL_INFO(dev)->gen >= 4)
4392 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 4530 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4393 4531
4394 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT)) 4532 if (crtc->config.sdvo_tv_clock)
4395 dpll |= PLL_REF_INPUT_TVCLKINBC; 4533 dpll |= PLL_REF_INPUT_TVCLKINBC;
4396 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4397 /* XXX: just matching BIOS for now */
4398 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4399 dpll |= 3;
4400 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && 4534 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4401 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4535 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4402 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
@@ -4422,15 +4556,9 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
4422 udelay(150); 4556 udelay(150);
4423 4557
4424 if (INTEL_INFO(dev)->gen >= 4) { 4558 if (INTEL_INFO(dev)->gen >= 4) {
4425 u32 temp = 0; 4559 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4426 if (is_sdvo) { 4560 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4427 temp = 0; 4561 I915_WRITE(DPLL_MD(pipe), dpll_md);
4428 if (crtc->config.pixel_multiplier > 1) {
4429 temp = (crtc->config.pixel_multiplier - 1)
4430 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4431 }
4432 }
4433 I915_WRITE(DPLL_MD(pipe), temp);
4434 } else { 4562 } else {
4435 /* The pixel multiplier can only be updated once the 4563 /* The pixel multiplier can only be updated once the
4436 * DPLL is enabled and the clocks are stable. 4564 * DPLL is enabled and the clocks are stable.
@@ -4442,7 +4570,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
4442} 4570}
4443 4571
4444static void i8xx_update_pll(struct intel_crtc *crtc, 4572static void i8xx_update_pll(struct intel_crtc *crtc,
4445 struct drm_display_mode *adjusted_mode,
4446 intel_clock_t *reduced_clock, 4573 intel_clock_t *reduced_clock,
4447 int num_connectors) 4574 int num_connectors)
4448{ 4575{
@@ -4497,20 +4624,26 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
4497 I915_WRITE(DPLL(pipe), dpll); 4624 I915_WRITE(DPLL(pipe), dpll);
4498} 4625}
4499 4626
4500static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, 4627static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4501 struct drm_display_mode *mode,
4502 struct drm_display_mode *adjusted_mode)
4503{ 4628{
4504 struct drm_device *dev = intel_crtc->base.dev; 4629 struct drm_device *dev = intel_crtc->base.dev;
4505 struct drm_i915_private *dev_priv = dev->dev_private; 4630 struct drm_i915_private *dev_priv = dev->dev_private;
4506 enum pipe pipe = intel_crtc->pipe; 4631 enum pipe pipe = intel_crtc->pipe;
4507 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 4632 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4508 uint32_t vsyncshift; 4633 struct drm_display_mode *adjusted_mode =
4634 &intel_crtc->config.adjusted_mode;
4635 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4636 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4637
4638 /* We need to be careful not to changed the adjusted mode, for otherwise
4639 * the hw state checker will get angry at the mismatch. */
4640 crtc_vtotal = adjusted_mode->crtc_vtotal;
4641 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4509 4642
4510 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 4643 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4511 /* the chip adds 2 halflines automatically */ 4644 /* the chip adds 2 halflines automatically */
4512 adjusted_mode->crtc_vtotal -= 1; 4645 crtc_vtotal -= 1;
4513 adjusted_mode->crtc_vblank_end -= 1; 4646 crtc_vblank_end -= 1;
4514 vsyncshift = adjusted_mode->crtc_hsync_start 4647 vsyncshift = adjusted_mode->crtc_hsync_start
4515 - adjusted_mode->crtc_htotal / 2; 4648 - adjusted_mode->crtc_htotal / 2;
4516 } else { 4649 } else {
@@ -4532,10 +4665,10 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4532 4665
4533 I915_WRITE(VTOTAL(cpu_transcoder), 4666 I915_WRITE(VTOTAL(cpu_transcoder),
4534 (adjusted_mode->crtc_vdisplay - 1) | 4667 (adjusted_mode->crtc_vdisplay - 1) |
4535 ((adjusted_mode->crtc_vtotal - 1) << 16)); 4668 ((crtc_vtotal - 1) << 16));
4536 I915_WRITE(VBLANK(cpu_transcoder), 4669 I915_WRITE(VBLANK(cpu_transcoder),
4537 (adjusted_mode->crtc_vblank_start - 1) | 4670 (adjusted_mode->crtc_vblank_start - 1) |
4538 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 4671 ((crtc_vblank_end - 1) << 16));
4539 I915_WRITE(VSYNC(cpu_transcoder), 4672 I915_WRITE(VSYNC(cpu_transcoder),
4540 (adjusted_mode->crtc_vsync_start - 1) | 4673 (adjusted_mode->crtc_vsync_start - 1) |
4541 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 4674 ((adjusted_mode->crtc_vsync_end - 1) << 16));
@@ -4555,13 +4688,52 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4555 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 4688 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4556} 4689}
4557 4690
4691static void intel_get_pipe_timings(struct intel_crtc *crtc,
4692 struct intel_crtc_config *pipe_config)
4693{
4694 struct drm_device *dev = crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4697 uint32_t tmp;
4698
4699 tmp = I915_READ(HTOTAL(cpu_transcoder));
4700 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4701 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4702 tmp = I915_READ(HBLANK(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HSYNC(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4708
4709 tmp = I915_READ(VTOTAL(cpu_transcoder));
4710 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4711 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4712 tmp = I915_READ(VBLANK(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VSYNC(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4718
4719 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4720 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4721 pipe_config->adjusted_mode.crtc_vtotal += 1;
4722 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4723 }
4724
4725 tmp = I915_READ(PIPESRC(crtc->pipe));
4726 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4727 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4728}
4729
4558static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 4730static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4559{ 4731{
4560 struct drm_device *dev = intel_crtc->base.dev; 4732 struct drm_device *dev = intel_crtc->base.dev;
4561 struct drm_i915_private *dev_priv = dev->dev_private; 4733 struct drm_i915_private *dev_priv = dev->dev_private;
4562 uint32_t pipeconf; 4734 uint32_t pipeconf;
4563 4735
4564 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe)); 4736 pipeconf = 0;
4565 4737
4566 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { 4738 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4567 /* Enable pixel doubling when the dot clock is > 90% of the (display) 4739 /* Enable pixel doubling when the dot clock is > 90% of the (display)
@@ -4573,26 +4745,28 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4573 if (intel_crtc->config.requested_mode.clock > 4745 if (intel_crtc->config.requested_mode.clock >
4574 dev_priv->display.get_display_clock_speed(dev) * 9 / 10) 4746 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4575 pipeconf |= PIPECONF_DOUBLE_WIDE; 4747 pipeconf |= PIPECONF_DOUBLE_WIDE;
4576 else
4577 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4578 } 4748 }
4579 4749
4580 /* default to 8bpc */ 4750 /* only g4x and later have fancy bpc/dither controls */
4581 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); 4751 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4582 if (intel_crtc->config.has_dp_encoder) { 4752 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4583 if (intel_crtc->config.dither) { 4753 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4584 pipeconf |= PIPECONF_6BPC | 4754 pipeconf |= PIPECONF_DITHER_EN |
4585 PIPECONF_DITHER_EN |
4586 PIPECONF_DITHER_TYPE_SP; 4755 PIPECONF_DITHER_TYPE_SP;
4587 }
4588 }
4589 4756
4590 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base, 4757 switch (intel_crtc->config.pipe_bpp) {
4591 INTEL_OUTPUT_EDP)) { 4758 case 18:
4592 if (intel_crtc->config.dither) { 4759 pipeconf |= PIPECONF_6BPC;
4593 pipeconf |= PIPECONF_6BPC | 4760 break;
4594 PIPECONF_ENABLE | 4761 case 24:
4595 I965_PIPECONF_ACTIVE; 4762 pipeconf |= PIPECONF_8BPC;
4763 break;
4764 case 30:
4765 pipeconf |= PIPECONF_10BPC;
4766 break;
4767 default:
4768 /* Case prevented by intel_choose_pipe_bpp_dither. */
4769 BUG();
4596 } 4770 }
4597 } 4771 }
4598 4772
@@ -4602,23 +4776,17 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4602 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 4776 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4603 } else { 4777 } else {
4604 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 4778 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4605 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4606 } 4779 }
4607 } 4780 }
4608 4781
4609 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4610 if (!IS_GEN2(dev) && 4782 if (!IS_GEN2(dev) &&
4611 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 4783 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4612 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 4784 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4613 else 4785 else
4614 pipeconf |= PIPECONF_PROGRESSIVE; 4786 pipeconf |= PIPECONF_PROGRESSIVE;
4615 4787
4616 if (IS_VALLEYVIEW(dev)) { 4788 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4617 if (intel_crtc->config.limited_color_range) 4789 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4618 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4619 else
4620 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4621 }
4622 4790
4623 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); 4791 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4624 POSTING_READ(PIPECONF(intel_crtc->pipe)); 4792 POSTING_READ(PIPECONF(intel_crtc->pipe));
@@ -4631,16 +4799,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4631 struct drm_device *dev = crtc->dev; 4799 struct drm_device *dev = crtc->dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private; 4800 struct drm_i915_private *dev_priv = dev->dev_private;
4633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4634 struct drm_display_mode *adjusted_mode =
4635 &intel_crtc->config.adjusted_mode;
4636 struct drm_display_mode *mode = &intel_crtc->config.requested_mode; 4802 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4637 int pipe = intel_crtc->pipe; 4803 int pipe = intel_crtc->pipe;
4638 int plane = intel_crtc->plane; 4804 int plane = intel_crtc->plane;
4639 int refclk, num_connectors = 0; 4805 int refclk, num_connectors = 0;
4640 intel_clock_t clock, reduced_clock; 4806 intel_clock_t clock, reduced_clock;
4641 u32 dspcntr; 4807 u32 dspcntr;
4642 bool ok, has_reduced_clock = false, is_sdvo = false; 4808 bool ok, has_reduced_clock = false;
4643 bool is_lvds = false, is_tv = false; 4809 bool is_lvds = false;
4644 struct intel_encoder *encoder; 4810 struct intel_encoder *encoder;
4645 const intel_limit_t *limit; 4811 const intel_limit_t *limit;
4646 int ret; 4812 int ret;
@@ -4650,15 +4816,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4650 case INTEL_OUTPUT_LVDS: 4816 case INTEL_OUTPUT_LVDS:
4651 is_lvds = true; 4817 is_lvds = true;
4652 break; 4818 break;
4653 case INTEL_OUTPUT_SDVO:
4654 case INTEL_OUTPUT_HDMI:
4655 is_sdvo = true;
4656 if (encoder->needs_tv_clock)
4657 is_tv = true;
4658 break;
4659 case INTEL_OUTPUT_TVOUT:
4660 is_tv = true;
4661 break;
4662 } 4819 }
4663 4820
4664 num_connectors++; 4821 num_connectors++;
@@ -4672,9 +4829,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4672 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 4829 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4673 */ 4830 */
4674 limit = intel_limit(crtc, refclk); 4831 limit = intel_limit(crtc, refclk);
4675 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 4832 ok = dev_priv->display.find_dpll(limit, crtc,
4676 &clock); 4833 intel_crtc->config.port_clock,
4677 if (!ok) { 4834 refclk, NULL, &clock);
4835 if (!ok && !intel_crtc->config.clock_set) {
4678 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 4836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4679 return -EINVAL; 4837 return -EINVAL;
4680 } 4838 }
@@ -4689,10 +4847,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4689 * by using the FP0/FP1. In such case we will disable the LVDS 4847 * by using the FP0/FP1. In such case we will disable the LVDS
4690 * downclock feature. 4848 * downclock feature.
4691 */ 4849 */
4692 has_reduced_clock = limit->find_pll(limit, crtc, 4850 has_reduced_clock =
4851 dev_priv->display.find_dpll(limit, crtc,
4693 dev_priv->lvds_downclock, 4852 dev_priv->lvds_downclock,
4694 refclk, 4853 refclk, &clock,
4695 &clock,
4696 &reduced_clock); 4854 &reduced_clock);
4697 } 4855 }
4698 /* Compat-code for transition, will disappear. */ 4856 /* Compat-code for transition, will disappear. */
@@ -4704,11 +4862,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4704 intel_crtc->config.dpll.p2 = clock.p2; 4862 intel_crtc->config.dpll.p2 = clock.p2;
4705 } 4863 }
4706 4864
4707 if (is_sdvo && is_tv)
4708 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4709
4710 if (IS_GEN2(dev)) 4865 if (IS_GEN2(dev))
4711 i8xx_update_pll(intel_crtc, adjusted_mode, 4866 i8xx_update_pll(intel_crtc,
4712 has_reduced_clock ? &reduced_clock : NULL, 4867 has_reduced_clock ? &reduced_clock : NULL,
4713 num_connectors); 4868 num_connectors);
4714 else if (IS_VALLEYVIEW(dev)) 4869 else if (IS_VALLEYVIEW(dev))
@@ -4716,7 +4871,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4716 else 4871 else
4717 i9xx_update_pll(intel_crtc, 4872 i9xx_update_pll(intel_crtc,
4718 has_reduced_clock ? &reduced_clock : NULL, 4873 has_reduced_clock ? &reduced_clock : NULL,
4719 num_connectors); 4874 num_connectors);
4720 4875
4721 /* Set up the display plane register */ 4876 /* Set up the display plane register */
4722 dspcntr = DISPPLANE_GAMMA_ENABLE; 4877 dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4728,10 +4883,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4728 dspcntr |= DISPPLANE_SEL_PIPE_B; 4883 dspcntr |= DISPPLANE_SEL_PIPE_B;
4729 } 4884 }
4730 4885
4731 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 4886 intel_set_pipe_timings(intel_crtc);
4732 drm_mode_debug_printmodeline(mode);
4733
4734 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4735 4887
4736 /* pipesrc and dspsize control the size that is scaled from, 4888 /* pipesrc and dspsize control the size that is scaled from,
4737 * which should always be the user's requested size. 4889 * which should always be the user's requested size.
@@ -4743,10 +4895,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4743 4895
4744 i9xx_set_pipeconf(intel_crtc); 4896 i9xx_set_pipeconf(intel_crtc);
4745 4897
4746 intel_enable_pipe(dev_priv, pipe, false);
4747
4748 intel_wait_for_vblank(dev, pipe);
4749
4750 I915_WRITE(DSPCNTR(plane), dspcntr); 4898 I915_WRITE(DSPCNTR(plane), dspcntr);
4751 POSTING_READ(DSPCNTR(plane)); 4899 POSTING_READ(DSPCNTR(plane));
4752 4900
@@ -4757,6 +4905,36 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4757 return ret; 4905 return ret;
4758} 4906}
4759 4907
4908static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4909 struct intel_crtc_config *pipe_config)
4910{
4911 struct drm_device *dev = crtc->base.dev;
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913 uint32_t tmp;
4914
4915 tmp = I915_READ(PFIT_CONTROL);
4916
4917 if (INTEL_INFO(dev)->gen < 4) {
4918 if (crtc->pipe != PIPE_B)
4919 return;
4920
4921 /* gen2/3 store dither state in pfit control, needs to match */
4922 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4923 } else {
4924 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4925 return;
4926 }
4927
4928 if (!(tmp & PFIT_ENABLE))
4929 return;
4930
4931 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4932 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4933 if (INTEL_INFO(dev)->gen < 5)
4934 pipe_config->gmch_pfit.lvds_border_bits =
4935 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4936}
4937
4760static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 4938static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4761 struct intel_crtc_config *pipe_config) 4939 struct intel_crtc_config *pipe_config)
4762{ 4940{
@@ -4764,10 +4942,34 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4764 struct drm_i915_private *dev_priv = dev->dev_private; 4942 struct drm_i915_private *dev_priv = dev->dev_private;
4765 uint32_t tmp; 4943 uint32_t tmp;
4766 4944
4945 pipe_config->cpu_transcoder = crtc->pipe;
4946 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4947
4767 tmp = I915_READ(PIPECONF(crtc->pipe)); 4948 tmp = I915_READ(PIPECONF(crtc->pipe));
4768 if (!(tmp & PIPECONF_ENABLE)) 4949 if (!(tmp & PIPECONF_ENABLE))
4769 return false; 4950 return false;
4770 4951
4952 intel_get_pipe_timings(crtc, pipe_config);
4953
4954 i9xx_get_pfit_config(crtc, pipe_config);
4955
4956 if (INTEL_INFO(dev)->gen >= 4) {
4957 tmp = I915_READ(DPLL_MD(crtc->pipe));
4958 pipe_config->pixel_multiplier =
4959 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4960 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4961 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4962 tmp = I915_READ(DPLL(crtc->pipe));
4963 pipe_config->pixel_multiplier =
4964 ((tmp & SDVO_MULTIPLIER_MASK)
4965 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4966 } else {
4967 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4968 * port and will be fixed up in the encoder->get_config
4969 * function. */
4970 pipe_config->pixel_multiplier = 1;
4971 }
4972
4771 return true; 4973 return true;
4772} 4974}
4773 4975
@@ -4779,7 +4981,6 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
4779 u32 val, final; 4981 u32 val, final;
4780 bool has_lvds = false; 4982 bool has_lvds = false;
4781 bool has_cpu_edp = false; 4983 bool has_cpu_edp = false;
4782 bool has_pch_edp = false;
4783 bool has_panel = false; 4984 bool has_panel = false;
4784 bool has_ck505 = false; 4985 bool has_ck505 = false;
4785 bool can_ssc = false; 4986 bool can_ssc = false;
@@ -4794,25 +4995,22 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
4794 break; 4995 break;
4795 case INTEL_OUTPUT_EDP: 4996 case INTEL_OUTPUT_EDP:
4796 has_panel = true; 4997 has_panel = true;
4797 if (intel_encoder_is_pch_edp(&encoder->base)) 4998 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
4798 has_pch_edp = true;
4799 else
4800 has_cpu_edp = true; 4999 has_cpu_edp = true;
4801 break; 5000 break;
4802 } 5001 }
4803 } 5002 }
4804 5003
4805 if (HAS_PCH_IBX(dev)) { 5004 if (HAS_PCH_IBX(dev)) {
4806 has_ck505 = dev_priv->display_clock_mode; 5005 has_ck505 = dev_priv->vbt.display_clock_mode;
4807 can_ssc = has_ck505; 5006 can_ssc = has_ck505;
4808 } else { 5007 } else {
4809 has_ck505 = false; 5008 has_ck505 = false;
4810 can_ssc = true; 5009 can_ssc = true;
4811 } 5010 }
4812 5011
4813 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", 5012 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
4814 has_panel, has_lvds, has_pch_edp, has_cpu_edp, 5013 has_panel, has_lvds, has_ck505);
4815 has_ck505);
4816 5014
4817 /* Ironlake: try to setup display ref clock before DPLL 5015 /* Ironlake: try to setup display ref clock before DPLL
4818 * enabling. This is only under driver's control after 5016 * enabling. This is only under driver's control after
@@ -5102,7 +5300,6 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
5102 struct drm_device *dev = crtc->dev; 5300 struct drm_device *dev = crtc->dev;
5103 struct drm_i915_private *dev_priv = dev->dev_private; 5301 struct drm_i915_private *dev_priv = dev->dev_private;
5104 struct intel_encoder *encoder; 5302 struct intel_encoder *encoder;
5105 struct intel_encoder *edp_encoder = NULL;
5106 int num_connectors = 0; 5303 int num_connectors = 0;
5107 bool is_lvds = false; 5304 bool is_lvds = false;
5108 5305
@@ -5111,34 +5308,28 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
5111 case INTEL_OUTPUT_LVDS: 5308 case INTEL_OUTPUT_LVDS:
5112 is_lvds = true; 5309 is_lvds = true;
5113 break; 5310 break;
5114 case INTEL_OUTPUT_EDP:
5115 edp_encoder = encoder;
5116 break;
5117 } 5311 }
5118 num_connectors++; 5312 num_connectors++;
5119 } 5313 }
5120 5314
5121 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 5315 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5122 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 5316 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5123 dev_priv->lvds_ssc_freq); 5317 dev_priv->vbt.lvds_ssc_freq);
5124 return dev_priv->lvds_ssc_freq * 1000; 5318 return dev_priv->vbt.lvds_ssc_freq * 1000;
5125 } 5319 }
5126 5320
5127 return 120000; 5321 return 120000;
5128} 5322}
5129 5323
5130static void ironlake_set_pipeconf(struct drm_crtc *crtc, 5324static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5131 struct drm_display_mode *adjusted_mode,
5132 bool dither)
5133{ 5325{
5134 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 5326 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5136 int pipe = intel_crtc->pipe; 5328 int pipe = intel_crtc->pipe;
5137 uint32_t val; 5329 uint32_t val;
5138 5330
5139 val = I915_READ(PIPECONF(pipe)); 5331 val = 0;
5140 5332
5141 val &= ~PIPECONF_BPC_MASK;
5142 switch (intel_crtc->config.pipe_bpp) { 5333 switch (intel_crtc->config.pipe_bpp) {
5143 case 18: 5334 case 18:
5144 val |= PIPECONF_6BPC; 5335 val |= PIPECONF_6BPC;
@@ -5157,20 +5348,16 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5157 BUG(); 5348 BUG();
5158 } 5349 }
5159 5350
5160 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); 5351 if (intel_crtc->config.dither)
5161 if (dither)
5162 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 5352 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5163 5353
5164 val &= ~PIPECONF_INTERLACE_MASK; 5354 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5165 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5166 val |= PIPECONF_INTERLACED_ILK; 5355 val |= PIPECONF_INTERLACED_ILK;
5167 else 5356 else
5168 val |= PIPECONF_PROGRESSIVE; 5357 val |= PIPECONF_PROGRESSIVE;
5169 5358
5170 if (intel_crtc->config.limited_color_range) 5359 if (intel_crtc->config.limited_color_range)
5171 val |= PIPECONF_COLOR_RANGE_SELECT; 5360 val |= PIPECONF_COLOR_RANGE_SELECT;
5172 else
5173 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5174 5361
5175 I915_WRITE(PIPECONF(pipe), val); 5362 I915_WRITE(PIPECONF(pipe), val);
5176 POSTING_READ(PIPECONF(pipe)); 5363 POSTING_READ(PIPECONF(pipe));
@@ -5240,33 +5427,31 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
5240 } 5427 }
5241} 5428}
5242 5429
5243static void haswell_set_pipeconf(struct drm_crtc *crtc, 5430static void haswell_set_pipeconf(struct drm_crtc *crtc)
5244 struct drm_display_mode *adjusted_mode,
5245 bool dither)
5246{ 5431{
5247 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 5432 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 5434 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5250 uint32_t val; 5435 uint32_t val;
5251 5436
5252 val = I915_READ(PIPECONF(cpu_transcoder)); 5437 val = 0;
5253 5438
5254 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); 5439 if (intel_crtc->config.dither)
5255 if (dither)
5256 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 5440 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5257 5441
5258 val &= ~PIPECONF_INTERLACE_MASK_HSW; 5442 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5259 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5260 val |= PIPECONF_INTERLACED_ILK; 5443 val |= PIPECONF_INTERLACED_ILK;
5261 else 5444 else
5262 val |= PIPECONF_PROGRESSIVE; 5445 val |= PIPECONF_PROGRESSIVE;
5263 5446
5264 I915_WRITE(PIPECONF(cpu_transcoder), val); 5447 I915_WRITE(PIPECONF(cpu_transcoder), val);
5265 POSTING_READ(PIPECONF(cpu_transcoder)); 5448 POSTING_READ(PIPECONF(cpu_transcoder));
5449
5450 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5451 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5266} 5452}
5267 5453
5268static bool ironlake_compute_clocks(struct drm_crtc *crtc, 5454static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5269 struct drm_display_mode *adjusted_mode,
5270 intel_clock_t *clock, 5455 intel_clock_t *clock,
5271 bool *has_reduced_clock, 5456 bool *has_reduced_clock,
5272 intel_clock_t *reduced_clock) 5457 intel_clock_t *reduced_clock)
@@ -5276,22 +5461,13 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5276 struct intel_encoder *intel_encoder; 5461 struct intel_encoder *intel_encoder;
5277 int refclk; 5462 int refclk;
5278 const intel_limit_t *limit; 5463 const intel_limit_t *limit;
5279 bool ret, is_sdvo = false, is_tv = false, is_lvds = false; 5464 bool ret, is_lvds = false;
5280 5465
5281 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5466 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5282 switch (intel_encoder->type) { 5467 switch (intel_encoder->type) {
5283 case INTEL_OUTPUT_LVDS: 5468 case INTEL_OUTPUT_LVDS:
5284 is_lvds = true; 5469 is_lvds = true;
5285 break; 5470 break;
5286 case INTEL_OUTPUT_SDVO:
5287 case INTEL_OUTPUT_HDMI:
5288 is_sdvo = true;
5289 if (intel_encoder->needs_tv_clock)
5290 is_tv = true;
5291 break;
5292 case INTEL_OUTPUT_TVOUT:
5293 is_tv = true;
5294 break;
5295 } 5471 }
5296 } 5472 }
5297 5473
@@ -5303,8 +5479,9 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5303 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 5479 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5304 */ 5480 */
5305 limit = intel_limit(crtc, refclk); 5481 limit = intel_limit(crtc, refclk);
5306 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 5482 ret = dev_priv->display.find_dpll(limit, crtc,
5307 clock); 5483 to_intel_crtc(crtc)->config.port_clock,
5484 refclk, NULL, clock);
5308 if (!ret) 5485 if (!ret)
5309 return false; 5486 return false;
5310 5487
@@ -5315,16 +5492,13 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5315 * by using the FP0/FP1. In such case we will disable the LVDS 5492 * by using the FP0/FP1. In such case we will disable the LVDS
5316 * downclock feature. 5493 * downclock feature.
5317 */ 5494 */
5318 *has_reduced_clock = limit->find_pll(limit, crtc, 5495 *has_reduced_clock =
5319 dev_priv->lvds_downclock, 5496 dev_priv->display.find_dpll(limit, crtc,
5320 refclk, 5497 dev_priv->lvds_downclock,
5321 clock, 5498 refclk, clock,
5322 reduced_clock); 5499 reduced_clock);
5323 } 5500 }
5324 5501
5325 if (is_sdvo && is_tv)
5326 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5327
5328 return true; 5502 return true;
5329} 5503}
5330 5504
@@ -5346,65 +5520,25 @@ static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5346 POSTING_READ(SOUTH_CHICKEN1); 5520 POSTING_READ(SOUTH_CHICKEN1);
5347} 5521}
5348 5522
5349static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) 5523static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5350{ 5524{
5351 struct drm_device *dev = intel_crtc->base.dev; 5525 struct drm_device *dev = intel_crtc->base.dev;
5352 struct drm_i915_private *dev_priv = dev->dev_private; 5526 struct drm_i915_private *dev_priv = dev->dev_private;
5353 struct intel_crtc *pipe_B_crtc =
5354 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5355
5356 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5357 intel_crtc->pipe, intel_crtc->fdi_lanes);
5358 if (intel_crtc->fdi_lanes > 4) {
5359 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5360 intel_crtc->pipe, intel_crtc->fdi_lanes);
5361 /* Clamp lanes to avoid programming the hw with bogus values. */
5362 intel_crtc->fdi_lanes = 4;
5363
5364 return false;
5365 }
5366
5367 if (INTEL_INFO(dev)->num_pipes == 2)
5368 return true;
5369 5527
5370 switch (intel_crtc->pipe) { 5528 switch (intel_crtc->pipe) {
5371 case PIPE_A: 5529 case PIPE_A:
5372 return true; 5530 break;
5373 case PIPE_B: 5531 case PIPE_B:
5374 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && 5532 if (intel_crtc->config.fdi_lanes > 2)
5375 intel_crtc->fdi_lanes > 2) {
5376 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5377 intel_crtc->pipe, intel_crtc->fdi_lanes);
5378 /* Clamp lanes to avoid programming the hw with bogus values. */
5379 intel_crtc->fdi_lanes = 2;
5380
5381 return false;
5382 }
5383
5384 if (intel_crtc->fdi_lanes > 2)
5385 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); 5533 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5386 else 5534 else
5387 cpt_enable_fdi_bc_bifurcation(dev); 5535 cpt_enable_fdi_bc_bifurcation(dev);
5388 5536
5389 return true; 5537 break;
5390 case PIPE_C: 5538 case PIPE_C:
5391 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5392 if (intel_crtc->fdi_lanes > 2) {
5393 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5394 intel_crtc->pipe, intel_crtc->fdi_lanes);
5395 /* Clamp lanes to avoid programming the hw with bogus values. */
5396 intel_crtc->fdi_lanes = 2;
5397
5398 return false;
5399 }
5400 } else {
5401 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5402 return false;
5403 }
5404
5405 cpt_enable_fdi_bc_bifurcation(dev); 5539 cpt_enable_fdi_bc_bifurcation(dev);
5406 5540
5407 return true; 5541 break;
5408 default: 5542 default:
5409 BUG(); 5543 BUG();
5410 } 5544 }
@@ -5421,78 +5555,13 @@ int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5421 return bps / (link_bw * 8) + 1; 5555 return bps / (link_bw * 8) + 1;
5422} 5556}
5423 5557
5424void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, 5558static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5425 struct intel_link_m_n *m_n)
5426{ 5559{
5427 struct drm_device *dev = crtc->base.dev; 5560 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5428 struct drm_i915_private *dev_priv = dev->dev_private;
5429 int pipe = crtc->pipe;
5430
5431 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5432 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5433 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5434 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5435}
5436
5437void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5438 struct intel_link_m_n *m_n)
5439{
5440 struct drm_device *dev = crtc->base.dev;
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442 int pipe = crtc->pipe;
5443 enum transcoder transcoder = crtc->config.cpu_transcoder;
5444
5445 if (INTEL_INFO(dev)->gen >= 5) {
5446 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5447 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5448 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5449 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5450 } else {
5451 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5452 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5453 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5454 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5455 }
5456}
5457
5458static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5459{
5460 struct drm_device *dev = crtc->dev;
5461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5462 struct drm_display_mode *adjusted_mode =
5463 &intel_crtc->config.adjusted_mode;
5464 struct intel_link_m_n m_n = {0};
5465 int target_clock, lane, link_bw;
5466
5467 /* FDI is a binary signal running at ~2.7GHz, encoding
5468 * each output octet as 10 bits. The actual frequency
5469 * is stored as a divider into a 100MHz clock, and the
5470 * mode pixel clock is stored in units of 1KHz.
5471 * Hence the bw of each lane in terms of the mode signal
5472 * is:
5473 */
5474 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5475
5476 if (intel_crtc->config.pixel_target_clock)
5477 target_clock = intel_crtc->config.pixel_target_clock;
5478 else
5479 target_clock = adjusted_mode->clock;
5480
5481 lane = ironlake_get_lanes_required(target_clock, link_bw,
5482 intel_crtc->config.pipe_bpp);
5483
5484 intel_crtc->fdi_lanes = lane;
5485
5486 if (intel_crtc->config.pixel_multiplier > 1)
5487 link_bw *= intel_crtc->config.pixel_multiplier;
5488 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5489 link_bw, &m_n);
5490
5491 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5492} 5561}
5493 5562
5494static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 5563static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5495 intel_clock_t *clock, u32 *fp, 5564 u32 *fp,
5496 intel_clock_t *reduced_clock, u32 *fp2) 5565 intel_clock_t *reduced_clock, u32 *fp2)
5497{ 5566{
5498 struct drm_crtc *crtc = &intel_crtc->base; 5567 struct drm_crtc *crtc = &intel_crtc->base;
@@ -5501,7 +5570,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5501 struct intel_encoder *intel_encoder; 5570 struct intel_encoder *intel_encoder;
5502 uint32_t dpll; 5571 uint32_t dpll;
5503 int factor, num_connectors = 0; 5572 int factor, num_connectors = 0;
5504 bool is_lvds = false, is_sdvo = false, is_tv = false; 5573 bool is_lvds = false, is_sdvo = false;
5505 5574
5506 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5575 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5507 switch (intel_encoder->type) { 5576 switch (intel_encoder->type) {
@@ -5511,11 +5580,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5511 case INTEL_OUTPUT_SDVO: 5580 case INTEL_OUTPUT_SDVO:
5512 case INTEL_OUTPUT_HDMI: 5581 case INTEL_OUTPUT_HDMI:
5513 is_sdvo = true; 5582 is_sdvo = true;
5514 if (intel_encoder->needs_tv_clock)
5515 is_tv = true;
5516 break;
5517 case INTEL_OUTPUT_TVOUT:
5518 is_tv = true;
5519 break; 5583 break;
5520 } 5584 }
5521 5585
@@ -5526,13 +5590,13 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5526 factor = 21; 5590 factor = 21;
5527 if (is_lvds) { 5591 if (is_lvds) {
5528 if ((intel_panel_use_ssc(dev_priv) && 5592 if ((intel_panel_use_ssc(dev_priv) &&
5529 dev_priv->lvds_ssc_freq == 100) || 5593 dev_priv->vbt.lvds_ssc_freq == 100) ||
5530 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) 5594 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5531 factor = 25; 5595 factor = 25;
5532 } else if (is_sdvo && is_tv) 5596 } else if (intel_crtc->config.sdvo_tv_clock)
5533 factor = 20; 5597 factor = 20;
5534 5598
5535 if (clock->m < factor * clock->n) 5599 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5536 *fp |= FP_CB_TUNE; 5600 *fp |= FP_CB_TUNE;
5537 5601
5538 if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) 5602 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
@@ -5544,23 +5608,21 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5544 dpll |= DPLLB_MODE_LVDS; 5608 dpll |= DPLLB_MODE_LVDS;
5545 else 5609 else
5546 dpll |= DPLLB_MODE_DAC_SERIAL; 5610 dpll |= DPLLB_MODE_DAC_SERIAL;
5547 if (is_sdvo) { 5611
5548 if (intel_crtc->config.pixel_multiplier > 1) { 5612 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5549 dpll |= (intel_crtc->config.pixel_multiplier - 1) 5613 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5550 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 5614
5551 } 5615 if (is_sdvo)
5552 dpll |= DPLL_DVO_HIGH_SPEED; 5616 dpll |= DPLL_DVO_HIGH_SPEED;
5553 } 5617 if (intel_crtc->config.has_dp_encoder)
5554 if (intel_crtc->config.has_dp_encoder &&
5555 intel_crtc->config.has_pch_encoder)
5556 dpll |= DPLL_DVO_HIGH_SPEED; 5618 dpll |= DPLL_DVO_HIGH_SPEED;
5557 5619
5558 /* compute bitmask from p1 value */ 5620 /* compute bitmask from p1 value */
5559 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 5621 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5560 /* also FPA1 */ 5622 /* also FPA1 */
5561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 5623 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5562 5624
5563 switch (clock->p2) { 5625 switch (intel_crtc->config.dpll.p2) {
5564 case 5: 5626 case 5:
5565 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 5627 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5566 break; 5628 break;
@@ -5575,18 +5637,12 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5575 break; 5637 break;
5576 } 5638 }
5577 5639
5578 if (is_sdvo && is_tv) 5640 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5579 dpll |= PLL_REF_INPUT_TVCLKINBC;
5580 else if (is_tv)
5581 /* XXX: just matching BIOS for now */
5582 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5583 dpll |= 3;
5584 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5585 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 5641 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5586 else 5642 else
5587 dpll |= PLL_REF_INPUT_DREFCLK; 5643 dpll |= PLL_REF_INPUT_DREFCLK;
5588 5644
5589 return dpll; 5645 return dpll | DPLL_VCO_ENABLE;
5590} 5646}
5591 5647
5592static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 5648static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
@@ -5596,19 +5652,16 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5596 struct drm_device *dev = crtc->dev; 5652 struct drm_device *dev = crtc->dev;
5597 struct drm_i915_private *dev_priv = dev->dev_private; 5653 struct drm_i915_private *dev_priv = dev->dev_private;
5598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5599 struct drm_display_mode *adjusted_mode =
5600 &intel_crtc->config.adjusted_mode;
5601 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5602 int pipe = intel_crtc->pipe; 5655 int pipe = intel_crtc->pipe;
5603 int plane = intel_crtc->plane; 5656 int plane = intel_crtc->plane;
5604 int num_connectors = 0; 5657 int num_connectors = 0;
5605 intel_clock_t clock, reduced_clock; 5658 intel_clock_t clock, reduced_clock;
5606 u32 dpll, fp = 0, fp2 = 0; 5659 u32 dpll = 0, fp = 0, fp2 = 0;
5607 bool ok, has_reduced_clock = false; 5660 bool ok, has_reduced_clock = false;
5608 bool is_lvds = false; 5661 bool is_lvds = false;
5609 struct intel_encoder *encoder; 5662 struct intel_encoder *encoder;
5663 struct intel_shared_dpll *pll;
5610 int ret; 5664 int ret;
5611 bool dither, fdi_config_ok;
5612 5665
5613 for_each_encoder_on_crtc(dev, crtc, encoder) { 5666 for_each_encoder_on_crtc(dev, crtc, encoder) {
5614 switch (encoder->type) { 5667 switch (encoder->type) {
@@ -5623,11 +5676,9 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5623 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), 5676 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5624 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); 5677 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5625 5678
5626 intel_crtc->config.cpu_transcoder = pipe; 5679 ok = ironlake_compute_clocks(crtc, &clock,
5627
5628 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5629 &has_reduced_clock, &reduced_clock); 5680 &has_reduced_clock, &reduced_clock);
5630 if (!ok) { 5681 if (!ok && !intel_crtc->config.clock_set) {
5631 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 5682 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5632 return -EINVAL; 5683 return -EINVAL;
5633 } 5684 }
@@ -5643,34 +5694,31 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5643 /* Ensure that the cursor is valid for the new mode before changing... */ 5694 /* Ensure that the cursor is valid for the new mode before changing... */
5644 intel_crtc_update_cursor(crtc, true); 5695 intel_crtc_update_cursor(crtc, true);
5645 5696
5646 /* determine panel color depth */
5647 dither = intel_crtc->config.dither;
5648 if (is_lvds && dev_priv->lvds_dither)
5649 dither = true;
5650
5651 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5652 if (has_reduced_clock)
5653 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5654 reduced_clock.m2;
5655
5656 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5657 has_reduced_clock ? &fp2 : NULL);
5658
5659 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5660 drm_mode_debug_printmodeline(mode);
5661
5662 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 5697 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5663 if (intel_crtc->config.has_pch_encoder) { 5698 if (intel_crtc->config.has_pch_encoder) {
5664 struct intel_pch_pll *pll; 5699 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5700 if (has_reduced_clock)
5701 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5702
5703 dpll = ironlake_compute_dpll(intel_crtc,
5704 &fp, &reduced_clock,
5705 has_reduced_clock ? &fp2 : NULL);
5706
5707 intel_crtc->config.dpll_hw_state.dpll = dpll;
5708 intel_crtc->config.dpll_hw_state.fp0 = fp;
5709 if (has_reduced_clock)
5710 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5711 else
5712 intel_crtc->config.dpll_hw_state.fp1 = fp;
5665 5713
5666 pll = intel_get_pch_pll(intel_crtc, dpll, fp); 5714 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5667 if (pll == NULL) { 5715 if (pll == NULL) {
5668 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", 5716 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5669 pipe); 5717 pipe_name(pipe));
5670 return -EINVAL; 5718 return -EINVAL;
5671 } 5719 }
5672 } else 5720 } else
5673 intel_put_pch_pll(intel_crtc); 5721 intel_put_shared_dpll(intel_crtc);
5674 5722
5675 if (intel_crtc->config.has_dp_encoder) 5723 if (intel_crtc->config.has_dp_encoder)
5676 intel_dp_set_m_n(intel_crtc); 5724 intel_dp_set_m_n(intel_crtc);
@@ -5679,11 +5727,18 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5679 if (encoder->pre_pll_enable) 5727 if (encoder->pre_pll_enable)
5680 encoder->pre_pll_enable(encoder); 5728 encoder->pre_pll_enable(encoder);
5681 5729
5682 if (intel_crtc->pch_pll) { 5730 if (is_lvds && has_reduced_clock && i915_powersave)
5683 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); 5731 intel_crtc->lowfreq_avail = true;
5732 else
5733 intel_crtc->lowfreq_avail = false;
5734
5735 if (intel_crtc->config.has_pch_encoder) {
5736 pll = intel_crtc_to_shared_dpll(intel_crtc);
5737
5738 I915_WRITE(PCH_DPLL(pll->id), dpll);
5684 5739
5685 /* Wait for the clocks to stabilize. */ 5740 /* Wait for the clocks to stabilize. */
5686 POSTING_READ(intel_crtc->pch_pll->pll_reg); 5741 POSTING_READ(PCH_DPLL(pll->id));
5687 udelay(150); 5742 udelay(150);
5688 5743
5689 /* The pixel multiplier can only be updated once the 5744 /* The pixel multiplier can only be updated once the
@@ -5691,32 +5746,25 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5691 * 5746 *
5692 * So write it again. 5747 * So write it again.
5693 */ 5748 */
5694 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); 5749 I915_WRITE(PCH_DPLL(pll->id), dpll);
5695 }
5696 5750
5697 intel_crtc->lowfreq_avail = false; 5751 if (has_reduced_clock)
5698 if (intel_crtc->pch_pll) { 5752 I915_WRITE(PCH_FP1(pll->id), fp2);
5699 if (is_lvds && has_reduced_clock && i915_powersave) { 5753 else
5700 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); 5754 I915_WRITE(PCH_FP1(pll->id), fp);
5701 intel_crtc->lowfreq_avail = true;
5702 } else {
5703 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5704 }
5705 } 5755 }
5706 5756
5707 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5757 intel_set_pipe_timings(intel_crtc);
5708 5758
5709 /* Note, this also computes intel_crtc->fdi_lanes which is used below in 5759 if (intel_crtc->config.has_pch_encoder) {
5710 * ironlake_check_fdi_lanes. */ 5760 intel_cpu_transcoder_set_m_n(intel_crtc,
5711 intel_crtc->fdi_lanes = 0; 5761 &intel_crtc->config.fdi_m_n);
5712 if (intel_crtc->config.has_pch_encoder) 5762 }
5713 ironlake_fdi_set_m_n(crtc);
5714
5715 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5716 5763
5717 ironlake_set_pipeconf(crtc, adjusted_mode, dither); 5764 if (IS_IVYBRIDGE(dev))
5765 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5718 5766
5719 intel_wait_for_vblank(dev, pipe); 5767 ironlake_set_pipeconf(crtc);
5720 5768
5721 /* Set up the display plane register */ 5769 /* Set up the display plane register */
5722 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); 5770 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
@@ -5726,9 +5774,46 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5726 5774
5727 intel_update_watermarks(dev); 5775 intel_update_watermarks(dev);
5728 5776
5729 intel_update_linetime_watermarks(dev, pipe, adjusted_mode); 5777 return ret;
5778}
5730 5779
5731 return fdi_config_ok ? ret : -EINVAL; 5780static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5781 struct intel_crtc_config *pipe_config)
5782{
5783 struct drm_device *dev = crtc->base.dev;
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5785 enum transcoder transcoder = pipe_config->cpu_transcoder;
5786
5787 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5788 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5789 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5790 & ~TU_SIZE_MASK;
5791 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5792 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5793 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5794}
5795
5796static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5797 struct intel_crtc_config *pipe_config)
5798{
5799 struct drm_device *dev = crtc->base.dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 uint32_t tmp;
5802
5803 tmp = I915_READ(PF_CTL(crtc->pipe));
5804
5805 if (tmp & PF_ENABLE) {
5806 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5807 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5808
5809 /* We currently do not free assignements of panel fitters on
5810 * ivb/hsw (since we don't use the higher upscaling modes which
5811 * differentiates them) so just WARN about this case for now. */
5812 if (IS_GEN7(dev)) {
5813 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5814 PF_PIPE_SEL_IVB(crtc->pipe));
5815 }
5816 }
5732} 5817}
5733 5818
5734static bool ironlake_get_pipe_config(struct intel_crtc *crtc, 5819static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
@@ -5738,42 +5823,67 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5738 struct drm_i915_private *dev_priv = dev->dev_private; 5823 struct drm_i915_private *dev_priv = dev->dev_private;
5739 uint32_t tmp; 5824 uint32_t tmp;
5740 5825
5826 pipe_config->cpu_transcoder = crtc->pipe;
5827 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5828
5741 tmp = I915_READ(PIPECONF(crtc->pipe)); 5829 tmp = I915_READ(PIPECONF(crtc->pipe));
5742 if (!(tmp & PIPECONF_ENABLE)) 5830 if (!(tmp & PIPECONF_ENABLE))
5743 return false; 5831 return false;
5744 5832
5745 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) 5833 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5834 struct intel_shared_dpll *pll;
5835
5746 pipe_config->has_pch_encoder = true; 5836 pipe_config->has_pch_encoder = true;
5747 5837
5838 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5839 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5840 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5841
5842 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5843
5844 /* XXX: Can't properly read out the pch dpll pixel multiplier
5845 * since we don't have state tracking for pch clocks yet. */
5846 pipe_config->pixel_multiplier = 1;
5847
5848 if (HAS_PCH_IBX(dev_priv->dev)) {
5849 pipe_config->shared_dpll = crtc->pipe;
5850 } else {
5851 tmp = I915_READ(PCH_DPLL_SEL);
5852 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5853 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5854 else
5855 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5856 }
5857
5858 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5859
5860 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5861 &pipe_config->dpll_hw_state));
5862 } else {
5863 pipe_config->pixel_multiplier = 1;
5864 }
5865
5866 intel_get_pipe_timings(crtc, pipe_config);
5867
5868 ironlake_get_pfit_config(crtc, pipe_config);
5869
5748 return true; 5870 return true;
5749} 5871}
5750 5872
5751static void haswell_modeset_global_resources(struct drm_device *dev) 5873static void haswell_modeset_global_resources(struct drm_device *dev)
5752{ 5874{
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5754 bool enable = false; 5875 bool enable = false;
5755 struct intel_crtc *crtc; 5876 struct intel_crtc *crtc;
5756 struct intel_encoder *encoder;
5757 5877
5758 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 5878 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5759 if (crtc->pipe != PIPE_A && crtc->base.enabled) 5879 if (!crtc->base.enabled)
5760 enable = true; 5880 continue;
5761 /* XXX: Should check for edp transcoder here, but thanks to init
5762 * sequence that's not yet available. Just in case desktop eDP
5763 * on PORT D is possible on haswell, too. */
5764 }
5765 5881
5766 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 5882 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5767 base.head) { 5883 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5768 if (encoder->type != INTEL_OUTPUT_EDP &&
5769 encoder->connectors_active)
5770 enable = true; 5884 enable = true;
5771 } 5885 }
5772 5886
5773 /* Even the eDP panel fitter is outside the always-on well. */
5774 if (dev_priv->pch_pf_size)
5775 enable = true;
5776
5777 intel_set_power_well(dev, enable); 5887 intel_set_power_well(dev, enable);
5778} 5888}
5779 5889
@@ -5784,68 +5894,28 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5784 struct drm_device *dev = crtc->dev; 5894 struct drm_device *dev = crtc->dev;
5785 struct drm_i915_private *dev_priv = dev->dev_private; 5895 struct drm_i915_private *dev_priv = dev->dev_private;
5786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5787 struct drm_display_mode *adjusted_mode =
5788 &intel_crtc->config.adjusted_mode;
5789 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5790 int pipe = intel_crtc->pipe;
5791 int plane = intel_crtc->plane; 5897 int plane = intel_crtc->plane;
5792 int num_connectors = 0;
5793 bool is_cpu_edp = false;
5794 struct intel_encoder *encoder;
5795 int ret; 5898 int ret;
5796 bool dither;
5797
5798 for_each_encoder_on_crtc(dev, crtc, encoder) {
5799 switch (encoder->type) {
5800 case INTEL_OUTPUT_EDP:
5801 if (!intel_encoder_is_pch_edp(&encoder->base))
5802 is_cpu_edp = true;
5803 break;
5804 }
5805
5806 num_connectors++;
5807 }
5808
5809 if (is_cpu_edp)
5810 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5811 else
5812 intel_crtc->config.cpu_transcoder = pipe;
5813
5814 /* We are not sure yet this won't happen. */
5815 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5816 INTEL_PCH_TYPE(dev));
5817 5899
5818 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", 5900 if (!intel_ddi_pll_mode_set(crtc))
5819 num_connectors, pipe_name(pipe));
5820
5821 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5822 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5823
5824 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5825
5826 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5827 return -EINVAL; 5901 return -EINVAL;
5828 5902
5829 /* Ensure that the cursor is valid for the new mode before changing... */ 5903 /* Ensure that the cursor is valid for the new mode before changing... */
5830 intel_crtc_update_cursor(crtc, true); 5904 intel_crtc_update_cursor(crtc, true);
5831 5905
5832 /* determine panel color depth */
5833 dither = intel_crtc->config.dither;
5834
5835 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5836 drm_mode_debug_printmodeline(mode);
5837
5838 if (intel_crtc->config.has_dp_encoder) 5906 if (intel_crtc->config.has_dp_encoder)
5839 intel_dp_set_m_n(intel_crtc); 5907 intel_dp_set_m_n(intel_crtc);
5840 5908
5841 intel_crtc->lowfreq_avail = false; 5909 intel_crtc->lowfreq_avail = false;
5842 5910
5843 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5911 intel_set_pipe_timings(intel_crtc);
5844 5912
5845 if (intel_crtc->config.has_pch_encoder) 5913 if (intel_crtc->config.has_pch_encoder) {
5846 ironlake_fdi_set_m_n(crtc); 5914 intel_cpu_transcoder_set_m_n(intel_crtc,
5915 &intel_crtc->config.fdi_m_n);
5916 }
5847 5917
5848 haswell_set_pipeconf(crtc, adjusted_mode, dither); 5918 haswell_set_pipeconf(crtc);
5849 5919
5850 intel_set_pipe_csc(crtc); 5920 intel_set_pipe_csc(crtc);
5851 5921
@@ -5857,8 +5927,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5857 5927
5858 intel_update_watermarks(dev); 5928 intel_update_watermarks(dev);
5859 5929
5860 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5861
5862 return ret; 5930 return ret;
5863} 5931}
5864 5932
@@ -5867,22 +5935,69 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5867{ 5935{
5868 struct drm_device *dev = crtc->base.dev; 5936 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private; 5937 struct drm_i915_private *dev_priv = dev->dev_private;
5938 enum intel_display_power_domain pfit_domain;
5870 uint32_t tmp; 5939 uint32_t tmp;
5871 5940
5872 tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder)); 5941 pipe_config->cpu_transcoder = crtc->pipe;
5942 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5943
5944 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5945 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5946 enum pipe trans_edp_pipe;
5947 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5948 default:
5949 WARN(1, "unknown pipe linked to edp transcoder\n");
5950 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5951 case TRANS_DDI_EDP_INPUT_A_ON:
5952 trans_edp_pipe = PIPE_A;
5953 break;
5954 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5955 trans_edp_pipe = PIPE_B;
5956 break;
5957 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5958 trans_edp_pipe = PIPE_C;
5959 break;
5960 }
5961
5962 if (trans_edp_pipe == crtc->pipe)
5963 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5964 }
5965
5966 if (!intel_display_power_enabled(dev,
5967 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5968 return false;
5969
5970 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5873 if (!(tmp & PIPECONF_ENABLE)) 5971 if (!(tmp & PIPECONF_ENABLE))
5874 return false; 5972 return false;
5875 5973
5876 /* 5974 /*
5877 * aswell has only FDI/PCH transcoder A. It is which is connected to 5975 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5878 * DDI E. So just check whether this pipe is wired to DDI E and whether 5976 * DDI E. So just check whether this pipe is wired to DDI E and whether
5879 * the PCH transcoder is on. 5977 * the PCH transcoder is on.
5880 */ 5978 */
5881 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe)); 5979 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5882 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && 5980 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5883 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) 5981 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5884 pipe_config->has_pch_encoder = true; 5982 pipe_config->has_pch_encoder = true;
5885 5983
5984 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5985 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5986 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5987
5988 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5989 }
5990
5991 intel_get_pipe_timings(crtc, pipe_config);
5992
5993 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5994 if (intel_display_power_enabled(dev, pfit_domain))
5995 ironlake_get_pfit_config(crtc, pipe_config);
5996
5997 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5998 (I915_READ(IPS_CTL) & IPS_ENABLE);
5999
6000 pipe_config->pixel_multiplier = 1;
5886 6001
5887 return true; 6002 return true;
5888} 6003}
@@ -6120,7 +6235,7 @@ static void ironlake_write_eld(struct drm_connector *connector,
6120 eldv |= IBX_ELD_VALIDB << 4; 6235 eldv |= IBX_ELD_VALIDB << 4;
6121 eldv |= IBX_ELD_VALIDB << 8; 6236 eldv |= IBX_ELD_VALIDB << 8;
6122 } else { 6237 } else {
6123 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); 6238 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6124 eldv = IBX_ELD_VALIDB << ((i - 1) * 4); 6239 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6125 } 6240 }
6126 6241
@@ -6188,16 +6303,31 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
6188 struct drm_device *dev = crtc->dev; 6303 struct drm_device *dev = crtc->dev;
6189 struct drm_i915_private *dev_priv = dev->dev_private; 6304 struct drm_i915_private *dev_priv = dev->dev_private;
6190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191 int palreg = PALETTE(intel_crtc->pipe); 6306 enum pipe pipe = intel_crtc->pipe;
6307 int palreg = PALETTE(pipe);
6192 int i; 6308 int i;
6309 bool reenable_ips = false;
6193 6310
6194 /* The clocks have to be on to load the palette. */ 6311 /* The clocks have to be on to load the palette. */
6195 if (!crtc->enabled || !intel_crtc->active) 6312 if (!crtc->enabled || !intel_crtc->active)
6196 return; 6313 return;
6197 6314
6315 if (!HAS_PCH_SPLIT(dev_priv->dev))
6316 assert_pll_enabled(dev_priv, pipe);
6317
6198 /* use legacy palette for Ironlake */ 6318 /* use legacy palette for Ironlake */
6199 if (HAS_PCH_SPLIT(dev)) 6319 if (HAS_PCH_SPLIT(dev))
6200 palreg = LGC_PALETTE(intel_crtc->pipe); 6320 palreg = LGC_PALETTE(pipe);
6321
6322 /* Workaround : Do not read or write the pipe palette/gamma data while
6323 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6324 */
6325 if (intel_crtc->config.ips_enabled &&
6326 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6327 GAMMA_MODE_MODE_SPLIT)) {
6328 hsw_disable_ips(intel_crtc);
6329 reenable_ips = true;
6330 }
6201 6331
6202 for (i = 0; i < 256; i++) { 6332 for (i = 0; i < 256; i++) {
6203 I915_WRITE(palreg + 4 * i, 6333 I915_WRITE(palreg + 4 * i,
@@ -6205,6 +6335,9 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
6205 (intel_crtc->lut_g[i] << 8) | 6335 (intel_crtc->lut_g[i] << 8) |
6206 intel_crtc->lut_b[i]); 6336 intel_crtc->lut_b[i]);
6207 } 6337 }
6338
6339 if (reenable_ips)
6340 hsw_enable_ips(intel_crtc);
6208} 6341}
6209 6342
6210static void i845_update_cursor(struct drm_crtc *crtc, u32 base) 6343static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
@@ -6451,7 +6584,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6451 intel_crtc->cursor_width = width; 6584 intel_crtc->cursor_width = width;
6452 intel_crtc->cursor_height = height; 6585 intel_crtc->cursor_height = height;
6453 6586
6454 intel_crtc_update_cursor(crtc, true); 6587 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6455 6588
6456 return 0; 6589 return 0;
6457fail_unpin: 6590fail_unpin:
@@ -6470,7 +6603,7 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6470 intel_crtc->cursor_x = x; 6603 intel_crtc->cursor_x = x;
6471 intel_crtc->cursor_y = y; 6604 intel_crtc->cursor_y = y;
6472 6605
6473 intel_crtc_update_cursor(crtc, true); 6606 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6474 6607
6475 return 0; 6608 return 0;
6476} 6609}
@@ -6791,8 +6924,10 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6791 return 0; 6924 return 0;
6792 } 6925 }
6793 6926
6794 /* XXX: Handle the 100Mhz refclk */ 6927 if (IS_PINEVIEW(dev))
6795 intel_clock(dev, 96000, &clock); 6928 pineview_clock(96000, &clock);
6929 else
6930 i9xx_clock(96000, &clock);
6796 } else { 6931 } else {
6797 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); 6932 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6798 6933
@@ -6804,9 +6939,9 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6804 if ((dpll & PLL_REF_INPUT_MASK) == 6939 if ((dpll & PLL_REF_INPUT_MASK) ==
6805 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 6940 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6806 /* XXX: might not be 66MHz */ 6941 /* XXX: might not be 66MHz */
6807 intel_clock(dev, 66000, &clock); 6942 i9xx_clock(66000, &clock);
6808 } else 6943 } else
6809 intel_clock(dev, 48000, &clock); 6944 i9xx_clock(48000, &clock);
6810 } else { 6945 } else {
6811 if (dpll & PLL_P1_DIVIDE_BY_TWO) 6946 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6812 clock.p1 = 2; 6947 clock.p1 = 2;
@@ -6819,7 +6954,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6819 else 6954 else
6820 clock.p2 = 2; 6955 clock.p2 = 2;
6821 6956
6822 intel_clock(dev, 48000, &clock); 6957 i9xx_clock(48000, &clock);
6823 } 6958 }
6824 } 6959 }
6825 6960
@@ -6950,7 +7085,8 @@ void intel_mark_idle(struct drm_device *dev)
6950 } 7085 }
6951} 7086}
6952 7087
6953void intel_mark_fb_busy(struct drm_i915_gem_object *obj) 7088void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7089 struct intel_ring_buffer *ring)
6954{ 7090{
6955 struct drm_device *dev = obj->base.dev; 7091 struct drm_device *dev = obj->base.dev;
6956 struct drm_crtc *crtc; 7092 struct drm_crtc *crtc;
@@ -6962,8 +7098,12 @@ void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6962 if (!crtc->fb) 7098 if (!crtc->fb)
6963 continue; 7099 continue;
6964 7100
6965 if (to_intel_framebuffer(crtc->fb)->obj == obj) 7101 if (to_intel_framebuffer(crtc->fb)->obj != obj)
6966 intel_increase_pllclock(crtc); 7102 continue;
7103
7104 intel_increase_pllclock(crtc);
7105 if (ring && intel_fbc_enabled(dev))
7106 ring->fbc_dirty = true;
6967 } 7107 }
6968} 7108}
6969 7109
@@ -6984,6 +7124,8 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
6984 kfree(work); 7124 kfree(work);
6985 } 7125 }
6986 7126
7127 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7128
6987 drm_crtc_cleanup(crtc); 7129 drm_crtc_cleanup(crtc);
6988 7130
6989 kfree(intel_crtc); 7131 kfree(intel_crtc);
@@ -7411,7 +7553,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
7411 goto cleanup_pending; 7553 goto cleanup_pending;
7412 7554
7413 intel_disable_fbc(dev); 7555 intel_disable_fbc(dev);
7414 intel_mark_fb_busy(obj); 7556 intel_mark_fb_busy(obj, NULL);
7415 mutex_unlock(&dev->struct_mutex); 7557 mutex_unlock(&dev->struct_mutex);
7416 7558
7417 trace_i915_flip_request(intel_crtc->plane, obj); 7559 trace_i915_flip_request(intel_crtc->plane, obj);
@@ -7442,28 +7584,6 @@ static struct drm_crtc_helper_funcs intel_helper_funcs = {
7442 .load_lut = intel_crtc_load_lut, 7584 .load_lut = intel_crtc_load_lut,
7443}; 7585};
7444 7586
7445bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7446{
7447 struct intel_encoder *other_encoder;
7448 struct drm_crtc *crtc = &encoder->new_crtc->base;
7449
7450 if (WARN_ON(!crtc))
7451 return false;
7452
7453 list_for_each_entry(other_encoder,
7454 &crtc->dev->mode_config.encoder_list,
7455 base.head) {
7456
7457 if (&other_encoder->new_crtc->base != crtc ||
7458 encoder == other_encoder)
7459 continue;
7460 else
7461 return true;
7462 }
7463
7464 return false;
7465}
7466
7467static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, 7587static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7468 struct drm_crtc *crtc) 7588 struct drm_crtc *crtc)
7469{ 7589{
@@ -7531,13 +7651,39 @@ static void intel_modeset_commit_output_state(struct drm_device *dev)
7531 } 7651 }
7532} 7652}
7533 7653
7654static void
7655connected_sink_compute_bpp(struct intel_connector * connector,
7656 struct intel_crtc_config *pipe_config)
7657{
7658 int bpp = pipe_config->pipe_bpp;
7659
7660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7661 connector->base.base.id,
7662 drm_get_connector_name(&connector->base));
7663
7664 /* Don't use an invalid EDID bpc value */
7665 if (connector->base.display_info.bpc &&
7666 connector->base.display_info.bpc * 3 < bpp) {
7667 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7668 bpp, connector->base.display_info.bpc*3);
7669 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7670 }
7671
7672 /* Clamp bpp to 8 on screens without EDID 1.4 */
7673 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7674 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7675 bpp);
7676 pipe_config->pipe_bpp = 24;
7677 }
7678}
7679
7534static int 7680static int
7535pipe_config_set_bpp(struct drm_crtc *crtc, 7681compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7536 struct drm_framebuffer *fb, 7682 struct drm_framebuffer *fb,
7537 struct intel_crtc_config *pipe_config) 7683 struct intel_crtc_config *pipe_config)
7538{ 7684{
7539 struct drm_device *dev = crtc->dev; 7685 struct drm_device *dev = crtc->base.dev;
7540 struct drm_connector *connector; 7686 struct intel_connector *connector;
7541 int bpp; 7687 int bpp;
7542 7688
7543 switch (fb->pixel_format) { 7689 switch (fb->pixel_format) {
@@ -7580,22 +7726,66 @@ pipe_config_set_bpp(struct drm_crtc *crtc,
7580 7726
7581 /* Clamp display bpp to EDID value */ 7727 /* Clamp display bpp to EDID value */
7582 list_for_each_entry(connector, &dev->mode_config.connector_list, 7728 list_for_each_entry(connector, &dev->mode_config.connector_list,
7583 head) { 7729 base.head) {
7584 if (connector->encoder && connector->encoder->crtc != crtc) 7730 if (!connector->new_encoder ||
7731 connector->new_encoder->new_crtc != crtc)
7585 continue; 7732 continue;
7586 7733
7587 /* Don't use an invalid EDID bpc value */ 7734 connected_sink_compute_bpp(connector, pipe_config);
7588 if (connector->display_info.bpc &&
7589 connector->display_info.bpc * 3 < bpp) {
7590 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7591 bpp, connector->display_info.bpc*3);
7592 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7593 }
7594 } 7735 }
7595 7736
7596 return bpp; 7737 return bpp;
7597} 7738}
7598 7739
7740static void intel_dump_pipe_config(struct intel_crtc *crtc,
7741 struct intel_crtc_config *pipe_config,
7742 const char *context)
7743{
7744 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7745 context, pipe_name(crtc->pipe));
7746
7747 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7748 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7749 pipe_config->pipe_bpp, pipe_config->dither);
7750 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7751 pipe_config->has_pch_encoder,
7752 pipe_config->fdi_lanes,
7753 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7754 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7755 pipe_config->fdi_m_n.tu);
7756 DRM_DEBUG_KMS("requested mode:\n");
7757 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7758 DRM_DEBUG_KMS("adjusted mode:\n");
7759 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7760 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7761 pipe_config->gmch_pfit.control,
7762 pipe_config->gmch_pfit.pgm_ratios,
7763 pipe_config->gmch_pfit.lvds_border_bits);
7764 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7765 pipe_config->pch_pfit.pos,
7766 pipe_config->pch_pfit.size);
7767 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7768}
7769
7770static bool check_encoder_cloning(struct drm_crtc *crtc)
7771{
7772 int num_encoders = 0;
7773 bool uncloneable_encoders = false;
7774 struct intel_encoder *encoder;
7775
7776 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7777 base.head) {
7778 if (&encoder->new_crtc->base != crtc)
7779 continue;
7780
7781 num_encoders++;
7782 if (!encoder->cloneable)
7783 uncloneable_encoders = true;
7784 }
7785
7786 return !(num_encoders > 1 && uncloneable_encoders);
7787}
7788
7599static struct intel_crtc_config * 7789static struct intel_crtc_config *
7600intel_modeset_pipe_config(struct drm_crtc *crtc, 7790intel_modeset_pipe_config(struct drm_crtc *crtc,
7601 struct drm_framebuffer *fb, 7791 struct drm_framebuffer *fb,
@@ -7605,7 +7795,13 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
7605 struct drm_encoder_helper_funcs *encoder_funcs; 7795 struct drm_encoder_helper_funcs *encoder_funcs;
7606 struct intel_encoder *encoder; 7796 struct intel_encoder *encoder;
7607 struct intel_crtc_config *pipe_config; 7797 struct intel_crtc_config *pipe_config;
7608 int plane_bpp; 7798 int plane_bpp, ret = -EINVAL;
7799 bool retry = true;
7800
7801 if (!check_encoder_cloning(crtc)) {
7802 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7803 return ERR_PTR(-EINVAL);
7804 }
7609 7805
7610 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); 7806 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7611 if (!pipe_config) 7807 if (!pipe_config)
@@ -7613,11 +7809,23 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
7613 7809
7614 drm_mode_copy(&pipe_config->adjusted_mode, mode); 7810 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7615 drm_mode_copy(&pipe_config->requested_mode, mode); 7811 drm_mode_copy(&pipe_config->requested_mode, mode);
7616 7812 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7617 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config); 7813 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7814
7815 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7816 * plane pixel format and any sink constraints into account. Returns the
7817 * source plane bpp so that dithering can be selected on mismatches
7818 * after encoders and crtc also have had their say. */
7819 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7820 fb, pipe_config);
7618 if (plane_bpp < 0) 7821 if (plane_bpp < 0)
7619 goto fail; 7822 goto fail;
7620 7823
7824encoder_retry:
7825 /* Ensure the port clock defaults are reset when retrying. */
7826 pipe_config->port_clock = 0;
7827 pipe_config->pixel_multiplier = 1;
7828
7621 /* Pass our mode to the connectors and the CRTC to give them a chance to 7829 /* Pass our mode to the connectors and the CRTC to give them a chance to
7622 * adjust it according to limitations or connector properties, and also 7830 * adjust it according to limitations or connector properties, and also
7623 * a chance to reject the mode entirely. 7831 * a chance to reject the mode entirely.
@@ -7646,11 +7854,27 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
7646 } 7854 }
7647 } 7855 }
7648 7856
7649 if (!(intel_crtc_compute_config(crtc, pipe_config))) { 7857 /* Set default port clock if not overwritten by the encoder. Needs to be
7858 * done afterwards in case the encoder adjusts the mode. */
7859 if (!pipe_config->port_clock)
7860 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7861
7862 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7863 if (ret < 0) {
7650 DRM_DEBUG_KMS("CRTC fixup failed\n"); 7864 DRM_DEBUG_KMS("CRTC fixup failed\n");
7651 goto fail; 7865 goto fail;
7652 } 7866 }
7653 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); 7867
7868 if (ret == RETRY) {
7869 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7870 ret = -EINVAL;
7871 goto fail;
7872 }
7873
7874 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7875 retry = false;
7876 goto encoder_retry;
7877 }
7654 7878
7655 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; 7879 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7656 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", 7880 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
@@ -7659,7 +7883,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
7659 return pipe_config; 7883 return pipe_config;
7660fail: 7884fail:
7661 kfree(pipe_config); 7885 kfree(pipe_config);
7662 return ERR_PTR(-EINVAL); 7886 return ERR_PTR(ret);
7663} 7887}
7664 7888
7665/* Computes which crtcs are affected and sets the relevant bits in the mask. For 7889/* Computes which crtcs are affected and sets the relevant bits in the mask. For
@@ -7755,6 +7979,9 @@ intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7755 */ 7979 */
7756 *modeset_pipes &= 1 << intel_crtc->pipe; 7980 *modeset_pipes &= 1 << intel_crtc->pipe;
7757 *prepare_pipes &= 1 << intel_crtc->pipe; 7981 *prepare_pipes &= 1 << intel_crtc->pipe;
7982
7983 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7984 *modeset_pipes, *prepare_pipes, *disable_pipes);
7758} 7985}
7759 7986
7760static bool intel_crtc_in_use(struct drm_crtc *crtc) 7987static bool intel_crtc_in_use(struct drm_crtc *crtc)
@@ -7821,31 +8048,114 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7821 list_for_each_entry((intel_crtc), \ 8048 list_for_each_entry((intel_crtc), \
7822 &(dev)->mode_config.crtc_list, \ 8049 &(dev)->mode_config.crtc_list, \
7823 base.head) \ 8050 base.head) \
7824 if (mask & (1 <<(intel_crtc)->pipe)) \ 8051 if (mask & (1 <<(intel_crtc)->pipe))
7825 8052
7826static bool 8053static bool
7827intel_pipe_config_compare(struct intel_crtc_config *current_config, 8054intel_pipe_config_compare(struct drm_device *dev,
8055 struct intel_crtc_config *current_config,
7828 struct intel_crtc_config *pipe_config) 8056 struct intel_crtc_config *pipe_config)
7829{ 8057{
7830 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) { 8058#define PIPE_CONF_CHECK_X(name) \
7831 DRM_ERROR("mismatch in has_pch_encoder " 8059 if (current_config->name != pipe_config->name) { \
7832 "(expected %i, found %i)\n", 8060 DRM_ERROR("mismatch in " #name " " \
7833 current_config->has_pch_encoder, 8061 "(expected 0x%08x, found 0x%08x)\n", \
7834 pipe_config->has_pch_encoder); 8062 current_config->name, \
7835 return false; 8063 pipe_config->name); \
7836 } 8064 return false; \
8065 }
8066
8067#define PIPE_CONF_CHECK_I(name) \
8068 if (current_config->name != pipe_config->name) { \
8069 DRM_ERROR("mismatch in " #name " " \
8070 "(expected %i, found %i)\n", \
8071 current_config->name, \
8072 pipe_config->name); \
8073 return false; \
8074 }
8075
8076#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8077 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8078 DRM_ERROR("mismatch in " #name " " \
8079 "(expected %i, found %i)\n", \
8080 current_config->name & (mask), \
8081 pipe_config->name & (mask)); \
8082 return false; \
8083 }
8084
8085#define PIPE_CONF_QUIRK(quirk) \
8086 ((current_config->quirks | pipe_config->quirks) & (quirk))
8087
8088 PIPE_CONF_CHECK_I(cpu_transcoder);
8089
8090 PIPE_CONF_CHECK_I(has_pch_encoder);
8091 PIPE_CONF_CHECK_I(fdi_lanes);
8092 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8093 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8094 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8095 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8096 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8097
8098 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8099 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8100 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8101 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8102 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8103 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8104
8105 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8106 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8107 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8108 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8109 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8110 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8111
8112 if (!HAS_PCH_SPLIT(dev))
8113 PIPE_CONF_CHECK_I(pixel_multiplier);
8114
8115 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8116 DRM_MODE_FLAG_INTERLACE);
8117
8118 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8119 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8120 DRM_MODE_FLAG_PHSYNC);
8121 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8122 DRM_MODE_FLAG_NHSYNC);
8123 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8124 DRM_MODE_FLAG_PVSYNC);
8125 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8126 DRM_MODE_FLAG_NVSYNC);
8127 }
8128
8129 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8130 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8131
8132 PIPE_CONF_CHECK_I(gmch_pfit.control);
8133 /* pfit ratios are autocomputed by the hw on gen4+ */
8134 if (INTEL_INFO(dev)->gen < 4)
8135 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8136 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8137 PIPE_CONF_CHECK_I(pch_pfit.pos);
8138 PIPE_CONF_CHECK_I(pch_pfit.size);
8139
8140 PIPE_CONF_CHECK_I(ips_enabled);
8141
8142 PIPE_CONF_CHECK_I(shared_dpll);
8143 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8144 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8145 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8146
8147#undef PIPE_CONF_CHECK_X
8148#undef PIPE_CONF_CHECK_I
8149#undef PIPE_CONF_CHECK_FLAGS
8150#undef PIPE_CONF_QUIRK
7837 8151
7838 return true; 8152 return true;
7839} 8153}
7840 8154
7841void 8155static void
7842intel_modeset_check_state(struct drm_device *dev) 8156check_connector_state(struct drm_device *dev)
7843{ 8157{
7844 drm_i915_private_t *dev_priv = dev->dev_private;
7845 struct intel_crtc *crtc;
7846 struct intel_encoder *encoder;
7847 struct intel_connector *connector; 8158 struct intel_connector *connector;
7848 struct intel_crtc_config pipe_config;
7849 8159
7850 list_for_each_entry(connector, &dev->mode_config.connector_list, 8160 list_for_each_entry(connector, &dev->mode_config.connector_list,
7851 base.head) { 8161 base.head) {
@@ -7856,6 +8166,13 @@ intel_modeset_check_state(struct drm_device *dev)
7856 WARN(&connector->new_encoder->base != connector->base.encoder, 8166 WARN(&connector->new_encoder->base != connector->base.encoder,
7857 "connector's staged encoder doesn't match current encoder\n"); 8167 "connector's staged encoder doesn't match current encoder\n");
7858 } 8168 }
8169}
8170
8171static void
8172check_encoder_state(struct drm_device *dev)
8173{
8174 struct intel_encoder *encoder;
8175 struct intel_connector *connector;
7859 8176
7860 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 8177 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7861 base.head) { 8178 base.head) {
@@ -7907,12 +8224,23 @@ intel_modeset_check_state(struct drm_device *dev)
7907 tracked_pipe, pipe); 8224 tracked_pipe, pipe);
7908 8225
7909 } 8226 }
8227}
8228
8229static void
8230check_crtc_state(struct drm_device *dev)
8231{
8232 drm_i915_private_t *dev_priv = dev->dev_private;
8233 struct intel_crtc *crtc;
8234 struct intel_encoder *encoder;
8235 struct intel_crtc_config pipe_config;
7910 8236
7911 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 8237 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7912 base.head) { 8238 base.head) {
7913 bool enabled = false; 8239 bool enabled = false;
7914 bool active = false; 8240 bool active = false;
7915 8241
8242 memset(&pipe_config, 0, sizeof(pipe_config));
8243
7916 DRM_DEBUG_KMS("[CRTC:%d]\n", 8244 DRM_DEBUG_KMS("[CRTC:%d]\n",
7917 crtc->base.base.id); 8245 crtc->base.base.id);
7918 8246
@@ -7927,6 +8255,7 @@ intel_modeset_check_state(struct drm_device *dev)
7927 if (encoder->connectors_active) 8255 if (encoder->connectors_active)
7928 active = true; 8256 active = true;
7929 } 8257 }
8258
7930 WARN(active != crtc->active, 8259 WARN(active != crtc->active,
7931 "crtc's computed active state doesn't match tracked active state " 8260 "crtc's computed active state doesn't match tracked active state "
7932 "(expected %i, found %i)\n", active, crtc->active); 8261 "(expected %i, found %i)\n", active, crtc->active);
@@ -7934,7 +8263,6 @@ intel_modeset_check_state(struct drm_device *dev)
7934 "crtc's computed enabled state doesn't match tracked enabled state " 8263 "crtc's computed enabled state doesn't match tracked enabled state "
7935 "(expected %i, found %i)\n", enabled, crtc->base.enabled); 8264 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7936 8265
7937 memset(&pipe_config, 0, sizeof(pipe_config));
7938 active = dev_priv->display.get_pipe_config(crtc, 8266 active = dev_priv->display.get_pipe_config(crtc,
7939 &pipe_config); 8267 &pipe_config);
7940 8268
@@ -7942,16 +8270,86 @@ intel_modeset_check_state(struct drm_device *dev)
7942 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 8270 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
7943 active = crtc->active; 8271 active = crtc->active;
7944 8272
8273 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8274 base.head) {
8275 if (encoder->base.crtc != &crtc->base)
8276 continue;
8277 if (encoder->get_config)
8278 encoder->get_config(encoder, &pipe_config);
8279 }
8280
7945 WARN(crtc->active != active, 8281 WARN(crtc->active != active,
7946 "crtc active state doesn't match with hw state " 8282 "crtc active state doesn't match with hw state "
7947 "(expected %i, found %i)\n", crtc->active, active); 8283 "(expected %i, found %i)\n", crtc->active, active);
7948 8284
7949 WARN(active && 8285 if (active &&
7950 !intel_pipe_config_compare(&crtc->config, &pipe_config), 8286 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
7951 "pipe state doesn't match!\n"); 8287 WARN(1, "pipe state doesn't match!\n");
8288 intel_dump_pipe_config(crtc, &pipe_config,
8289 "[hw state]");
8290 intel_dump_pipe_config(crtc, &crtc->config,
8291 "[sw state]");
8292 }
7952 } 8293 }
7953} 8294}
7954 8295
8296static void
8297check_shared_dpll_state(struct drm_device *dev)
8298{
8299 drm_i915_private_t *dev_priv = dev->dev_private;
8300 struct intel_crtc *crtc;
8301 struct intel_dpll_hw_state dpll_hw_state;
8302 int i;
8303
8304 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8305 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8306 int enabled_crtcs = 0, active_crtcs = 0;
8307 bool active;
8308
8309 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8310
8311 DRM_DEBUG_KMS("%s\n", pll->name);
8312
8313 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8314
8315 WARN(pll->active > pll->refcount,
8316 "more active pll users than references: %i vs %i\n",
8317 pll->active, pll->refcount);
8318 WARN(pll->active && !pll->on,
8319 "pll in active use but not on in sw tracking\n");
8320 WARN(pll->on != active,
8321 "pll on state mismatch (expected %i, found %i)\n",
8322 pll->on, active);
8323
8324 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8325 base.head) {
8326 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8327 enabled_crtcs++;
8328 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8329 active_crtcs++;
8330 }
8331 WARN(pll->active != active_crtcs,
8332 "pll active crtcs mismatch (expected %i, found %i)\n",
8333 pll->active, active_crtcs);
8334 WARN(pll->refcount != enabled_crtcs,
8335 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8336 pll->refcount, enabled_crtcs);
8337
8338 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8339 sizeof(dpll_hw_state)),
8340 "pll hw state mismatch\n");
8341 }
8342}
8343
8344void
8345intel_modeset_check_state(struct drm_device *dev)
8346{
8347 check_connector_state(dev);
8348 check_encoder_state(dev);
8349 check_crtc_state(dev);
8350 check_shared_dpll_state(dev);
8351}
8352
7955static int __intel_set_mode(struct drm_crtc *crtc, 8353static int __intel_set_mode(struct drm_crtc *crtc,
7956 struct drm_display_mode *mode, 8354 struct drm_display_mode *mode,
7957 int x, int y, struct drm_framebuffer *fb) 8355 int x, int y, struct drm_framebuffer *fb)
@@ -7988,11 +8386,10 @@ static int __intel_set_mode(struct drm_crtc *crtc,
7988 8386
7989 goto out; 8387 goto out;
7990 } 8388 }
8389 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8390 "[modeset]");
7991 } 8391 }
7992 8392
7993 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7994 modeset_pipes, prepare_pipes, disable_pipes);
7995
7996 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) 8393 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7997 intel_crtc_disable(&intel_crtc->base); 8394 intel_crtc_disable(&intel_crtc->base);
7998 8395
@@ -8005,12 +8402,10 @@ static int __intel_set_mode(struct drm_crtc *crtc,
8005 * to set it here already despite that we pass it down the callchain. 8402 * to set it here already despite that we pass it down the callchain.
8006 */ 8403 */
8007 if (modeset_pipes) { 8404 if (modeset_pipes) {
8008 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8009 crtc->mode = *mode; 8405 crtc->mode = *mode;
8010 /* mode_set/enable/disable functions rely on a correct pipe 8406 /* mode_set/enable/disable functions rely on a correct pipe
8011 * config. */ 8407 * config. */
8012 to_intel_crtc(crtc)->config = *pipe_config; 8408 to_intel_crtc(crtc)->config = *pipe_config;
8013 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8014 } 8409 }
8015 8410
8016 /* Only after disabling all output pipelines that will be changed can we 8411 /* Only after disabling all output pipelines that will be changed can we
@@ -8349,12 +8744,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
8349 goto fail; 8744 goto fail;
8350 8745
8351 if (config->mode_changed) { 8746 if (config->mode_changed) {
8352 if (set->mode) {
8353 DRM_DEBUG_KMS("attempting to set mode from"
8354 " userspace\n");
8355 drm_mode_debug_printmodeline(set->mode);
8356 }
8357
8358 ret = intel_set_mode(set->crtc, set->mode, 8747 ret = intel_set_mode(set->crtc, set->mode,
8359 set->x, set->y, set->fb); 8748 set->x, set->y, set->fb);
8360 } else if (config->fb_changed) { 8749 } else if (config->fb_changed) {
@@ -8365,8 +8754,8 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
8365 } 8754 }
8366 8755
8367 if (ret) { 8756 if (ret) {
8368 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n", 8757 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8369 set->crtc->base.id, ret); 8758 set->crtc->base.id, ret);
8370fail: 8759fail:
8371 intel_set_config_restore_state(dev, config); 8760 intel_set_config_restore_state(dev, config);
8372 8761
@@ -8397,23 +8786,93 @@ static void intel_cpu_pll_init(struct drm_device *dev)
8397 intel_ddi_pll_init(dev); 8786 intel_ddi_pll_init(dev);
8398} 8787}
8399 8788
8400static void intel_pch_pll_init(struct drm_device *dev) 8789static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8790 struct intel_shared_dpll *pll,
8791 struct intel_dpll_hw_state *hw_state)
8401{ 8792{
8402 drm_i915_private_t *dev_priv = dev->dev_private; 8793 uint32_t val;
8403 int i;
8404 8794
8405 if (dev_priv->num_pch_pll == 0) { 8795 val = I915_READ(PCH_DPLL(pll->id));
8406 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); 8796 hw_state->dpll = val;
8407 return; 8797 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8798 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8799
8800 return val & DPLL_VCO_ENABLE;
8801}
8802
8803static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8804 struct intel_shared_dpll *pll)
8805{
8806 uint32_t reg, val;
8807
8808 /* PCH refclock must be enabled first */
8809 assert_pch_refclk_enabled(dev_priv);
8810
8811 reg = PCH_DPLL(pll->id);
8812 val = I915_READ(reg);
8813 val |= DPLL_VCO_ENABLE;
8814 I915_WRITE(reg, val);
8815 POSTING_READ(reg);
8816 udelay(200);
8817}
8818
8819static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8820 struct intel_shared_dpll *pll)
8821{
8822 struct drm_device *dev = dev_priv->dev;
8823 struct intel_crtc *crtc;
8824 uint32_t reg, val;
8825
8826 /* Make sure no transcoder isn't still depending on us. */
8827 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8828 if (intel_crtc_to_shared_dpll(crtc) == pll)
8829 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8408 } 8830 }
8409 8831
8410 for (i = 0; i < dev_priv->num_pch_pll; i++) { 8832 reg = PCH_DPLL(pll->id);
8411 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); 8833 val = I915_READ(reg);
8412 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); 8834 val &= ~DPLL_VCO_ENABLE;
8413 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); 8835 I915_WRITE(reg, val);
8836 POSTING_READ(reg);
8837 udelay(200);
8838}
8839
8840static char *ibx_pch_dpll_names[] = {
8841 "PCH DPLL A",
8842 "PCH DPLL B",
8843};
8844
8845static void ibx_pch_dpll_init(struct drm_device *dev)
8846{
8847 struct drm_i915_private *dev_priv = dev->dev_private;
8848 int i;
8849
8850 dev_priv->num_shared_dpll = 2;
8851
8852 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8853 dev_priv->shared_dplls[i].id = i;
8854 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8855 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8856 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8857 dev_priv->shared_dplls[i].get_hw_state =
8858 ibx_pch_dpll_get_hw_state;
8414 } 8859 }
8415} 8860}
8416 8861
8862static void intel_shared_dpll_init(struct drm_device *dev)
8863{
8864 struct drm_i915_private *dev_priv = dev->dev_private;
8865
8866 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8867 ibx_pch_dpll_init(dev);
8868 else
8869 dev_priv->num_shared_dpll = 0;
8870
8871 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8872 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8873 dev_priv->num_shared_dpll);
8874}
8875
8417static void intel_crtc_init(struct drm_device *dev, int pipe) 8876static void intel_crtc_init(struct drm_device *dev, int pipe)
8418{ 8877{
8419 drm_i915_private_t *dev_priv = dev->dev_private; 8878 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -8436,7 +8895,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
8436 /* Swap pipes & planes for FBC on pre-965 */ 8895 /* Swap pipes & planes for FBC on pre-965 */
8437 intel_crtc->pipe = pipe; 8896 intel_crtc->pipe = pipe;
8438 intel_crtc->plane = pipe; 8897 intel_crtc->plane = pipe;
8439 intel_crtc->config.cpu_transcoder = pipe;
8440 if (IS_MOBILE(dev) && IS_GEN3(dev)) { 8898 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8441 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); 8899 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8442 intel_crtc->plane = !pipe; 8900 intel_crtc->plane = !pipe;
@@ -8519,13 +8977,8 @@ static void intel_setup_outputs(struct drm_device *dev)
8519 struct drm_i915_private *dev_priv = dev->dev_private; 8977 struct drm_i915_private *dev_priv = dev->dev_private;
8520 struct intel_encoder *encoder; 8978 struct intel_encoder *encoder;
8521 bool dpd_is_edp = false; 8979 bool dpd_is_edp = false;
8522 bool has_lvds;
8523 8980
8524 has_lvds = intel_lvds_init(dev); 8981 intel_lvds_init(dev);
8525 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8526 /* disable the panel fitter on everything but LVDS */
8527 I915_WRITE(PFIT_CONTROL, 0);
8528 }
8529 8982
8530 if (!IS_ULT(dev)) 8983 if (!IS_ULT(dev))
8531 intel_crt_init(dev); 8984 intel_crt_init(dev);
@@ -8598,10 +9051,8 @@ static void intel_setup_outputs(struct drm_device *dev)
8598 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); 9051 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8599 } 9052 }
8600 9053
8601 if (!found && SUPPORTS_INTEGRATED_DP(dev)) { 9054 if (!found && SUPPORTS_INTEGRATED_DP(dev))
8602 DRM_DEBUG_KMS("probing DP_B\n");
8603 intel_dp_init(dev, DP_B, PORT_B); 9055 intel_dp_init(dev, DP_B, PORT_B);
8604 }
8605 } 9056 }
8606 9057
8607 /* Before G4X SDVOC doesn't have its own detect register */ 9058 /* Before G4X SDVOC doesn't have its own detect register */
@@ -8617,17 +9068,13 @@ static void intel_setup_outputs(struct drm_device *dev)
8617 DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); 9068 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8618 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); 9069 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8619 } 9070 }
8620 if (SUPPORTS_INTEGRATED_DP(dev)) { 9071 if (SUPPORTS_INTEGRATED_DP(dev))
8621 DRM_DEBUG_KMS("probing DP_C\n");
8622 intel_dp_init(dev, DP_C, PORT_C); 9072 intel_dp_init(dev, DP_C, PORT_C);
8623 }
8624 } 9073 }
8625 9074
8626 if (SUPPORTS_INTEGRATED_DP(dev) && 9075 if (SUPPORTS_INTEGRATED_DP(dev) &&
8627 (I915_READ(DP_D) & DP_DETECTED)) { 9076 (I915_READ(DP_D) & DP_DETECTED))
8628 DRM_DEBUG_KMS("probing DP_D\n");
8629 intel_dp_init(dev, DP_D, PORT_D); 9077 intel_dp_init(dev, DP_D, PORT_D);
8630 }
8631 } else if (IS_GEN2(dev)) 9078 } else if (IS_GEN2(dev))
8632 intel_dvo_init(dev); 9079 intel_dvo_init(dev);
8633 9080
@@ -8675,6 +9122,7 @@ int intel_framebuffer_init(struct drm_device *dev,
8675 struct drm_mode_fb_cmd2 *mode_cmd, 9122 struct drm_mode_fb_cmd2 *mode_cmd,
8676 struct drm_i915_gem_object *obj) 9123 struct drm_i915_gem_object *obj)
8677{ 9124{
9125 int pitch_limit;
8678 int ret; 9126 int ret;
8679 9127
8680 if (obj->tiling_mode == I915_TILING_Y) { 9128 if (obj->tiling_mode == I915_TILING_Y) {
@@ -8688,10 +9136,26 @@ int intel_framebuffer_init(struct drm_device *dev,
8688 return -EINVAL; 9136 return -EINVAL;
8689 } 9137 }
8690 9138
8691 /* FIXME <= Gen4 stride limits are bit unclear */ 9139 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
8692 if (mode_cmd->pitches[0] > 32768) { 9140 pitch_limit = 32*1024;
8693 DRM_DEBUG("pitch (%d) must be at less than 32768\n", 9141 } else if (INTEL_INFO(dev)->gen >= 4) {
8694 mode_cmd->pitches[0]); 9142 if (obj->tiling_mode)
9143 pitch_limit = 16*1024;
9144 else
9145 pitch_limit = 32*1024;
9146 } else if (INTEL_INFO(dev)->gen >= 3) {
9147 if (obj->tiling_mode)
9148 pitch_limit = 8*1024;
9149 else
9150 pitch_limit = 16*1024;
9151 } else
9152 /* XXX DSPC is limited to 4k tiled */
9153 pitch_limit = 8*1024;
9154
9155 if (mode_cmd->pitches[0] > pitch_limit) {
9156 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9157 obj->tiling_mode ? "tiled" : "linear",
9158 mode_cmd->pitches[0], pitch_limit);
8695 return -EINVAL; 9159 return -EINVAL;
8696 } 9160 }
8697 9161
@@ -8712,7 +9176,8 @@ int intel_framebuffer_init(struct drm_device *dev,
8712 case DRM_FORMAT_XRGB1555: 9176 case DRM_FORMAT_XRGB1555:
8713 case DRM_FORMAT_ARGB1555: 9177 case DRM_FORMAT_ARGB1555:
8714 if (INTEL_INFO(dev)->gen > 3) { 9178 if (INTEL_INFO(dev)->gen > 3) {
8715 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 9179 DRM_DEBUG("unsupported pixel format: %s\n",
9180 drm_get_format_name(mode_cmd->pixel_format));
8716 return -EINVAL; 9181 return -EINVAL;
8717 } 9182 }
8718 break; 9183 break;
@@ -8723,7 +9188,8 @@ int intel_framebuffer_init(struct drm_device *dev,
8723 case DRM_FORMAT_XBGR2101010: 9188 case DRM_FORMAT_XBGR2101010:
8724 case DRM_FORMAT_ABGR2101010: 9189 case DRM_FORMAT_ABGR2101010:
8725 if (INTEL_INFO(dev)->gen < 4) { 9190 if (INTEL_INFO(dev)->gen < 4) {
8726 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 9191 DRM_DEBUG("unsupported pixel format: %s\n",
9192 drm_get_format_name(mode_cmd->pixel_format));
8727 return -EINVAL; 9193 return -EINVAL;
8728 } 9194 }
8729 break; 9195 break;
@@ -8732,12 +9198,14 @@ int intel_framebuffer_init(struct drm_device *dev,
8732 case DRM_FORMAT_YVYU: 9198 case DRM_FORMAT_YVYU:
8733 case DRM_FORMAT_VYUY: 9199 case DRM_FORMAT_VYUY:
8734 if (INTEL_INFO(dev)->gen < 5) { 9200 if (INTEL_INFO(dev)->gen < 5) {
8735 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 9201 DRM_DEBUG("unsupported pixel format: %s\n",
9202 drm_get_format_name(mode_cmd->pixel_format));
8736 return -EINVAL; 9203 return -EINVAL;
8737 } 9204 }
8738 break; 9205 break;
8739 default: 9206 default:
8740 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format); 9207 DRM_DEBUG("unsupported pixel format: %s\n",
9208 drm_get_format_name(mode_cmd->pixel_format));
8741 return -EINVAL; 9209 return -EINVAL;
8742 } 9210 }
8743 9211
@@ -8782,6 +9250,15 @@ static void intel_init_display(struct drm_device *dev)
8782{ 9250{
8783 struct drm_i915_private *dev_priv = dev->dev_private; 9251 struct drm_i915_private *dev_priv = dev->dev_private;
8784 9252
9253 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9254 dev_priv->display.find_dpll = g4x_find_best_dpll;
9255 else if (IS_VALLEYVIEW(dev))
9256 dev_priv->display.find_dpll = vlv_find_best_dpll;
9257 else if (IS_PINEVIEW(dev))
9258 dev_priv->display.find_dpll = pnv_find_best_dpll;
9259 else
9260 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9261
8785 if (HAS_DDI(dev)) { 9262 if (HAS_DDI(dev)) {
8786 dev_priv->display.get_pipe_config = haswell_get_pipe_config; 9263 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8787 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; 9264 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
@@ -8796,6 +9273,13 @@ static void intel_init_display(struct drm_device *dev)
8796 dev_priv->display.crtc_disable = ironlake_crtc_disable; 9273 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8797 dev_priv->display.off = ironlake_crtc_off; 9274 dev_priv->display.off = ironlake_crtc_off;
8798 dev_priv->display.update_plane = ironlake_update_plane; 9275 dev_priv->display.update_plane = ironlake_update_plane;
9276 } else if (IS_VALLEYVIEW(dev)) {
9277 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9278 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9279 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9280 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9281 dev_priv->display.off = i9xx_crtc_off;
9282 dev_priv->display.update_plane = i9xx_update_plane;
8799 } else { 9283 } else {
8800 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 9284 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8801 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; 9285 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
@@ -9037,6 +9521,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
9037 mutex_unlock(&dev->struct_mutex); 9521 mutex_unlock(&dev->struct_mutex);
9038} 9522}
9039 9523
9524void intel_modeset_suspend_hw(struct drm_device *dev)
9525{
9526 intel_suspend_hw(dev);
9527}
9528
9040void intel_modeset_init(struct drm_device *dev) 9529void intel_modeset_init(struct drm_device *dev)
9041{ 9530{
9042 struct drm_i915_private *dev_priv = dev->dev_private; 9531 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9082,13 +9571,13 @@ void intel_modeset_init(struct drm_device *dev)
9082 for (j = 0; j < dev_priv->num_plane; j++) { 9571 for (j = 0; j < dev_priv->num_plane; j++) {
9083 ret = intel_plane_init(dev, i, j); 9572 ret = intel_plane_init(dev, i, j);
9084 if (ret) 9573 if (ret)
9085 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n", 9574 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9086 i, j, ret); 9575 pipe_name(i), sprite_name(i, j), ret);
9087 } 9576 }
9088 } 9577 }
9089 9578
9090 intel_cpu_pll_init(dev); 9579 intel_cpu_pll_init(dev);
9091 intel_pch_pll_init(dev); 9580 intel_shared_dpll_init(dev);
9092 9581
9093 /* Just disable it once at startup */ 9582 /* Just disable it once at startup */
9094 i915_disable_vga(dev); 9583 i915_disable_vga(dev);
@@ -9289,57 +9778,18 @@ void i915_redisable_vga(struct drm_device *dev)
9289 } 9778 }
9290} 9779}
9291 9780
9292/* Scan out the current hw modeset state, sanitizes it and maps it into the drm 9781static void intel_modeset_readout_hw_state(struct drm_device *dev)
9293 * and i915 state tracking structures. */
9294void intel_modeset_setup_hw_state(struct drm_device *dev,
9295 bool force_restore)
9296{ 9782{
9297 struct drm_i915_private *dev_priv = dev->dev_private; 9783 struct drm_i915_private *dev_priv = dev->dev_private;
9298 enum pipe pipe; 9784 enum pipe pipe;
9299 u32 tmp;
9300 struct drm_plane *plane;
9301 struct intel_crtc *crtc; 9785 struct intel_crtc *crtc;
9302 struct intel_encoder *encoder; 9786 struct intel_encoder *encoder;
9303 struct intel_connector *connector; 9787 struct intel_connector *connector;
9788 int i;
9304 9789
9305 if (HAS_DDI(dev)) {
9306 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9307
9308 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9309 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9310 case TRANS_DDI_EDP_INPUT_A_ON:
9311 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9312 pipe = PIPE_A;
9313 break;
9314 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9315 pipe = PIPE_B;
9316 break;
9317 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9318 pipe = PIPE_C;
9319 break;
9320 default:
9321 /* A bogus value has been programmed, disable
9322 * the transcoder */
9323 WARN(1, "Bogus eDP source %08x\n", tmp);
9324 intel_ddi_disable_transcoder_func(dev_priv,
9325 TRANSCODER_EDP);
9326 goto setup_pipes;
9327 }
9328
9329 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9330 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9331
9332 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9333 pipe_name(pipe));
9334 }
9335 }
9336
9337setup_pipes:
9338 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 9790 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9339 base.head) { 9791 base.head) {
9340 enum transcoder tmp = crtc->config.cpu_transcoder;
9341 memset(&crtc->config, 0, sizeof(crtc->config)); 9792 memset(&crtc->config, 0, sizeof(crtc->config));
9342 crtc->config.cpu_transcoder = tmp;
9343 9793
9344 crtc->active = dev_priv->display.get_pipe_config(crtc, 9794 crtc->active = dev_priv->display.get_pipe_config(crtc,
9345 &crtc->config); 9795 &crtc->config);
@@ -9351,16 +9801,35 @@ setup_pipes:
9351 crtc->active ? "enabled" : "disabled"); 9801 crtc->active ? "enabled" : "disabled");
9352 } 9802 }
9353 9803
9804 /* FIXME: Smash this into the new shared dpll infrastructure. */
9354 if (HAS_DDI(dev)) 9805 if (HAS_DDI(dev))
9355 intel_ddi_setup_hw_pll_state(dev); 9806 intel_ddi_setup_hw_pll_state(dev);
9356 9807
9808 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9809 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9810
9811 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9812 pll->active = 0;
9813 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9814 base.head) {
9815 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9816 pll->active++;
9817 }
9818 pll->refcount = pll->active;
9819
9820 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9821 pll->name, pll->refcount);
9822 }
9823
9357 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9824 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9358 base.head) { 9825 base.head) {
9359 pipe = 0; 9826 pipe = 0;
9360 9827
9361 if (encoder->get_hw_state(encoder, &pipe)) { 9828 if (encoder->get_hw_state(encoder, &pipe)) {
9362 encoder->base.crtc = 9829 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9363 dev_priv->pipe_to_crtc_mapping[pipe]; 9830 encoder->base.crtc = &crtc->base;
9831 if (encoder->get_config)
9832 encoder->get_config(encoder, &crtc->config);
9364 } else { 9833 } else {
9365 encoder->base.crtc = NULL; 9834 encoder->base.crtc = NULL;
9366 } 9835 }
@@ -9388,6 +9857,20 @@ setup_pipes:
9388 drm_get_connector_name(&connector->base), 9857 drm_get_connector_name(&connector->base),
9389 connector->base.encoder ? "enabled" : "disabled"); 9858 connector->base.encoder ? "enabled" : "disabled");
9390 } 9859 }
9860}
9861
9862/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9863 * and i915 state tracking structures. */
9864void intel_modeset_setup_hw_state(struct drm_device *dev,
9865 bool force_restore)
9866{
9867 struct drm_i915_private *dev_priv = dev->dev_private;
9868 enum pipe pipe;
9869 struct drm_plane *plane;
9870 struct intel_crtc *crtc;
9871 struct intel_encoder *encoder;
9872
9873 intel_modeset_readout_hw_state(dev);
9391 9874
9392 /* HW state is read out, now we need to sanitize this mess. */ 9875 /* HW state is read out, now we need to sanitize this mess. */
9393 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
@@ -9398,6 +9881,7 @@ setup_pipes:
9398 for_each_pipe(pipe) { 9881 for_each_pipe(pipe) {
9399 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 9882 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9400 intel_sanitize_crtc(crtc); 9883 intel_sanitize_crtc(crtc);
9884 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9401 } 9885 }
9402 9886
9403 if (force_restore) { 9887 if (force_restore) {
@@ -9440,12 +9924,23 @@ void intel_modeset_cleanup(struct drm_device *dev)
9440 struct drm_crtc *crtc; 9924 struct drm_crtc *crtc;
9441 struct intel_crtc *intel_crtc; 9925 struct intel_crtc *intel_crtc;
9442 9926
9927 /*
9928 * Interrupts and polling as the first thing to avoid creating havoc.
9929 * Too much stuff here (turning of rps, connectors, ...) would
9930 * experience fancy races otherwise.
9931 */
9932 drm_irq_uninstall(dev);
9933 cancel_work_sync(&dev_priv->hotplug_work);
9934 /*
9935 * Due to the hpd irq storm handling the hotplug work can re-arm the
9936 * poll handlers. Hence disable polling after hpd handling is shut down.
9937 */
9443 drm_kms_helper_poll_fini(dev); 9938 drm_kms_helper_poll_fini(dev);
9939
9444 mutex_lock(&dev->struct_mutex); 9940 mutex_lock(&dev->struct_mutex);
9445 9941
9446 intel_unregister_dsm_handler(); 9942 intel_unregister_dsm_handler();
9447 9943
9448
9449 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9944 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9450 /* Skip inactive CRTCs */ 9945 /* Skip inactive CRTCs */
9451 if (!crtc->fb) 9946 if (!crtc->fb)
@@ -9461,17 +9956,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
9461 9956
9462 ironlake_teardown_rc6(dev); 9957 ironlake_teardown_rc6(dev);
9463 9958
9464 if (IS_VALLEYVIEW(dev))
9465 vlv_init_dpio(dev);
9466
9467 mutex_unlock(&dev->struct_mutex); 9959 mutex_unlock(&dev->struct_mutex);
9468 9960
9469 /* Disable the irq before mode object teardown, for the irq might
9470 * enqueue unpin/hotplug work. */
9471 drm_irq_uninstall(dev);
9472 cancel_work_sync(&dev_priv->hotplug_work);
9473 cancel_work_sync(&dev_priv->rps.work);
9474
9475 /* flush any delayed tasks or pending work */ 9961 /* flush any delayed tasks or pending work */
9476 flush_scheduled_work(); 9962 flush_scheduled_work();
9477 9963
@@ -9520,6 +10006,9 @@ int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9520#include <linux/seq_file.h> 10006#include <linux/seq_file.h>
9521 10007
9522struct intel_display_error_state { 10008struct intel_display_error_state {
10009
10010 u32 power_well_driver;
10011
9523 struct intel_cursor_error_state { 10012 struct intel_cursor_error_state {
9524 u32 control; 10013 u32 control;
9525 u32 position; 10014 u32 position;
@@ -9528,6 +10017,7 @@ struct intel_display_error_state {
9528 } cursor[I915_MAX_PIPES]; 10017 } cursor[I915_MAX_PIPES];
9529 10018
9530 struct intel_pipe_error_state { 10019 struct intel_pipe_error_state {
10020 enum transcoder cpu_transcoder;
9531 u32 conf; 10021 u32 conf;
9532 u32 source; 10022 u32 source;
9533 10023
@@ -9562,8 +10052,12 @@ intel_display_capture_error_state(struct drm_device *dev)
9562 if (error == NULL) 10052 if (error == NULL)
9563 return NULL; 10053 return NULL;
9564 10054
10055 if (HAS_POWER_WELL(dev))
10056 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10057
9565 for_each_pipe(i) { 10058 for_each_pipe(i) {
9566 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i); 10059 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10060 error->pipe[i].cpu_transcoder = cpu_transcoder;
9567 10061
9568 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { 10062 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9569 error->cursor[i].control = I915_READ(CURCNTR(i)); 10063 error->cursor[i].control = I915_READ(CURCNTR(i));
@@ -9598,46 +10092,60 @@ intel_display_capture_error_state(struct drm_device *dev)
9598 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); 10092 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9599 } 10093 }
9600 10094
10095 /* In the code above we read the registers without checking if the power
10096 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10097 * prevent the next I915_WRITE from detecting it and printing an error
10098 * message. */
10099 if (HAS_POWER_WELL(dev))
10100 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10101
9601 return error; 10102 return error;
9602} 10103}
9603 10104
10105#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10106
9604void 10107void
9605intel_display_print_error_state(struct seq_file *m, 10108intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9606 struct drm_device *dev, 10109 struct drm_device *dev,
9607 struct intel_display_error_state *error) 10110 struct intel_display_error_state *error)
9608{ 10111{
9609 int i; 10112 int i;
9610 10113
9611 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); 10114 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10115 if (HAS_POWER_WELL(dev))
10116 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10117 error->power_well_driver);
9612 for_each_pipe(i) { 10118 for_each_pipe(i) {
9613 seq_printf(m, "Pipe [%d]:\n", i); 10119 err_printf(m, "Pipe [%d]:\n", i);
9614 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); 10120 err_printf(m, " CPU transcoder: %c\n",
9615 seq_printf(m, " SRC: %08x\n", error->pipe[i].source); 10121 transcoder_name(error->pipe[i].cpu_transcoder));
9616 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); 10122 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9617 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); 10123 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9618 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); 10124 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9619 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); 10125 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9620 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); 10126 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9621 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); 10127 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9622 10128 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9623 seq_printf(m, "Plane [%d]:\n", i); 10129 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9624 seq_printf(m, " CNTR: %08x\n", error->plane[i].control); 10130
9625 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 10131 err_printf(m, "Plane [%d]:\n", i);
10132 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10133 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9626 if (INTEL_INFO(dev)->gen <= 3) { 10134 if (INTEL_INFO(dev)->gen <= 3) {
9627 seq_printf(m, " SIZE: %08x\n", error->plane[i].size); 10135 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9628 seq_printf(m, " POS: %08x\n", error->plane[i].pos); 10136 err_printf(m, " POS: %08x\n", error->plane[i].pos);
9629 } 10137 }
9630 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) 10138 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9631 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); 10139 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9632 if (INTEL_INFO(dev)->gen >= 4) { 10140 if (INTEL_INFO(dev)->gen >= 4) {
9633 seq_printf(m, " SURF: %08x\n", error->plane[i].surface); 10141 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9634 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); 10142 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9635 } 10143 }
9636 10144
9637 seq_printf(m, "Cursor [%d]:\n", i); 10145 err_printf(m, "Cursor [%d]:\n", i);
9638 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); 10146 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9639 seq_printf(m, " POS: %08x\n", error->cursor[i].position); 10147 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9640 seq_printf(m, " BASE: %08x\n", error->cursor[i].base); 10148 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
9641 } 10149 }
9642} 10150}
9643#endif 10151#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 10:32:08 -0500