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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c406
1 files changed, 377 insertions, 29 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a2834276cb38..d9c50ff94d76 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -56,11 +56,13 @@ typedef struct {
56} intel_p2_t; 56} intel_p2_t;
57 57
58#define INTEL_P2_NUM 2 58#define INTEL_P2_NUM 2
59 59typedef struct intel_limit intel_limit_t;
60typedef struct { 60struct intel_limit {
61 intel_range_t dot, vco, n, m, m1, m2, p, p1; 61 intel_range_t dot, vco, n, m, m1, m2, p, p1;
62 intel_p2_t p2; 62 intel_p2_t p2;
63} intel_limit_t; 63 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
64 int, int, intel_clock_t *);
65};
64 66
65#define I8XX_DOT_MIN 25000 67#define I8XX_DOT_MIN 25000
66#define I8XX_DOT_MAX 350000 68#define I8XX_DOT_MAX 350000
@@ -90,18 +92,32 @@ typedef struct {
90#define I9XX_DOT_MAX 400000 92#define I9XX_DOT_MAX 400000
91#define I9XX_VCO_MIN 1400000 93#define I9XX_VCO_MIN 1400000
92#define I9XX_VCO_MAX 2800000 94#define I9XX_VCO_MAX 2800000
95#define IGD_VCO_MIN 1700000
96#define IGD_VCO_MAX 3500000
93#define I9XX_N_MIN 1 97#define I9XX_N_MIN 1
94#define I9XX_N_MAX 6 98#define I9XX_N_MAX 6
99/* IGD's Ncounter is a ring counter */
100#define IGD_N_MIN 3
101#define IGD_N_MAX 6
95#define I9XX_M_MIN 70 102#define I9XX_M_MIN 70
96#define I9XX_M_MAX 120 103#define I9XX_M_MAX 120
104#define IGD_M_MIN 2
105#define IGD_M_MAX 256
97#define I9XX_M1_MIN 10 106#define I9XX_M1_MIN 10
98#define I9XX_M1_MAX 22 107#define I9XX_M1_MAX 22
99#define I9XX_M2_MIN 5 108#define I9XX_M2_MIN 5
100#define I9XX_M2_MAX 9 109#define I9XX_M2_MAX 9
110/* IGD M1 is reserved, and must be 0 */
111#define IGD_M1_MIN 0
112#define IGD_M1_MAX 0
113#define IGD_M2_MIN 0
114#define IGD_M2_MAX 254
101#define I9XX_P_SDVO_DAC_MIN 5 115#define I9XX_P_SDVO_DAC_MIN 5
102#define I9XX_P_SDVO_DAC_MAX 80 116#define I9XX_P_SDVO_DAC_MAX 80
103#define I9XX_P_LVDS_MIN 7 117#define I9XX_P_LVDS_MIN 7
104#define I9XX_P_LVDS_MAX 98 118#define I9XX_P_LVDS_MAX 98
119#define IGD_P_LVDS_MIN 7
120#define IGD_P_LVDS_MAX 112
105#define I9XX_P1_MIN 1 121#define I9XX_P1_MIN 1
106#define I9XX_P1_MAX 8 122#define I9XX_P1_MAX 8
107#define I9XX_P2_SDVO_DAC_SLOW 10 123#define I9XX_P2_SDVO_DAC_SLOW 10
@@ -115,6 +131,97 @@ typedef struct {
115#define INTEL_LIMIT_I8XX_LVDS 1 131#define INTEL_LIMIT_I8XX_LVDS 1
116#define INTEL_LIMIT_I9XX_SDVO_DAC 2 132#define INTEL_LIMIT_I9XX_SDVO_DAC 2
117#define INTEL_LIMIT_I9XX_LVDS 3 133#define INTEL_LIMIT_I9XX_LVDS 3
134#define INTEL_LIMIT_G4X_SDVO 4
135#define INTEL_LIMIT_G4X_HDMI_DAC 5
136#define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS 6
137#define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7
138#define INTEL_LIMIT_IGD_SDVO_DAC 8
139#define INTEL_LIMIT_IGD_LVDS 9
140
141/*The parameter is for SDVO on G4x platform*/
142#define G4X_DOT_SDVO_MIN 25000
143#define G4X_DOT_SDVO_MAX 270000
144#define G4X_VCO_MIN 1750000
145#define G4X_VCO_MAX 3500000
146#define G4X_N_SDVO_MIN 1
147#define G4X_N_SDVO_MAX 4
148#define G4X_M_SDVO_MIN 104
149#define G4X_M_SDVO_MAX 138
150#define G4X_M1_SDVO_MIN 17
151#define G4X_M1_SDVO_MAX 23
152#define G4X_M2_SDVO_MIN 5
153#define G4X_M2_SDVO_MAX 11
154#define G4X_P_SDVO_MIN 10
155#define G4X_P_SDVO_MAX 30
156#define G4X_P1_SDVO_MIN 1
157#define G4X_P1_SDVO_MAX 3
158#define G4X_P2_SDVO_SLOW 10
159#define G4X_P2_SDVO_FAST 10
160#define G4X_P2_SDVO_LIMIT 270000
161
162/*The parameter is for HDMI_DAC on G4x platform*/
163#define G4X_DOT_HDMI_DAC_MIN 22000
164#define G4X_DOT_HDMI_DAC_MAX 400000
165#define G4X_N_HDMI_DAC_MIN 1
166#define G4X_N_HDMI_DAC_MAX 4
167#define G4X_M_HDMI_DAC_MIN 104
168#define G4X_M_HDMI_DAC_MAX 138
169#define G4X_M1_HDMI_DAC_MIN 16
170#define G4X_M1_HDMI_DAC_MAX 23
171#define G4X_M2_HDMI_DAC_MIN 5
172#define G4X_M2_HDMI_DAC_MAX 11
173#define G4X_P_HDMI_DAC_MIN 5
174#define G4X_P_HDMI_DAC_MAX 80
175#define G4X_P1_HDMI_DAC_MIN 1
176#define G4X_P1_HDMI_DAC_MAX 8
177#define G4X_P2_HDMI_DAC_SLOW 10
178#define G4X_P2_HDMI_DAC_FAST 5
179#define G4X_P2_HDMI_DAC_LIMIT 165000
180
181/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
182#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
183#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
184#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
185#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
186#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
187#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
188#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
189#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
190#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
191#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
192#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
193#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
194#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
195#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
196#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
197#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
198#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
199
200/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
201#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
202#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
203#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
204#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
205#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
206#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
207#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
208#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
209#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
210#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
211#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
212#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
213#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
214#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
215#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
216#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
217#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
218
219static bool
220intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
221 int target, int refclk, intel_clock_t *best_clock);
222static bool
223intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
224 int target, int refclk, intel_clock_t *best_clock);
118 225
119static const intel_limit_t intel_limits[] = { 226static const intel_limit_t intel_limits[] = {
120 { /* INTEL_LIMIT_I8XX_DVO_DAC */ 227 { /* INTEL_LIMIT_I8XX_DVO_DAC */
@@ -128,6 +235,7 @@ static const intel_limit_t intel_limits[] = {
128 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, 235 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
129 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 236 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
130 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, 237 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
238 .find_pll = intel_find_best_PLL,
131 }, 239 },
132 { /* INTEL_LIMIT_I8XX_LVDS */ 240 { /* INTEL_LIMIT_I8XX_LVDS */
133 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, 241 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
@@ -140,6 +248,7 @@ static const intel_limit_t intel_limits[] = {
140 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, 248 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
141 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 249 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
142 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, 250 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
251 .find_pll = intel_find_best_PLL,
143 }, 252 },
144 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 253 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
145 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, 254 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
@@ -152,6 +261,7 @@ static const intel_limit_t intel_limits[] = {
152 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 261 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
153 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 262 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
154 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 263 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
264 .find_pll = intel_find_best_PLL,
155 }, 265 },
156 { /* INTEL_LIMIT_I9XX_LVDS */ 266 { /* INTEL_LIMIT_I9XX_LVDS */
157 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, 267 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
@@ -167,19 +277,157 @@ static const intel_limit_t intel_limits[] = {
167 */ 277 */
168 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 278 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
169 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, 279 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
280 .find_pll = intel_find_best_PLL,
281 },
282 /* below parameter and function is for G4X Chipset Family*/
283 { /* INTEL_LIMIT_G4X_SDVO */
284 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
285 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
286 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
287 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
288 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
289 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
290 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
291 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
292 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
293 .p2_slow = G4X_P2_SDVO_SLOW,
294 .p2_fast = G4X_P2_SDVO_FAST
295 },
296 .find_pll = intel_g4x_find_best_PLL,
297 },
298 { /* INTEL_LIMIT_G4X_HDMI_DAC */
299 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
300 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
301 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
302 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
303 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
304 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
305 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
306 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
307 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
308 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
309 .p2_fast = G4X_P2_HDMI_DAC_FAST
310 },
311 .find_pll = intel_g4x_find_best_PLL,
312 },
313 { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
314 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
315 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
316 .vco = { .min = G4X_VCO_MIN,
317 .max = G4X_VCO_MAX },
318 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
319 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
320 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
321 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
322 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
323 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
324 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
325 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
326 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
327 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
328 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
329 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
330 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
331 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
332 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
333 },
334 .find_pll = intel_g4x_find_best_PLL,
335 },
336 { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
337 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
338 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
339 .vco = { .min = G4X_VCO_MIN,
340 .max = G4X_VCO_MAX },
341 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
342 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
343 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
344 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
345 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
346 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
347 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
348 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
349 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
350 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
351 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
352 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
353 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
354 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
355 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
356 },
357 .find_pll = intel_g4x_find_best_PLL,
358 },
359 { /* INTEL_LIMIT_IGD_SDVO */
360 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
361 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
362 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
363 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
364 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
365 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
366 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
367 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
368 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
369 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
170 }, 370 },
371 { /* INTEL_LIMIT_IGD_LVDS */
372 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
373 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
374 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
375 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
376 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
377 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
378 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
379 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
380 /* IGD only supports single-channel mode. */
381 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
382 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
383 },
384
171}; 385};
172 386
387static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388{
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
397 limit = &intel_limits
398 [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
399 else
400 /* LVDS with dual channel */
401 limit = &intel_limits
402 [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
408 } else /* The option is for other outputs */
409 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
410
411 return limit;
412}
413
173static const intel_limit_t *intel_limit(struct drm_crtc *crtc) 414static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
174{ 415{
175 struct drm_device *dev = crtc->dev; 416 struct drm_device *dev = crtc->dev;
176 const intel_limit_t *limit; 417 const intel_limit_t *limit;
177 418
178 if (IS_I9XX(dev)) { 419 if (IS_G4X(dev)) {
420 limit = intel_g4x_limit(crtc);
421 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
180 limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS]; 423 limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
181 else 424 else
182 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 425 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
426 } else if (IS_IGD(dev)) {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
428 limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
429 else
430 limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
183 } else { 431 } else {
184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
185 limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS]; 433 limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
@@ -189,8 +437,21 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
189 return limit; 437 return limit;
190} 438}
191 439
192static void intel_clock(int refclk, intel_clock_t *clock) 440/* m1 is reserved as 0 in IGD, n is a ring counter */
441static void igd_clock(int refclk, intel_clock_t *clock)
193{ 442{
443 clock->m = clock->m2 + 2;
444 clock->p = clock->p1 * clock->p2;
445 clock->vco = refclk * clock->m / clock->n;
446 clock->dot = clock->vco / clock->p;
447}
448
449static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
450{
451 if (IS_IGD(dev)) {
452 igd_clock(refclk, clock);
453 return;
454 }
194 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 455 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
195 clock->p = clock->p1 * clock->p2; 456 clock->p = clock->p1 * clock->p2;
196 clock->vco = refclk * clock->m / (clock->n + 2); 457 clock->vco = refclk * clock->m / (clock->n + 2);
@@ -226,6 +487,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
226static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) 487static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
227{ 488{
228 const intel_limit_t *limit = intel_limit (crtc); 489 const intel_limit_t *limit = intel_limit (crtc);
490 struct drm_device *dev = crtc->dev;
229 491
230 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 492 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
231 INTELPllInvalid ("p1 out of range\n"); 493 INTELPllInvalid ("p1 out of range\n");
@@ -235,7 +497,7 @@ static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
235 INTELPllInvalid ("m2 out of range\n"); 497 INTELPllInvalid ("m2 out of range\n");
236 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 498 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
237 INTELPllInvalid ("m1 out of range\n"); 499 INTELPllInvalid ("m1 out of range\n");
238 if (clock->m1 <= clock->m2) 500 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
239 INTELPllInvalid ("m1 <= m2\n"); 501 INTELPllInvalid ("m1 <= m2\n");
240 if (clock->m < limit->m.min || limit->m.max < clock->m) 502 if (clock->m < limit->m.min || limit->m.max < clock->m)
241 INTELPllInvalid ("m out of range\n"); 503 INTELPllInvalid ("m out of range\n");
@@ -252,18 +514,14 @@ static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
252 return true; 514 return true;
253} 515}
254 516
255/** 517static bool
256 * Returns a set of divisors for the desired target clock with the given 518intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
257 * refclk, or FALSE. The returned values represent the clock equation: 519 int target, int refclk, intel_clock_t *best_clock)
258 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 520
259 */
260static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
261 int refclk, intel_clock_t *best_clock)
262{ 521{
263 struct drm_device *dev = crtc->dev; 522 struct drm_device *dev = crtc->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private; 523 struct drm_i915_private *dev_priv = dev->dev_private;
265 intel_clock_t clock; 524 intel_clock_t clock;
266 const intel_limit_t *limit = intel_limit(crtc);
267 int err = target; 525 int err = target;
268 526
269 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 527 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
@@ -289,15 +547,17 @@ static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
289 memset (best_clock, 0, sizeof (*best_clock)); 547 memset (best_clock, 0, sizeof (*best_clock));
290 548
291 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 549 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
292 for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 && 550 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
293 clock.m2 <= limit->m2.max; clock.m2++) { 551 /* m1 is always 0 in IGD */
552 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
553 break;
294 for (clock.n = limit->n.min; clock.n <= limit->n.max; 554 for (clock.n = limit->n.min; clock.n <= limit->n.max;
295 clock.n++) { 555 clock.n++) {
296 for (clock.p1 = limit->p1.min; 556 for (clock.p1 = limit->p1.min;
297 clock.p1 <= limit->p1.max; clock.p1++) { 557 clock.p1 <= limit->p1.max; clock.p1++) {
298 int this_err; 558 int this_err;
299 559
300 intel_clock(refclk, &clock); 560 intel_clock(dev, refclk, &clock);
301 561
302 if (!intel_PLL_is_valid(crtc, &clock)) 562 if (!intel_PLL_is_valid(crtc, &clock))
303 continue; 563 continue;
@@ -315,6 +575,63 @@ static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
315 return (err != target); 575 return (err != target);
316} 576}
317 577
578static bool
579intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581{
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
587 /* approximately equals target * 0.00488 */
588 int err_most = (target >> 8) + (target >> 10);
589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
592 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
593 LVDS_CLKB_POWER_UP)
594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
604 memset(best_clock, 0, sizeof(*best_clock));
605 max_n = limit->n.max;
606 /* based on hardware requriment prefer smaller n to precision */
607 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
608 /* based on hardware requirment prefere larger m1,m2, p1 */
609 for (clock.m1 = limit->m1.max;
610 clock.m1 >= limit->m1.min; clock.m1--) {
611 for (clock.m2 = limit->m2.max;
612 clock.m2 >= limit->m2.min; clock.m2--) {
613 for (clock.p1 = limit->p1.max;
614 clock.p1 >= limit->p1.min; clock.p1--) {
615 int this_err;
616
617 intel_clock(dev, refclk, &clock);
618 if (!intel_PLL_is_valid(crtc, &clock))
619 continue;
620 this_err = abs(clock.dot - target) ;
621 if (this_err < err_most) {
622 *best_clock = clock;
623 err_most = this_err;
624 max_n = clock.n;
625 found = true;
626 }
627 }
628 }
629 }
630 }
631
632 return found;
633}
634
318void 635void
319intel_wait_for_vblank(struct drm_device *dev) 636intel_wait_for_vblank(struct drm_device *dev)
320{ 637{
@@ -634,7 +951,7 @@ static int intel_get_core_clock_speed(struct drm_device *dev)
634 return 400000; 951 return 400000;
635 else if (IS_I915G(dev)) 952 else if (IS_I915G(dev))
636 return 333000; 953 return 333000;
637 else if (IS_I945GM(dev) || IS_845G(dev)) 954 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
638 return 200000; 955 return 200000;
639 else if (IS_I915GM(dev)) { 956 else if (IS_I915GM(dev)) {
640 u16 gcfgc = 0; 957 u16 gcfgc = 0;
@@ -733,6 +1050,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
733 bool is_crt = false, is_lvds = false, is_tv = false; 1050 bool is_crt = false, is_lvds = false, is_tv = false;
734 struct drm_mode_config *mode_config = &dev->mode_config; 1051 struct drm_mode_config *mode_config = &dev->mode_config;
735 struct drm_connector *connector; 1052 struct drm_connector *connector;
1053 const intel_limit_t *limit;
736 int ret; 1054 int ret;
737 1055
738 drm_vblank_pre_modeset(dev, pipe); 1056 drm_vblank_pre_modeset(dev, pipe);
@@ -776,13 +1094,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
776 refclk = 48000; 1094 refclk = 48000;
777 } 1095 }
778 1096
779 ok = intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, &clock); 1097 /*
1098 * Returns a set of divisors for the desired target clock with the given
1099 * refclk, or FALSE. The returned values represent the clock equation:
1100 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
1101 */
1102 limit = intel_limit(crtc);
1103 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
780 if (!ok) { 1104 if (!ok) {
781 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 1105 DRM_ERROR("Couldn't find PLL settings for mode!\n");
782 return -EINVAL; 1106 return -EINVAL;
783 } 1107 }
784 1108
785 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 1109 if (IS_IGD(dev))
1110 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1111 else
1112 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
786 1113
787 dpll = DPLL_VGA_MODE_DIS; 1114 dpll = DPLL_VGA_MODE_DIS;
788 if (IS_I9XX(dev)) { 1115 if (IS_I9XX(dev)) {
@@ -799,7 +1126,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
799 } 1126 }
800 1127
801 /* compute bitmask from p1 value */ 1128 /* compute bitmask from p1 value */
802 dpll |= (1 << (clock.p1 - 1)) << 16; 1129 if (IS_IGD(dev))
1130 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1131 else
1132 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
803 switch (clock.p2) { 1133 switch (clock.p2) {
804 case 5: 1134 case 5:
805 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1135 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
@@ -1279,10 +1609,20 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1279 fp = I915_READ((pipe == 0) ? FPA1 : FPB1); 1609 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
1280 1610
1281 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 1611 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1282 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 1612 if (IS_IGD(dev)) {
1283 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 1613 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
1614 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
1615 } else {
1616 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1617 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1618 }
1619
1284 if (IS_I9XX(dev)) { 1620 if (IS_I9XX(dev)) {
1285 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 1621 if (IS_IGD(dev))
1622 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
1623 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
1624 else
1625 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
1286 DPLL_FPA01_P1_POST_DIV_SHIFT); 1626 DPLL_FPA01_P1_POST_DIV_SHIFT);
1287 1627
1288 switch (dpll & DPLL_MODE_MASK) { 1628 switch (dpll & DPLL_MODE_MASK) {
@@ -1301,7 +1641,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1301 } 1641 }
1302 1642
1303 /* XXX: Handle the 100Mhz refclk */ 1643 /* XXX: Handle the 100Mhz refclk */
1304 intel_clock(96000, &clock); 1644 intel_clock(dev, 96000, &clock);
1305 } else { 1645 } else {
1306 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); 1646 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
1307 1647
@@ -1313,9 +1653,9 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1313 if ((dpll & PLL_REF_INPUT_MASK) == 1653 if ((dpll & PLL_REF_INPUT_MASK) ==
1314 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 1654 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1315 /* XXX: might not be 66MHz */ 1655 /* XXX: might not be 66MHz */
1316 intel_clock(66000, &clock); 1656 intel_clock(dev, 66000, &clock);
1317 } else 1657 } else
1318 intel_clock(48000, &clock); 1658 intel_clock(dev, 48000, &clock);
1319 } else { 1659 } else {
1320 if (dpll & PLL_P1_DIVIDE_BY_TWO) 1660 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1321 clock.p1 = 2; 1661 clock.p1 = 2;
@@ -1328,7 +1668,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1328 else 1668 else
1329 clock.p2 = 2; 1669 clock.p2 = 2;
1330 1670
1331 intel_clock(48000, &clock); 1671 intel_clock(dev, 48000, &clock);
1332 } 1672 }
1333 } 1673 }
1334 1674
@@ -1474,13 +1814,21 @@ static void intel_setup_outputs(struct drm_device *dev)
1474 1814
1475 if (IS_I9XX(dev)) { 1815 if (IS_I9XX(dev)) {
1476 int found; 1816 int found;
1817 u32 reg;
1477 1818
1478 if (I915_READ(SDVOB) & SDVO_DETECTED) { 1819 if (I915_READ(SDVOB) & SDVO_DETECTED) {
1479 found = intel_sdvo_init(dev, SDVOB); 1820 found = intel_sdvo_init(dev, SDVOB);
1480 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 1821 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1481 intel_hdmi_init(dev, SDVOB); 1822 intel_hdmi_init(dev, SDVOB);
1482 } 1823 }
1483 if (!IS_G4X(dev) || (I915_READ(SDVOB) & SDVO_DETECTED)) { 1824
1825 /* Before G4X SDVOC doesn't have its own detect register */
1826 if (IS_G4X(dev))
1827 reg = SDVOC;
1828 else
1829 reg = SDVOB;
1830
1831 if (I915_READ(reg) & SDVO_DETECTED) {
1484 found = intel_sdvo_init(dev, SDVOC); 1832 found = intel_sdvo_init(dev, SDVOC);
1485 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 1833 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1486 intel_hdmi_init(dev, SDVOC); 1834 intel_hdmi_init(dev, SDVOC);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 10:29:04 -0400