1 files changed, 5 insertions, 9 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2b63859a74b6..25a3ed693460 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2490,11 +2490,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
         udelay(150);
 
         /* Ironlake workaround, enable clock pointer after FDI enable*/
-        if (HAS_PCH_IBX(dev)) {
-                I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
-                I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
-                           FDI_RX_PHASE_SYNC_POINTER_EN);
-        }
+        I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
+        I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
+                   FDI_RX_PHASE_SYNC_POINTER_EN);
 
         reg = FDI_RX_IIR(pipe);
         for (tries = 0; tries < 5; tries++) {
@@ -2600,8 +2598,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
         POSTING_READ(reg);
         udelay(150);
 
-        if (HAS_PCH_CPT(dev))
-                cpt_phase_pointer_enable(dev, pipe);
+        cpt_phase_pointer_enable(dev, pipe);
 
         for (i = 0; i < 4; i++) {
                 reg = FDI_TX_CTL(pipe);
@@ -2735,8 +2732,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
         POSTING_READ(reg);
         udelay(150);
 
-        if (HAS_PCH_CPT(dev))
-                cpt_phase_pointer_enable(dev, pipe);
+        cpt_phase_pointer_enable(dev, pipe);
 
         for (i = 0; i < 4; i++) {
                 reg = FDI_TX_CTL(pipe);