diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f425b23e3803..f851db7be2cc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -4680,8 +4680,17 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, | |||
4680 | 4680 | ||
4681 | crtc = intel_get_crtc_for_plane(dev, plane); | 4681 | crtc = intel_get_crtc_for_plane(dev, plane); |
4682 | clock = crtc->mode.clock; | 4682 | clock = crtc->mode.clock; |
4683 | if (!clock) { | ||
4684 | *sprite_wm = 0; | ||
4685 | return false; | ||
4686 | } | ||
4683 | 4687 | ||
4684 | line_time_us = (sprite_width * 1000) / clock; | 4688 | line_time_us = (sprite_width * 1000) / clock; |
4689 | if (!line_time_us) { | ||
4690 | *sprite_wm = 0; | ||
4691 | return false; | ||
4692 | } | ||
4693 | |||
4685 | line_count = (latency_ns / line_time_us + 1000) / 1000; | 4694 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
4686 | line_size = sprite_width * pixel_size; | 4695 | line_size = sprite_width * pixel_size; |
4687 | 4696 | ||
@@ -6175,7 +6184,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) | |||
6175 | int i; | 6184 | int i; |
6176 | 6185 | ||
6177 | /* The clocks have to be on to load the palette. */ | 6186 | /* The clocks have to be on to load the palette. */ |
6178 | if (!crtc->enabled) | 6187 | if (!crtc->enabled || !intel_crtc->active) |
6179 | return; | 6188 | return; |
6180 | 6189 | ||
6181 | /* use legacy palette for Ironlake */ | 6190 | /* use legacy palette for Ironlake */ |
@@ -6561,7 +6570,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev, | |||
6561 | mode_cmd.height = mode->vdisplay; | 6570 | mode_cmd.height = mode->vdisplay; |
6562 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, | 6571 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6563 | bpp); | 6572 | bpp); |
6564 | mode_cmd.pixel_format = 0; | 6573 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
6565 | 6574 | ||
6566 | return intel_framebuffer_create(dev, &mode_cmd, obj); | 6575 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
6567 | } | 6576 | } |
@@ -8185,7 +8194,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
8185 | 8194 | ||
8186 | if (intel_enable_rc6(dev_priv->dev)) | 8195 | if (intel_enable_rc6(dev_priv->dev)) |
8187 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE | | 8196 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE | |
8188 | (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0; | 8197 | ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0); |
8189 | 8198 | ||
8190 | I915_WRITE(GEN6_RC_CONTROL, | 8199 | I915_WRITE(GEN6_RC_CONTROL, |
8191 | rc6_mask | | 8200 | rc6_mask | |