1 files changed, 217 insertions, 64 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f469a84cacfd..88a1ab7c05ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1029,19 +1029,28 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 void i8xx_disable_fbc(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long timeout = jiffies + msecs_to_jiffies(1);
         u32 fbc_ctl;
 
         if (!I915_HAS_FBC(dev))
                 return;
 
+        if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
+                return; /* Already off, just return */
+
         /* Disable compression */
         fbc_ctl = I915_READ(FBC_CONTROL);
         fbc_ctl &= ~FBC_CTL_EN;
         I915_WRITE(FBC_CONTROL, fbc_ctl);
 
         /* Wait for compressing bit to clear */
-        while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
-                ; /* nothing */
+        while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
+                if (time_after(jiffies, timeout)) {
+                        DRM_DEBUG_DRIVER("FBC idle timed out\n");
+                        break;
+                }
+                ; /* do nothing */
+        }
 
         intel_wait_for_vblank(dev);
 
@@ -1239,10 +1248,11 @@ static void intel_update_fbc(struct drm_crtc *crtc,
         return;
 
 out_disable:
-        DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
         /* Multiple disables should be harmless */
-        if (intel_fbc_enabled(dev))
+        if (intel_fbc_enabled(dev)) {
+                DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
                 intel_disable_fbc(dev);
+        }
 }
 
 static int
@@ -1386,7 +1396,8 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
         Start = obj_priv->gtt_offset;
         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 
-        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
+        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
+                      Start, Offset, x, y, crtc->fb->pitch);
         I915_WRITE(dspstride, crtc->fb->pitch);
         if (IS_I965G(dev)) {
                 I915_WRITE(dspbase, Offset);
@@ -2345,6 +2356,8 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
                 if (mode->clock * 3 > 27000 * 4)
                         return MODE_CLOCK_HIGH;
         }
+
+        drm_mode_set_crtcinfo(adjusted_mode, 0);
         return true;
 }
 
@@ -2629,6 +2642,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 
 struct cxsr_latency {
         int is_desktop;
+        int is_ddr3;
         unsigned long fsb_freq;
         unsigned long mem_freq;
         unsigned long display_sr;
@@ -2638,33 +2652,45 @@ struct cxsr_latency {
 };
 
 static struct cxsr_latency cxsr_latency_table[] = {
-        {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
-        {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
-        {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
-
-        {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
-        {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
-        {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
-
-        {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
-        {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
-        {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
-
-        {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
-        {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
-        {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
-
-        {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
-        {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
-        {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
-
-        {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
-        {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
-        {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
+        {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
+        {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
+        {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
+        {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
+        {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
+
+        {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
+        {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
+        {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
+        {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
+        {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
+
+        {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
+        {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
+        {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
+        {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
+        {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
+
+        {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
+        {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
+        {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
+        {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
+        {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
+
+        {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
+        {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
+        {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
+        {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
+        {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
+
+        {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
+        {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
+        {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
+        {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
+        {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 };
 
-static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
-                                                   int mem)
+static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 
+                                                   int fsb, int mem)
 {
         int i;
         struct cxsr_latency *latency;
@@ -2675,6 +2701,7 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
                 latency = &cxsr_latency_table[i];
                 if (is_desktop == latency->is_desktop &&
+                    is_ddr3 == latency->is_ddr3 &&
                     fsb == latency->fsb_freq && mem == latency->mem_freq)
                         return latency;
         }
@@ -2789,8 +2816,8 @@ static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
         struct cxsr_latency *latency;
         int sr_clock;
 
-        latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
-                                         dev_priv->mem_freq);
+        latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 
+                                         dev_priv->fsb_freq, dev_priv->mem_freq);
         if (!latency) {
                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
                 pineview_disable_cxsr(dev);
@@ -3772,6 +3799,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 }
         }
 
+        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+                pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+                /* the chip adds 2 halflines automatically */
+                adjusted_mode->crtc_vdisplay -= 1;
+                adjusted_mode->crtc_vtotal -= 1;
+                adjusted_mode->crtc_vblank_start -= 1;
+                adjusted_mode->crtc_vblank_end -= 1;
+                adjusted_mode->crtc_vsync_end -= 1;
+                adjusted_mode->crtc_vsync_start -= 1;
+        } else
+                pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
+
         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
                    ((adjusted_mode->crtc_htotal - 1) << 16));
         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
@@ -4436,6 +4475,8 @@ static void intel_idle_update(struct work_struct *work)
 
         mutex_lock(&dev->struct_mutex);
 
+        i915_update_gfx_val(dev_priv);
+
         if (IS_I945G(dev) || IS_I945GM(dev)) {
                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
@@ -4564,12 +4605,6 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
         spin_lock_irqsave(&dev->event_lock, flags);
         work = intel_crtc->unpin_work;
         if (work == NULL || !work->pending) {
-                if (work && !work->pending) {
-                        obj_priv = to_intel_bo(work->pending_flip_obj);
-                        DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
-                                         obj_priv,
-                                         atomic_read(&obj_priv->pending_flip));
-                }
                 spin_unlock_irqrestore(&dev->event_lock, flags);
                 return;
         }
@@ -4629,14 +4664,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         unsigned long flags;
         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
         int ret, pipesrc;
-        RING_LOCALS;
 
         work = kzalloc(sizeof *work, GFP_KERNEL);
         if (work == NULL)
                 return -ENOMEM;
 
-        mutex_lock(&dev->struct_mutex);
-
         work->event = event;
         work->dev = crtc->dev;
         intel_fb = to_intel_framebuffer(crtc->fb);
@@ -4646,10 +4678,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         /* We borrow the event spin lock for protecting unpin_work */
         spin_lock_irqsave(&dev->event_lock, flags);
         if (intel_crtc->unpin_work) {
-                DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
                 spin_unlock_irqrestore(&dev->event_lock, flags);
                 kfree(work);
-                mutex_unlock(&dev->struct_mutex);
+
+                DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
                 return -EBUSY;
         }
         intel_crtc->unpin_work = work;
@@ -4658,13 +4690,19 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         intel_fb = to_intel_framebuffer(fb);
         obj = intel_fb->obj;
 
+        mutex_lock(&dev->struct_mutex);
         ret = intel_pin_and_fence_fb_obj(dev, obj);
         if (ret != 0) {
-                DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
-                          to_intel_bo(obj));
-                kfree(work);
-                intel_crtc->unpin_work = NULL;
                 mutex_unlock(&dev->struct_mutex);
+
+                spin_lock_irqsave(&dev->event_lock, flags);
+                intel_crtc->unpin_work = NULL;
+                spin_unlock_irqrestore(&dev->event_lock, flags);
+
+                kfree(work);
+
+                DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
+                                 to_intel_bo(obj));
                 return ret;
         }
 
@@ -5023,10 +5061,32 @@ err_unref:
         return NULL;
 }
 
+bool ironlake_set_drps(struct drm_device *dev, u8 val)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u16 rgvswctl;
+
+        rgvswctl = I915_READ16(MEMSWCTL);
+        if (rgvswctl & MEMCTL_CMD_STS) {
+                DRM_DEBUG("gpu busy, RCS change rejected\n");
+                return false; /* still busy with another command */
+        }
+
+        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
+                (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
+        I915_WRITE16(MEMSWCTL, rgvswctl);
+        POSTING_READ16(MEMSWCTL);
+
+        rgvswctl |= MEMCTL_CMD_STS;
+        I915_WRITE16(MEMSWCTL, rgvswctl);
+
+        return true;
+}
+
 void ironlake_enable_drps(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
+        u32 rgvmodectl = I915_READ(MEMMODECTL);
         u8 fmax, fmin, fstart, vstart;
         int i = 0;
 
@@ -5045,13 +5105,21 @@ void ironlake_enable_drps(struct drm_device *dev)
         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
                 MEMMODE_FSTART_SHIFT;
+        fstart = fmax;
+
         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
                 PXVFREQ_PX_SHIFT;
 
-        dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
+        dev_priv->fmax = fstart; /* IPS callback will increase this */
+        dev_priv->fstart = fstart;
+
+        dev_priv->max_delay = fmax;
         dev_priv->min_delay = fmin;
         dev_priv->cur_delay = fstart;
 
+        DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
+                         fstart);
+
         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
 
         /*
@@ -5073,20 +5141,19 @@ void ironlake_enable_drps(struct drm_device *dev)
         }
         msleep(1);
 
-        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
-                (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
-        I915_WRITE(MEMSWCTL, rgvswctl);
-        POSTING_READ(MEMSWCTL);
+        ironlake_set_drps(dev, fstart);
 
-        rgvswctl |= MEMCTL_CMD_STS;
-        I915_WRITE(MEMSWCTL, rgvswctl);
+        dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
+                I915_READ(0x112e0);
+        dev_priv->last_time1 = jiffies_to_msecs(jiffies);
+        dev_priv->last_count2 = I915_READ(0x112f4);
+        getrawmonotonic(&dev_priv->last_time2);
 }
 
 void ironlake_disable_drps(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 rgvswctl;
-        u8 fstart;
+        u16 rgvswctl = I915_READ16(MEMSWCTL);
 
         /* Ack interrupts, disable EFC interrupt */
         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
@@ -5096,11 +5163,7 @@ void ironlake_disable_drps(struct drm_device *dev)
         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
 
         /* Go back to the starting frequency */
-        fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
-                MEMMODE_FSTART_SHIFT;
-        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
-                (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
-        I915_WRITE(MEMSWCTL, rgvswctl);
+        ironlake_set_drps(dev, dev_priv->fstart);
         msleep(1);
         rgvswctl |= MEMCTL_CMD_STS;
         I915_WRITE(MEMSWCTL, rgvswctl);
@@ -5108,6 +5171,92 @@ void ironlake_disable_drps(struct drm_device *dev)
 
 }
 
+static unsigned long intel_pxfreq(u32 vidfreq)
+{
+        unsigned long freq;
+        int div = (vidfreq & 0x3f0000) >> 16;
+        int post = (vidfreq & 0x3000) >> 12;
+        int pre = (vidfreq & 0x7);
+
+        if (!pre)
+                return 0;
+
+        freq = ((div * 133333) / ((1<<post) * pre));
+
+        return freq;
+}
+
+void intel_init_emon(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 lcfuse;
+        u8 pxw[16];
+        int i;
+
+        /* Disable to program */
+        I915_WRITE(ECR, 0);
+        POSTING_READ(ECR);
+
+        /* Program energy weights for various events */
+        I915_WRITE(SDEW, 0x15040d00);
+        I915_WRITE(CSIEW0, 0x007f0000);
+        I915_WRITE(CSIEW1, 0x1e220004);
+        I915_WRITE(CSIEW2, 0x04000004);
+
+        for (i = 0; i < 5; i++)
+                I915_WRITE(PEW + (i * 4), 0);
+        for (i = 0; i < 3; i++)
+                I915_WRITE(DEW + (i * 4), 0);
+
+        /* Program P-state weights to account for frequency power adjustment */
+        for (i = 0; i < 16; i++) {
+                u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
+                unsigned long freq = intel_pxfreq(pxvidfreq);
+                unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
+                        PXVFREQ_PX_SHIFT;
+                unsigned long val;
+
+                val = vid * vid;
+                val *= (freq / 1000);
+                val *= 255;
+                val /= (127*127*900);
+                if (val > 0xff)
+                        DRM_ERROR("bad pxval: %ld\n", val);
+                pxw[i] = val;
+        }
+        /* Render standby states get 0 weight */
+        pxw[14] = 0;
+        pxw[15] = 0;
+
+        for (i = 0; i < 4; i++) {
+                u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
+                        (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
+                I915_WRITE(PXW + (i * 4), val);
+        }
+
+        /* Adjust magic regs to magic values (more experimental results) */
+        I915_WRITE(OGW0, 0);
+        I915_WRITE(OGW1, 0);
+        I915_WRITE(EG0, 0x00007f00);
+        I915_WRITE(EG1, 0x0000000e);
+        I915_WRITE(EG2, 0x000e0000);
+        I915_WRITE(EG3, 0x68000300);
+        I915_WRITE(EG4, 0x42000000);
+        I915_WRITE(EG5, 0x00140031);
+        I915_WRITE(EG6, 0);
+        I915_WRITE(EG7, 0);
+
+        for (i = 0; i < 8; i++)
+                I915_WRITE(PXWL + (i * 4), 0);
+
+        /* Enable PMON + select events */
+        I915_WRITE(ECR, 0x80000019);
+
+        lcfuse = I915_READ(LCFUSE02);
+
+        dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
+}
+
 void intel_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5277,11 +5426,13 @@ static void intel_init_display(struct drm_device *dev)
                         dev_priv->display.update_wm = NULL;
         } else if (IS_PINEVIEW(dev)) {
                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
+                                            dev_priv->is_ddr3,
                                             dev_priv->fsb_freq,
                                             dev_priv->mem_freq)) {
                         DRM_INFO("failed to find known CxSR latency "
-                                 "(found fsb freq %d, mem freq %d), "
+                                 "(found ddr%s fsb freq %d, mem freq %d), "
                                  "disabling CxSR\n",
+                                 (dev_priv->is_ddr3 == 1) ? "3": "2",
                                  dev_priv->fsb_freq, dev_priv->mem_freq);
                         /* Disable CxSR and never update its watermark again */
                         pineview_disable_cxsr(dev);
@@ -5354,8 +5505,10 @@ void intel_modeset_init(struct drm_device *dev)
 
         intel_init_clock_gating(dev);
 
-        if (IS_IRONLAKE_M(dev))
+        if (IS_IRONLAKE_M(dev)) {
                 ironlake_enable_drps(dev);
+                intel_init_emon(dev);
+        }
 
         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,