diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_crt.c | 50 |
1 files changed, 11 insertions, 39 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index e5051446c48e..9f3d3e563414 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c | |||
| @@ -39,7 +39,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode) | |||
| 39 | struct drm_i915_private *dev_priv = dev->dev_private; | 39 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 40 | u32 temp, reg; | 40 | u32 temp, reg; |
| 41 | 41 | ||
| 42 | if (IS_IGDNG(dev)) | 42 | if (IS_IRONLAKE(dev)) |
| 43 | reg = PCH_ADPA; | 43 | reg = PCH_ADPA; |
| 44 | else | 44 | else |
| 45 | reg = ADPA; | 45 | reg = ADPA; |
| @@ -64,34 +64,6 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode) | |||
| 64 | } | 64 | } |
| 65 | 65 | ||
| 66 | I915_WRITE(reg, temp); | 66 | I915_WRITE(reg, temp); |
| 67 | |||
| 68 | if (IS_IGD(dev)) { | ||
| 69 | if (mode == DRM_MODE_DPMS_OFF) { | ||
| 70 | /* turn off DAC */ | ||
| 71 | temp = I915_READ(PORT_HOTPLUG_EN); | ||
| 72 | temp &= ~CRT_EOS_INT_EN; | ||
| 73 | I915_WRITE(PORT_HOTPLUG_EN, temp); | ||
| 74 | |||
| 75 | temp = I915_READ(PORT_HOTPLUG_STAT); | ||
| 76 | if (temp & CRT_EOS_INT_STATUS) | ||
| 77 | I915_WRITE(PORT_HOTPLUG_STAT, | ||
| 78 | CRT_EOS_INT_STATUS); | ||
| 79 | } else { | ||
| 80 | /* turn on DAC. EOS interrupt must be enabled after DAC | ||
| 81 | * is enabled, so it sounds not good to enable it in | ||
| 82 | * i915_driver_irq_postinstall() | ||
| 83 | * wait 12.5ms after DAC is enabled | ||
| 84 | */ | ||
| 85 | msleep(13); | ||
| 86 | temp = I915_READ(PORT_HOTPLUG_STAT); | ||
| 87 | if (temp & CRT_EOS_INT_STATUS) | ||
| 88 | I915_WRITE(PORT_HOTPLUG_STAT, | ||
| 89 | CRT_EOS_INT_STATUS); | ||
| 90 | temp = I915_READ(PORT_HOTPLUG_EN); | ||
| 91 | temp |= CRT_EOS_INT_EN; | ||
| 92 | I915_WRITE(PORT_HOTPLUG_EN, temp); | ||
| 93 | } | ||
| 94 | } | ||
| 95 | } | 67 | } |
| 96 | 68 | ||
| 97 | static int intel_crt_mode_valid(struct drm_connector *connector, | 69 | static int intel_crt_mode_valid(struct drm_connector *connector, |
| @@ -141,7 +113,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, | |||
| 141 | else | 113 | else |
| 142 | dpll_md_reg = DPLL_B_MD; | 114 | dpll_md_reg = DPLL_B_MD; |
| 143 | 115 | ||
| 144 | if (IS_IGDNG(dev)) | 116 | if (IS_IRONLAKE(dev)) |
| 145 | adpa_reg = PCH_ADPA; | 117 | adpa_reg = PCH_ADPA; |
| 146 | else | 118 | else |
| 147 | adpa_reg = ADPA; | 119 | adpa_reg = ADPA; |
| @@ -150,7 +122,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, | |||
| 150 | * Disable separate mode multiplier used when cloning SDVO to CRT | 122 | * Disable separate mode multiplier used when cloning SDVO to CRT |
| 151 | * XXX this needs to be adjusted when we really are cloning | 123 | * XXX this needs to be adjusted when we really are cloning |
| 152 | */ | 124 | */ |
| 153 | if (IS_I965G(dev) && !IS_IGDNG(dev)) { | 125 | if (IS_I965G(dev) && !IS_IRONLAKE(dev)) { |
| 154 | dpll_md = I915_READ(dpll_md_reg); | 126 | dpll_md = I915_READ(dpll_md_reg); |
| 155 | I915_WRITE(dpll_md_reg, | 127 | I915_WRITE(dpll_md_reg, |
| 156 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); | 128 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); |
| @@ -164,18 +136,18 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, | |||
| 164 | 136 | ||
| 165 | if (intel_crtc->pipe == 0) { | 137 | if (intel_crtc->pipe == 0) { |
| 166 | adpa |= ADPA_PIPE_A_SELECT; | 138 | adpa |= ADPA_PIPE_A_SELECT; |
| 167 | if (!IS_IGDNG(dev)) | 139 | if (!IS_IRONLAKE(dev)) |
| 168 | I915_WRITE(BCLRPAT_A, 0); | 140 | I915_WRITE(BCLRPAT_A, 0); |
| 169 | } else { | 141 | } else { |
| 170 | adpa |= ADPA_PIPE_B_SELECT; | 142 | adpa |= ADPA_PIPE_B_SELECT; |
| 171 | if (!IS_IGDNG(dev)) | 143 | if (!IS_IRONLAKE(dev)) |
| 172 | I915_WRITE(BCLRPAT_B, 0); | 144 | I915_WRITE(BCLRPAT_B, 0); |
| 173 | } | 145 | } |
| 174 | 146 | ||
| 175 | I915_WRITE(adpa_reg, adpa); | 147 | I915_WRITE(adpa_reg, adpa); |
| 176 | } | 148 | } |
| 177 | 149 | ||
| 178 | static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector) | 150 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
| 179 | { | 151 | { |
| 180 | struct drm_device *dev = connector->dev; | 152 | struct drm_device *dev = connector->dev; |
| 181 | struct drm_i915_private *dev_priv = dev->dev_private; | 153 | struct drm_i915_private *dev_priv = dev->dev_private; |
| @@ -194,7 +166,7 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector) | |||
| 194 | ADPA_CRT_HOTPLUG_ENABLE | | 166 | ADPA_CRT_HOTPLUG_ENABLE | |
| 195 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER); | 167 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER); |
| 196 | 168 | ||
| 197 | DRM_DEBUG("pch crt adpa 0x%x", adpa); | 169 | DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa); |
| 198 | I915_WRITE(PCH_ADPA, adpa); | 170 | I915_WRITE(PCH_ADPA, adpa); |
| 199 | 171 | ||
| 200 | while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0) | 172 | while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0) |
| @@ -227,8 +199,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |||
| 227 | u32 hotplug_en; | 199 | u32 hotplug_en; |
| 228 | int i, tries = 0; | 200 | int i, tries = 0; |
| 229 | 201 | ||
| 230 | if (IS_IGDNG(dev)) | 202 | if (IS_IRONLAKE(dev)) |
| 231 | return intel_igdng_crt_detect_hotplug(connector); | 203 | return intel_ironlake_crt_detect_hotplug(connector); |
| 232 | 204 | ||
| 233 | /* | 205 | /* |
| 234 | * On 4 series desktop, CRT detect sequence need to be done twice | 206 | * On 4 series desktop, CRT detect sequence need to be done twice |
| @@ -549,12 +521,12 @@ void intel_crt_init(struct drm_device *dev) | |||
| 549 | &intel_output->enc); | 521 | &intel_output->enc); |
| 550 | 522 | ||
| 551 | /* Set up the DDC bus. */ | 523 | /* Set up the DDC bus. */ |
| 552 | if (IS_IGDNG(dev)) | 524 | if (IS_IRONLAKE(dev)) |
| 553 | i2c_reg = PCH_GPIOA; | 525 | i2c_reg = PCH_GPIOA; |
| 554 | else { | 526 | else { |
| 555 | i2c_reg = GPIOA; | 527 | i2c_reg = GPIOA; |
| 556 | /* Use VBT information for CRT DDC if available */ | 528 | /* Use VBT information for CRT DDC if available */ |
| 557 | if (dev_priv->crt_ddc_bus != -1) | 529 | if (dev_priv->crt_ddc_bus != 0) |
| 558 | i2c_reg = dev_priv->crt_ddc_bus; | 530 | i2c_reg = dev_priv->crt_ddc_bus; |
| 559 | } | 531 | } |
| 560 | intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); | 532 | intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); |
