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path: root/drivers/gpu/drm/i915/i915_suspend.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c40
1 files changed, 7 insertions, 33 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 8150fdc08d49..56785e8fb2eb 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -236,19 +236,9 @@ static void i915_save_display(struct drm_device *dev)
236 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR); 236 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
237 } 237 }
238 238
239 /* Only regfile.save FBC state on the platform that supports FBC */ 239 /* save FBC interval */
240 if (HAS_FBC(dev)) { 240 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
241 if (HAS_PCH_SPLIT(dev)) { 241 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
242 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
243 } else if (IS_GM45(dev)) {
244 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
245 } else {
246 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
247 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
248 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
249 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
250 }
251 }
252 242
253 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 243 if (!drm_core_check_feature(dev, DRIVER_MODESET))
254 i915_save_vga(dev); 244 i915_save_vga(dev);
@@ -300,18 +290,10 @@ static void i915_restore_display(struct drm_device *dev)
300 290
301 /* only restore FBC info on the platform that supports FBC*/ 291 /* only restore FBC info on the platform that supports FBC*/
302 intel_disable_fbc(dev); 292 intel_disable_fbc(dev);
303 if (HAS_FBC(dev)) { 293
304 if (HAS_PCH_SPLIT(dev)) { 294 /* restore FBC interval */
305 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE); 295 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
306 } else if (IS_GM45(dev)) { 296 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
307 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
308 } else {
309 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
310 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
311 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
312 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
313 }
314 }
315 297
316 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 298 if (!drm_core_check_feature(dev, DRIVER_MODESET))
317 i915_restore_vga(dev); 299 i915_restore_vga(dev);
@@ -324,10 +306,6 @@ int i915_save_state(struct drm_device *dev)
324 struct drm_i915_private *dev_priv = dev->dev_private; 306 struct drm_i915_private *dev_priv = dev->dev_private;
325 int i; 307 int i;
326 308
327 if (INTEL_INFO(dev)->gen <= 4)
328 pci_read_config_byte(dev->pdev, LBB,
329 &dev_priv->regfile.saveLBB);
330
331 mutex_lock(&dev->struct_mutex); 309 mutex_lock(&dev->struct_mutex);
332 310
333 i915_save_display(dev); 311 i915_save_display(dev);
@@ -377,10 +355,6 @@ int i915_restore_state(struct drm_device *dev)
377 struct drm_i915_private *dev_priv = dev->dev_private; 355 struct drm_i915_private *dev_priv = dev->dev_private;
378 int i; 356 int i;
379 357
380 if (INTEL_INFO(dev)->gen <= 4)
381 pci_write_config_byte(dev->pdev, LBB,
382 dev_priv->regfile.saveLBB);
383
384 mutex_lock(&dev->struct_mutex); 358 mutex_lock(&dev->struct_mutex);
385 359
386 i915_gem_restore_fences(dev); 360 i915_gem_restore_fences(dev);