1 files changed, 19 insertions, 10 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88a2c0792f26..56708c64e68f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1447,6 +1447,8 @@
 #define   MCH_SSKPD_WM0_MASK            0x3f
 #define   MCH_SSKPD_WM0_VAL             0xc
 
+#define MCH_SECP_NRG_STTS               (MCHBAR_MIRROR_BASE_SNB + 0x592c)
+
 /* Clocking configuration register */
 #define CLKCFG                  0x10c00
 #define CLKCFG_FSB_400                                  (5 << 0)        /* hrawclk 100 */
@@ -1703,15 +1705,26 @@
  */
 #define CCID                    0x2180
 #define   CCID_EN               (1<<0)
+/*
+ * Notes on SNB/IVB/VLV context size:
+ * - Power context is saved elsewhere (LLC or stolen)
+ * - Ring/execlist context is saved on SNB, not on IVB
+ * - Extended context size already includes render context size
+ * - We always need to follow the extended context size.
+ *   SNB BSpec has comments indicating that we should use the
+ *   render context size instead if execlists are disabled, but
+ *   based on empirical testing that's just nonsense.
+ * - Pipelined/VF state is saved on SNB/IVB respectively
+ * - GT1 size just indicates how much of render context
+ *   doesn't need saving on GT1
+ */
 #define CXT_SIZE                0x21a0
 #define GEN6_CXT_POWER_SIZE(cxt_reg)    ((cxt_reg >> 24) & 0x3f)
 #define GEN6_CXT_RING_SIZE(cxt_reg)     ((cxt_reg >> 18) & 0x3f)
 #define GEN6_CXT_RENDER_SIZE(cxt_reg)   ((cxt_reg >> 12) & 0x3f)
 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
-#define GEN6_CXT_TOTAL_SIZE(cxt_reg)    (GEN6_CXT_POWER_SIZE(cxt_reg) + \
-                                        GEN6_CXT_RING_SIZE(cxt_reg) + \
-                                        GEN6_CXT_RENDER_SIZE(cxt_reg) + \
+#define GEN6_CXT_TOTAL_SIZE(cxt_reg)    (GEN6_CXT_RING_SIZE(cxt_reg) + \
                                         GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
                                         GEN6_CXT_PIPELINE_SIZE(cxt_reg))
 #define GEN7_CXT_SIZE           0x21a8
@@ -1721,11 +1734,7 @@
 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
 #define GEN7_CXT_GT1_SIZE(ctx_reg)      ((ctx_reg >> 6) & 0x7)
 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)  ((ctx_reg >> 0) & 0x3f)
-#define GEN7_CXT_TOTAL_SIZE(ctx_reg)    (GEN7_CXT_POWER_SIZE(ctx_reg) + \
-                                         GEN7_CXT_RING_SIZE(ctx_reg) + \
-                                         GEN7_CXT_RENDER_SIZE(ctx_reg) + \
-                                         GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
-                                         GEN7_CXT_GT1_SIZE(ctx_reg) + \
+#define GEN7_CXT_TOTAL_SIZE(ctx_reg)    (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
                                          GEN7_CXT_VFSTATE_SIZE(ctx_reg))
 /* Haswell does have the CXT_SIZE register however it does not appear to be
  * valid. Now, docs explain in dwords what is in the context object. The full
@@ -4827,8 +4836,8 @@
 #define HSW_PWR_WELL_DRIVER                     0x45404 /* CTL2 */
 #define HSW_PWR_WELL_KVMR                       0x45408 /* CTL3 */
 #define HSW_PWR_WELL_DEBUG                      0x4540C /* CTL4 */
-#define   HSW_PWR_WELL_ENABLE                   (1<<31)
-#define   HSW_PWR_WELL_STATE                    (1<<30)
+#define   HSW_PWR_WELL_ENABLE_REQUEST           (1<<31)
+#define   HSW_PWR_WELL_STATE_ENABLED            (1<<30)
 #define HSW_PWR_WELL_CTL5                       0x45410
 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP       (1<<31)
 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE        (1<<20)