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path: root/drivers/gpu/drm/i915/i915_reg.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h30
1 files changed, 21 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3afb783cb9d..f9607387c00c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -319,6 +319,8 @@
319#define RING_HWS_PGA(base) ((base)+0x80) 319#define RING_HWS_PGA(base) ((base)+0x80)
320#define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 320#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
321#define RENDER_HWS_PGA_GEN7 (0x04080) 321#define RENDER_HWS_PGA_GEN7 (0x04080)
322#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
323#define DONE_REG 0x40b0
322#define BSD_HWS_PGA_GEN7 (0x04180) 324#define BSD_HWS_PGA_GEN7 (0x04180)
323#define BLT_HWS_PGA_GEN7 (0x04280) 325#define BLT_HWS_PGA_GEN7 (0x04280)
324#define RING_ACTHD(base) ((base)+0x74) 326#define RING_ACTHD(base) ((base)+0x74)
@@ -352,6 +354,12 @@
352#define IPEIR_I965 0x02064 354#define IPEIR_I965 0x02064
353#define IPEHR_I965 0x02068 355#define IPEHR_I965 0x02068
354#define INSTDONE_I965 0x0206c 356#define INSTDONE_I965 0x0206c
357#define RING_IPEIR(base) ((base)+0x64)
358#define RING_IPEHR(base) ((base)+0x68)
359#define RING_INSTDONE(base) ((base)+0x6c)
360#define RING_INSTPS(base) ((base)+0x70)
361#define RING_DMA_FADD(base) ((base)+0x78)
362#define RING_INSTPM(base) ((base)+0xc0)
355#define INSTPS 0x02070 /* 965+ only */ 363#define INSTPS 0x02070 /* 965+ only */
356#define INSTDONE1 0x0207c /* 965+ only */ 364#define INSTDONE1 0x0207c /* 965+ only */
357#define ACTHD_I965 0x02074 365#define ACTHD_I965 0x02074
@@ -365,14 +373,6 @@
365#define INSTDONE 0x02090 373#define INSTDONE 0x02090
366#define NOPID 0x02094 374#define NOPID 0x02094
367#define HWSTAM 0x02098 375#define HWSTAM 0x02098
368#define VCS_INSTDONE 0x1206C
369#define VCS_IPEIR 0x12064
370#define VCS_IPEHR 0x12068
371#define VCS_ACTHD 0x12074
372#define BCS_INSTDONE 0x2206C
373#define BCS_IPEIR 0x22064
374#define BCS_IPEHR 0x22068
375#define BCS_ACTHD 0x22074
376 376
377#define ERROR_GEN6 0x040a0 377#define ERROR_GEN6 0x040a0
378 378
@@ -391,7 +391,7 @@
391 391
392#define MI_MODE 0x0209c 392#define MI_MODE 0x0209c
393# define VS_TIMER_DISPATCH (1 << 6) 393# define VS_TIMER_DISPATCH (1 << 6)
394# define MI_FLUSH_ENABLE (1 << 11) 394# define MI_FLUSH_ENABLE (1 << 12)
395 395
396#define GFX_MODE 0x02520 396#define GFX_MODE 0x02520
397#define GFX_MODE_GEN7 0x0229c 397#define GFX_MODE_GEN7 0x0229c
@@ -3742,4 +3742,16 @@
3742 */ 3742 */
3743#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 3743#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
3744 3744
3745#define IBX_AUD_CONFIG_A 0xe2000
3746#define CPT_AUD_CONFIG_A 0xe5000
3747#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
3748#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
3749#define AUD_CONFIG_UPPER_N_SHIFT 20
3750#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
3751#define AUD_CONFIG_LOWER_N_SHIFT 4
3752#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
3753#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
3754#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
3755#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
3756
3745#endif /* _I915_REG_H_ */ 3757#endif /* _I915_REG_H_ */