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Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h15
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 76126e0ae609..a48b7cad6f11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2122,9 +2122,13 @@
2122 * Please check the detailed lore in the commit message for for experimental 2122 * Please check the detailed lore in the commit message for for experimental
2123 * evidence. 2123 * evidence.
2124 */ 2124 */
2125#define PORTD_HOTPLUG_LIVE_STATUS (1 << 29) 2125#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2126#define PORTC_HOTPLUG_LIVE_STATUS (1 << 28) 2126#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2127#define PORTB_HOTPLUG_LIVE_STATUS (1 << 27) 2127#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2128/* VLV DP/HDMI bits again match Bspec */
2129#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2130#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2131#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
2128#define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2132#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2129#define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2133#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2130#define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2134#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
@@ -2138,7 +2142,8 @@
2138#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2142#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2139#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2143#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2140#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2144#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2141#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (1 << 4) 2145#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2146
2142/* SDVO is different across gen3/4 */ 2147/* SDVO is different across gen3/4 */
2143#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2148#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2144#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2149#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
@@ -3573,8 +3578,6 @@
3573#define DISP_BASEADDR_MASK (0xfffff000) 3578#define DISP_BASEADDR_MASK (0xfffff000)
3574#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 3579#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3575#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 3580#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3576#define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3577 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3578 3581
3579/* VBIOS flags */ 3582/* VBIOS flags */
3580#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410) 3583#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)