diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 25ed911a3112..cb8f43429279 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -2471,6 +2471,9 @@ | |||
2471 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) | 2471 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
2472 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | 2472 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
2473 | 2473 | ||
2474 | #define PCH_3DCGDIS1 0x46024 | ||
2475 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) | ||
2476 | |||
2474 | #define FDI_PLL_FREQ_CTL 0x46030 | 2477 | #define FDI_PLL_FREQ_CTL 0x46030 |
2475 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) | 2478 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
2476 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 | 2479 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |
@@ -2588,6 +2591,13 @@ | |||
2588 | #define ILK_DISPLAY_CHICKEN2 0x42004 | 2591 | #define ILK_DISPLAY_CHICKEN2 0x42004 |
2589 | #define ILK_DPARB_GATE (1<<22) | 2592 | #define ILK_DPARB_GATE (1<<22) |
2590 | #define ILK_VSDPFD_FULL (1<<21) | 2593 | #define ILK_VSDPFD_FULL (1<<21) |
2594 | #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 | ||
2595 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) | ||
2596 | #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) | ||
2597 | #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) | ||
2598 | #define ILK_HDCP_DISABLE (1<<25) | ||
2599 | #define ILK_eDP_A_DISABLE (1<<24) | ||
2600 | #define ILK_DESKTOP (1<<23) | ||
2591 | #define ILK_DSPCLK_GATE 0x42020 | 2601 | #define ILK_DSPCLK_GATE 0x42020 |
2592 | #define ILK_DPARB_CLK_GATE (1<<5) | 2602 | #define ILK_DPARB_CLK_GATE (1<<5) |
2593 | /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ | 2603 | /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ |
@@ -3033,6 +3043,7 @@ | |||
3033 | #define TRANS_DP_10BPC (1<<9) | 3043 | #define TRANS_DP_10BPC (1<<9) |
3034 | #define TRANS_DP_6BPC (2<<9) | 3044 | #define TRANS_DP_6BPC (2<<9) |
3035 | #define TRANS_DP_12BPC (3<<9) | 3045 | #define TRANS_DP_12BPC (3<<9) |
3046 | #define TRANS_DP_BPC_MASK (3<<9) | ||
3036 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) | 3047 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
3037 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 | 3048 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 |
3038 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) | 3049 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) |