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path: root/drivers/gpu/drm/i915/i915_reg.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h43
1 files changed, 40 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d49b9507ed0..48d5e8e051cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -210,6 +210,14 @@
210#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 210#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
211#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 211#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
212#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 212#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
213/* IVB has funny definitions for which plane to flip. */
214#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
215#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
216#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
217#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
218#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
219#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
220
213#define MI_SET_CONTEXT MI_INSTR(0x18, 0) 221#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
214#define MI_MM_SPACE_GTT (1<<8) 222#define MI_MM_SPACE_GTT (1<<8)
215#define MI_MM_SPACE_PHYSICAL (0<<8) 223#define MI_MM_SPACE_PHYSICAL (0<<8)
@@ -3313,7 +3321,7 @@
3313 3321
3314/* PCH */ 3322/* PCH */
3315 3323
3316/* south display engine interrupt */ 3324/* south display engine interrupt: IBX */
3317#define SDE_AUDIO_POWER_D (1 << 27) 3325#define SDE_AUDIO_POWER_D (1 << 27)
3318#define SDE_AUDIO_POWER_C (1 << 26) 3326#define SDE_AUDIO_POWER_C (1 << 26)
3319#define SDE_AUDIO_POWER_B (1 << 25) 3327#define SDE_AUDIO_POWER_B (1 << 25)
@@ -3349,15 +3357,44 @@
3349#define SDE_TRANSA_CRC_ERR (1 << 1) 3357#define SDE_TRANSA_CRC_ERR (1 << 1)
3350#define SDE_TRANSA_FIFO_UNDER (1 << 0) 3358#define SDE_TRANSA_FIFO_UNDER (1 << 0)
3351#define SDE_TRANS_MASK (0x3f) 3359#define SDE_TRANS_MASK (0x3f)
3352/* CPT */ 3360
3353#define SDE_CRT_HOTPLUG_CPT (1 << 19) 3361/* south display engine interrupt: CPT/PPT */
3362#define SDE_AUDIO_POWER_D_CPT (1 << 31)
3363#define SDE_AUDIO_POWER_C_CPT (1 << 30)
3364#define SDE_AUDIO_POWER_B_CPT (1 << 29)
3365#define SDE_AUDIO_POWER_SHIFT_CPT 29
3366#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
3367#define SDE_AUXD_CPT (1 << 27)
3368#define SDE_AUXC_CPT (1 << 26)
3369#define SDE_AUXB_CPT (1 << 25)
3370#define SDE_AUX_MASK_CPT (7 << 25)
3354#define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3371#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3355#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3372#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3356#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3373#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3374#define SDE_CRT_HOTPLUG_CPT (1 << 19)
3357#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3375#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3358 SDE_PORTD_HOTPLUG_CPT | \ 3376 SDE_PORTD_HOTPLUG_CPT | \
3359 SDE_PORTC_HOTPLUG_CPT | \ 3377 SDE_PORTC_HOTPLUG_CPT | \
3360 SDE_PORTB_HOTPLUG_CPT) 3378 SDE_PORTB_HOTPLUG_CPT)
3379#define SDE_GMBUS_CPT (1 << 17)
3380#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3381#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3382#define SDE_FDI_RXC_CPT (1 << 8)
3383#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3384#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3385#define SDE_FDI_RXB_CPT (1 << 4)
3386#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3387#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3388#define SDE_FDI_RXA_CPT (1 << 0)
3389#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3390 SDE_AUDIO_CP_REQ_B_CPT | \
3391 SDE_AUDIO_CP_REQ_A_CPT)
3392#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3393 SDE_AUDIO_CP_CHG_B_CPT | \
3394 SDE_AUDIO_CP_CHG_A_CPT)
3395#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3396 SDE_FDI_RXB_CPT | \
3397 SDE_FDI_RXA_CPT)
3361 3398
3362#define SDEISR 0xc4000 3399#define SDEISR 0xc4000
3363#define SDEIMR 0xc4004 3400#define SDEIMR 0xc4004