1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0dfcbad4eb7b..6caa748fa00f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2261,6 +2261,8 @@
 #define BLC_PWM_CPU_CTL2        0x48250
 #define BLC_PWM_CPU_CTL         0x48254
 
+#define HSW_BLC_PWM2_CTL        0x48350
+
 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
 #define BLC_PWM_PCH_CTL1        0xc8250
@@ -2269,6 +2271,12 @@
 #define   BLM_PCH_POLARITY                      (1 << 29)
 #define BLC_PWM_PCH_CTL2        0xc8254
 
+#define UTIL_PIN_CTL            0x48400
+#define   UTIL_PIN_ENABLE       (1 << 31)
+
+#define PCH_GTC_CTL             0xe7000
+#define   PCH_GTC_ENABLE        (1 << 31)
+
 /* TV port control */
 #define TV_CTL                  0x68000
 /** Enables the TV encoder */
@@ -5009,7 +5017,14 @@
 #define  LCPLL_CLK_FREQ_450             (0<<26)
 #define  LCPLL_CD_CLOCK_DISABLE         (1<<25)
 #define  LCPLL_CD2X_CLOCK_DISABLE       (1<<23)
+#define  LCPLL_POWER_DOWN_ALLOW         (1<<22)
 #define  LCPLL_CD_SOURCE_FCLK           (1<<21)
+#define  LCPLL_CD_SOURCE_FCLK_DONE      (1<<19)
+
+#define D_COMP                          (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
+#define  D_COMP_RCOMP_IN_PROGRESS       (1<<9)
+#define  D_COMP_COMP_FORCE              (1<<8)
+#define  D_COMP_COMP_DISABLE            (1<<0)
 
 /* Pipe WM_LINETIME - watermark line time */
 #define PIPE_WM_LINETIME_A              0x45270