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path: root/drivers/gpu/drm/i915/i915_reg.h
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-rw-r--r--drivers/gpu/drm/i915/i915_reg.h133
1 files changed, 133 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44eabb088b48..d791043c8ec1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2461,6 +2461,8 @@
2461#define WM3_LP_ILK 0x45110 2461#define WM3_LP_ILK 0x45110
2462#define WM3_LP_EN (1<<31) 2462#define WM3_LP_EN (1<<31)
2463#define WM1S_LP_ILK 0x45120 2463#define WM1S_LP_ILK 0x45120
2464#define WM2S_LP_IVB 0x45124
2465#define WM3S_LP_IVB 0x45128
2464#define WM1S_LP_EN (1<<31) 2466#define WM1S_LP_EN (1<<31)
2465 2467
2466/* Memory latency timer register */ 2468/* Memory latency timer register */
@@ -2677,6 +2679,137 @@
2677#define _DSPBSURF 0x7119C 2679#define _DSPBSURF 0x7119C
2678#define _DSPBTILEOFF 0x711A4 2680#define _DSPBTILEOFF 0x711A4
2679 2681
2682/* Sprite A control */
2683#define _DVSACNTR 0x72180
2684#define DVS_ENABLE (1<<31)
2685#define DVS_GAMMA_ENABLE (1<<30)
2686#define DVS_PIXFORMAT_MASK (3<<25)
2687#define DVS_FORMAT_YUV422 (0<<25)
2688#define DVS_FORMAT_RGBX101010 (1<<25)
2689#define DVS_FORMAT_RGBX888 (2<<25)
2690#define DVS_FORMAT_RGBX161616 (3<<25)
2691#define DVS_SOURCE_KEY (1<<22)
2692#define DVS_RGB_ORDER_RGBX (1<<20)
2693#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
2694#define DVS_YUV_ORDER_YUYV (0<<16)
2695#define DVS_YUV_ORDER_UYVY (1<<16)
2696#define DVS_YUV_ORDER_YVYU (2<<16)
2697#define DVS_YUV_ORDER_VYUY (3<<16)
2698#define DVS_DEST_KEY (1<<2)
2699#define DVS_TRICKLE_FEED_DISABLE (1<<14)
2700#define DVS_TILED (1<<10)
2701#define _DVSALINOFF 0x72184
2702#define _DVSASTRIDE 0x72188
2703#define _DVSAPOS 0x7218c
2704#define _DVSASIZE 0x72190
2705#define _DVSAKEYVAL 0x72194
2706#define _DVSAKEYMSK 0x72198
2707#define _DVSASURF 0x7219c
2708#define _DVSAKEYMAXVAL 0x721a0
2709#define _DVSATILEOFF 0x721a4
2710#define _DVSASURFLIVE 0x721ac
2711#define _DVSASCALE 0x72204
2712#define DVS_SCALE_ENABLE (1<<31)
2713#define DVS_FILTER_MASK (3<<29)
2714#define DVS_FILTER_MEDIUM (0<<29)
2715#define DVS_FILTER_ENHANCING (1<<29)
2716#define DVS_FILTER_SOFTENING (2<<29)
2717#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
2718#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
2719#define _DVSAGAMC 0x72300
2720
2721#define _DVSBCNTR 0x73180
2722#define _DVSBLINOFF 0x73184
2723#define _DVSBSTRIDE 0x73188
2724#define _DVSBPOS 0x7318c
2725#define _DVSBSIZE 0x73190
2726#define _DVSBKEYVAL 0x73194
2727#define _DVSBKEYMSK 0x73198
2728#define _DVSBSURF 0x7319c
2729#define _DVSBKEYMAXVAL 0x731a0
2730#define _DVSBTILEOFF 0x731a4
2731#define _DVSBSURFLIVE 0x731ac
2732#define _DVSBSCALE 0x73204
2733#define _DVSBGAMC 0x73300
2734
2735#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
2736#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
2737#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
2738#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
2739#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
2740#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
2741#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
2742#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
2743
2744#define _SPRA_CTL 0x70280
2745#define SPRITE_ENABLE (1<<31)
2746#define SPRITE_GAMMA_ENABLE (1<<30)
2747#define SPRITE_PIXFORMAT_MASK (7<<25)
2748#define SPRITE_FORMAT_YUV422 (0<<25)
2749#define SPRITE_FORMAT_RGBX101010 (1<<25)
2750#define SPRITE_FORMAT_RGBX888 (2<<25)
2751#define SPRITE_FORMAT_RGBX161616 (3<<25)
2752#define SPRITE_FORMAT_YUV444 (4<<25)
2753#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
2754#define SPRITE_CSC_ENABLE (1<<24)
2755#define SPRITE_SOURCE_KEY (1<<22)
2756#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
2757#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
2758#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
2759#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
2760#define SPRITE_YUV_ORDER_YUYV (0<<16)
2761#define SPRITE_YUV_ORDER_UYVY (1<<16)
2762#define SPRITE_YUV_ORDER_YVYU (2<<16)
2763#define SPRITE_YUV_ORDER_VYUY (3<<16)
2764#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
2765#define SPRITE_INT_GAMMA_ENABLE (1<<13)
2766#define SPRITE_TILED (1<<10)
2767#define SPRITE_DEST_KEY (1<<2)
2768#define _SPRA_LINOFF 0x70284
2769#define _SPRA_STRIDE 0x70288
2770#define _SPRA_POS 0x7028c
2771#define _SPRA_SIZE 0x70290
2772#define _SPRA_KEYVAL 0x70294
2773#define _SPRA_KEYMSK 0x70298
2774#define _SPRA_SURF 0x7029c
2775#define _SPRA_KEYMAX 0x702a0
2776#define _SPRA_TILEOFF 0x702a4
2777#define _SPRA_SCALE 0x70304
2778#define SPRITE_SCALE_ENABLE (1<<31)
2779#define SPRITE_FILTER_MASK (3<<29)
2780#define SPRITE_FILTER_MEDIUM (0<<29)
2781#define SPRITE_FILTER_ENHANCING (1<<29)
2782#define SPRITE_FILTER_SOFTENING (2<<29)
2783#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
2784#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
2785#define _SPRA_GAMC 0x70400
2786
2787#define _SPRB_CTL 0x71280
2788#define _SPRB_LINOFF 0x71284
2789#define _SPRB_STRIDE 0x71288
2790#define _SPRB_POS 0x7128c
2791#define _SPRB_SIZE 0x71290
2792#define _SPRB_KEYVAL 0x71294
2793#define _SPRB_KEYMSK 0x71298
2794#define _SPRB_SURF 0x7129c
2795#define _SPRB_KEYMAX 0x712a0
2796#define _SPRB_TILEOFF 0x712a4
2797#define _SPRB_SCALE 0x71304
2798#define _SPRB_GAMC 0x71400
2799
2800#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
2801#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
2802#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
2803#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
2804#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
2805#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
2806#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
2807#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
2808#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
2809#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
2810#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
2811#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
2812
2680/* VBIOS regs */ 2813/* VBIOS regs */
2681#define VGACNTRL 0x71400 2814#define VGACNTRL 0x71400
2682# define VGA_DISP_DISABLE (1 << 31) 2815# define VGA_DISP_DISABLE (1 << 31)