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path: root/drivers/gpu/drm/i915/i915_reg.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3d59862c7ccd..cbbf59f56dfa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -298,6 +298,10 @@
298#define INSTDONE 0x02090 298#define INSTDONE 0x02090
299#define NOPID 0x02094 299#define NOPID 0x02094
300#define HWSTAM 0x02098 300#define HWSTAM 0x02098
301
302#define MI_MODE 0x0209c
303# define VS_TIMER_DISPATCH (1 << 6)
304
301#define SCPD0 0x0209c /* 915+ only */ 305#define SCPD0 0x0209c /* 915+ only */
302#define IER 0x020a0 306#define IER 0x020a0
303#define IIR 0x020a4 307#define IIR 0x020a4
@@ -366,7 +370,7 @@
366#define FBC_CTL_PERIODIC (1<<30) 370#define FBC_CTL_PERIODIC (1<<30)
367#define FBC_CTL_INTERVAL_SHIFT (16) 371#define FBC_CTL_INTERVAL_SHIFT (16)
368#define FBC_CTL_UNCOMPRESSIBLE (1<<14) 372#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
369#define FBC_C3_IDLE (1<<13) 373#define FBC_CTL_C3_IDLE (1<<13)
370#define FBC_CTL_STRIDE_SHIFT (5) 374#define FBC_CTL_STRIDE_SHIFT (5)
371#define FBC_CTL_FENCENO (1<<0) 375#define FBC_CTL_FENCENO (1<<0)
372#define FBC_COMMAND 0x0320c 376#define FBC_COMMAND 0x0320c
@@ -2172,6 +2176,14 @@
2172#define DISPLAY_PORT_PLL_BIOS_1 0x46010 2176#define DISPLAY_PORT_PLL_BIOS_1 0x46010
2173#define DISPLAY_PORT_PLL_BIOS_2 0x46014 2177#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2174 2178
2179#define PCH_DSPCLK_GATE_D 0x42020
2180# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2181# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2182
2183#define PCH_3DCGDIS0 0x46020
2184# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2185# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2186
2175#define FDI_PLL_FREQ_CTL 0x46030 2187#define FDI_PLL_FREQ_CTL 0x46030
2176#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2188#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2177#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2189#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00