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path: root/drivers/gpu/drm/i915/i915_irq.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8a667f1db75a..0a3a5806a12e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -53,7 +53,7 @@
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54 54
55/** Interrupts that we mask and unmask at runtime. */ 55/** Interrupts that we mask and unmask at runtime. */
56#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) 56#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57 57
58#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ 58#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS) 59 PIPE_VBLANK_INTERRUPT_STATUS)
@@ -362,6 +362,9 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev)
362 dev_priv->hangcheck_count = 0; 362 dev_priv->hangcheck_count = 0;
363 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); 363 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
364 } 364 }
365 if (gt_iir & GT_BSD_USER_INTERRUPT)
366 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
367
365 368
366 if (de_iir & DE_GSE) 369 if (de_iir & DE_GSE)
367 ironlake_opregion_gse_intr(dev); 370 ironlake_opregion_gse_intr(dev);
@@ -944,6 +947,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
944 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); 947 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
945 } 948 }
946 949
950 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
951 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
952
947 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) 953 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
948 intel_prepare_page_flip(dev, 0); 954 intel_prepare_page_flip(dev, 0);
949 955
@@ -1297,7 +1303,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1297 /* enable kind of interrupts always enabled */ 1303 /* enable kind of interrupts always enabled */
1298 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1304 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1299 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1305 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1300 u32 render_mask = GT_PIPE_NOTIFY; 1306 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1301 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | 1307 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1302 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; 1308 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1303 1309
@@ -1376,6 +1382,9 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1376 1382
1377 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue); 1383 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1378 1384
1385 if (HAS_BSD(dev))
1386 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1387
1379 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1388 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1380 1389
1381 if (HAS_PCH_SPLIT(dev)) 1390 if (HAS_PCH_SPLIT(dev))