diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 163 |
1 files changed, 99 insertions, 64 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index aa7fd82aa6eb..85f4c5de97e2 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -43,10 +43,13 @@ | |||
43 | * we leave them always unmasked in IMR and then control enabling them through | 43 | * we leave them always unmasked in IMR and then control enabling them through |
44 | * PIPESTAT alone. | 44 | * PIPESTAT alone. |
45 | */ | 45 | */ |
46 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ | 46 | #define I915_INTERRUPT_ENABLE_FIX \ |
47 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | 47 | (I915_ASLE_INTERRUPT | \ |
48 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | 48 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
49 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | 49 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ |
50 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | ||
51 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | ||
52 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | ||
50 | 53 | ||
51 | /** Interrupts that we mask and unmask at runtime. */ | 54 | /** Interrupts that we mask and unmask at runtime. */ |
52 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | 55 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) |
@@ -61,7 +64,7 @@ | |||
61 | DRM_I915_VBLANK_PIPE_B) | 64 | DRM_I915_VBLANK_PIPE_B) |
62 | 65 | ||
63 | void | 66 | void |
64 | igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | 67 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
65 | { | 68 | { |
66 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | 69 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { |
67 | dev_priv->gt_irq_mask_reg &= ~mask; | 70 | dev_priv->gt_irq_mask_reg &= ~mask; |
@@ -71,7 +74,7 @@ igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |||
71 | } | 74 | } |
72 | 75 | ||
73 | static inline void | 76 | static inline void |
74 | igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | 77 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
75 | { | 78 | { |
76 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | 79 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { |
77 | dev_priv->gt_irq_mask_reg |= mask; | 80 | dev_priv->gt_irq_mask_reg |= mask; |
@@ -82,7 +85,7 @@ igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |||
82 | 85 | ||
83 | /* For display hotplug interrupt */ | 86 | /* For display hotplug interrupt */ |
84 | void | 87 | void |
85 | igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | 88 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
86 | { | 89 | { |
87 | if ((dev_priv->irq_mask_reg & mask) != 0) { | 90 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
88 | dev_priv->irq_mask_reg &= ~mask; | 91 | dev_priv->irq_mask_reg &= ~mask; |
@@ -92,7 +95,7 @@ igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |||
92 | } | 95 | } |
93 | 96 | ||
94 | static inline void | 97 | static inline void |
95 | igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | 98 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
96 | { | 99 | { |
97 | if ((dev_priv->irq_mask_reg & mask) != mask) { | 100 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
98 | dev_priv->irq_mask_reg |= mask; | 101 | dev_priv->irq_mask_reg |= mask; |
@@ -157,6 +160,20 @@ i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |||
157 | } | 160 | } |
158 | 161 | ||
159 | /** | 162 | /** |
163 | * intel_enable_asle - enable ASLE interrupt for OpRegion | ||
164 | */ | ||
165 | void intel_enable_asle (struct drm_device *dev) | ||
166 | { | ||
167 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
168 | |||
169 | if (IS_IRONLAKE(dev)) | ||
170 | ironlake_enable_display_irq(dev_priv, DE_GSE); | ||
171 | else | ||
172 | i915_enable_pipestat(dev_priv, 1, | ||
173 | I915_LEGACY_BLC_EVENT_ENABLE); | ||
174 | } | ||
175 | |||
176 | /** | ||
160 | * i915_pipe_enabled - check if a pipe is enabled | 177 | * i915_pipe_enabled - check if a pipe is enabled |
161 | * @dev: DRM device | 178 | * @dev: DRM device |
162 | * @pipe: pipe to check | 179 | * @pipe: pipe to check |
@@ -191,7 +208,8 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |||
191 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | 208 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; |
192 | 209 | ||
193 | if (!i915_pipe_enabled(dev, pipe)) { | 210 | if (!i915_pipe_enabled(dev, pipe)) { |
194 | DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); | 211 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
212 | "pipe %d\n", pipe); | ||
195 | return 0; | 213 | return 0; |
196 | } | 214 | } |
197 | 215 | ||
@@ -220,7 +238,8 @@ u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) | |||
220 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | 238 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; |
221 | 239 | ||
222 | if (!i915_pipe_enabled(dev, pipe)) { | 240 | if (!i915_pipe_enabled(dev, pipe)) { |
223 | DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); | 241 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
242 | "pipe %d\n", pipe); | ||
224 | return 0; | 243 | return 0; |
225 | } | 244 | } |
226 | 245 | ||
@@ -250,12 +269,12 @@ static void i915_hotplug_work_func(struct work_struct *work) | |||
250 | drm_sysfs_hotplug_event(dev); | 269 | drm_sysfs_hotplug_event(dev); |
251 | } | 270 | } |
252 | 271 | ||
253 | irqreturn_t igdng_irq_handler(struct drm_device *dev) | 272 | irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
254 | { | 273 | { |
255 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 274 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
256 | int ret = IRQ_NONE; | 275 | int ret = IRQ_NONE; |
257 | u32 de_iir, gt_iir, de_ier; | 276 | u32 de_iir, gt_iir, de_ier, pch_iir; |
258 | u32 new_de_iir, new_gt_iir; | 277 | u32 new_de_iir, new_gt_iir, new_pch_iir; |
259 | struct drm_i915_master_private *master_priv; | 278 | struct drm_i915_master_private *master_priv; |
260 | 279 | ||
261 | /* disable master interrupt before clearing iir */ | 280 | /* disable master interrupt before clearing iir */ |
@@ -265,13 +284,18 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev) | |||
265 | 284 | ||
266 | de_iir = I915_READ(DEIIR); | 285 | de_iir = I915_READ(DEIIR); |
267 | gt_iir = I915_READ(GTIIR); | 286 | gt_iir = I915_READ(GTIIR); |
287 | pch_iir = I915_READ(SDEIIR); | ||
268 | 288 | ||
269 | for (;;) { | 289 | for (;;) { |
270 | if (de_iir == 0 && gt_iir == 0) | 290 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
271 | break; | 291 | break; |
272 | 292 | ||
273 | ret = IRQ_HANDLED; | 293 | ret = IRQ_HANDLED; |
274 | 294 | ||
295 | /* should clear PCH hotplug event before clear CPU irq */ | ||
296 | I915_WRITE(SDEIIR, pch_iir); | ||
297 | new_pch_iir = I915_READ(SDEIIR); | ||
298 | |||
275 | I915_WRITE(DEIIR, de_iir); | 299 | I915_WRITE(DEIIR, de_iir); |
276 | new_de_iir = I915_READ(DEIIR); | 300 | new_de_iir = I915_READ(DEIIR); |
277 | I915_WRITE(GTIIR, gt_iir); | 301 | I915_WRITE(GTIIR, gt_iir); |
@@ -291,8 +315,18 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev) | |||
291 | DRM_WAKEUP(&dev_priv->irq_queue); | 315 | DRM_WAKEUP(&dev_priv->irq_queue); |
292 | } | 316 | } |
293 | 317 | ||
318 | if (de_iir & DE_GSE) | ||
319 | ironlake_opregion_gse_intr(dev); | ||
320 | |||
321 | /* check event from PCH */ | ||
322 | if ((de_iir & DE_PCH_EVENT) && | ||
323 | (pch_iir & SDE_HOTPLUG_MASK)) { | ||
324 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | ||
325 | } | ||
326 | |||
294 | de_iir = new_de_iir; | 327 | de_iir = new_de_iir; |
295 | gt_iir = new_gt_iir; | 328 | gt_iir = new_gt_iir; |
329 | pch_iir = new_pch_iir; | ||
296 | } | 330 | } |
297 | 331 | ||
298 | I915_WRITE(DEIER, de_ier); | 332 | I915_WRITE(DEIER, de_ier); |
@@ -317,19 +351,19 @@ static void i915_error_work_func(struct work_struct *work) | |||
317 | char *reset_event[] = { "RESET=1", NULL }; | 351 | char *reset_event[] = { "RESET=1", NULL }; |
318 | char *reset_done_event[] = { "ERROR=0", NULL }; | 352 | char *reset_done_event[] = { "ERROR=0", NULL }; |
319 | 353 | ||
320 | DRM_DEBUG("generating error event\n"); | 354 | DRM_DEBUG_DRIVER("generating error event\n"); |
321 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); | 355 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
322 | 356 | ||
323 | if (atomic_read(&dev_priv->mm.wedged)) { | 357 | if (atomic_read(&dev_priv->mm.wedged)) { |
324 | if (IS_I965G(dev)) { | 358 | if (IS_I965G(dev)) { |
325 | DRM_DEBUG("resetting chip\n"); | 359 | DRM_DEBUG_DRIVER("resetting chip\n"); |
326 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | 360 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
327 | if (!i965_reset(dev, GDRST_RENDER)) { | 361 | if (!i965_reset(dev, GDRST_RENDER)) { |
328 | atomic_set(&dev_priv->mm.wedged, 0); | 362 | atomic_set(&dev_priv->mm.wedged, 0); |
329 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | 363 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
330 | } | 364 | } |
331 | } else { | 365 | } else { |
332 | printk("reboot required\n"); | 366 | DRM_DEBUG_DRIVER("reboot required\n"); |
333 | } | 367 | } |
334 | } | 368 | } |
335 | } | 369 | } |
@@ -355,7 +389,7 @@ static void i915_capture_error_state(struct drm_device *dev) | |||
355 | 389 | ||
356 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | 390 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
357 | if (!error) { | 391 | if (!error) { |
358 | DRM_DEBUG("out ot memory, not capturing error state\n"); | 392 | DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n"); |
359 | goto out; | 393 | goto out; |
360 | } | 394 | } |
361 | 395 | ||
@@ -512,7 +546,6 @@ static void i915_handle_error(struct drm_device *dev, bool wedged) | |||
512 | /* | 546 | /* |
513 | * Wakeup waiting processes so they don't hang | 547 | * Wakeup waiting processes so they don't hang |
514 | */ | 548 | */ |
515 | printk("i915: Waking up sleeping processes\n"); | ||
516 | DRM_WAKEUP(&dev_priv->irq_queue); | 549 | DRM_WAKEUP(&dev_priv->irq_queue); |
517 | } | 550 | } |
518 | 551 | ||
@@ -535,8 +568,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
535 | 568 | ||
536 | atomic_inc(&dev_priv->irq_received); | 569 | atomic_inc(&dev_priv->irq_received); |
537 | 570 | ||
538 | if (IS_IGDNG(dev)) | 571 | if (IS_IRONLAKE(dev)) |
539 | return igdng_irq_handler(dev); | 572 | return ironlake_irq_handler(dev); |
540 | 573 | ||
541 | iir = I915_READ(IIR); | 574 | iir = I915_READ(IIR); |
542 | 575 | ||
@@ -568,14 +601,14 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
568 | */ | 601 | */ |
569 | if (pipea_stats & 0x8000ffff) { | 602 | if (pipea_stats & 0x8000ffff) { |
570 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) | 603 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
571 | DRM_DEBUG("pipe a underrun\n"); | 604 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
572 | I915_WRITE(PIPEASTAT, pipea_stats); | 605 | I915_WRITE(PIPEASTAT, pipea_stats); |
573 | irq_received = 1; | 606 | irq_received = 1; |
574 | } | 607 | } |
575 | 608 | ||
576 | if (pipeb_stats & 0x8000ffff) { | 609 | if (pipeb_stats & 0x8000ffff) { |
577 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) | 610 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
578 | DRM_DEBUG("pipe b underrun\n"); | 611 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
579 | I915_WRITE(PIPEBSTAT, pipeb_stats); | 612 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
580 | irq_received = 1; | 613 | irq_received = 1; |
581 | } | 614 | } |
@@ -591,7 +624,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
591 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | 624 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
592 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | 625 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
593 | 626 | ||
594 | DRM_DEBUG("hotplug event received, stat 0x%08x\n", | 627 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
595 | hotplug_status); | 628 | hotplug_status); |
596 | if (hotplug_status & dev_priv->hotplug_supported_mask) | 629 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
597 | queue_work(dev_priv->wq, | 630 | queue_work(dev_priv->wq, |
@@ -599,27 +632,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
599 | 632 | ||
600 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | 633 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
601 | I915_READ(PORT_HOTPLUG_STAT); | 634 | I915_READ(PORT_HOTPLUG_STAT); |
602 | |||
603 | /* EOS interrupts occurs */ | ||
604 | if (IS_IGD(dev) && | ||
605 | (hotplug_status & CRT_EOS_INT_STATUS)) { | ||
606 | u32 temp; | ||
607 | |||
608 | DRM_DEBUG("EOS interrupt occurs\n"); | ||
609 | /* status is already cleared */ | ||
610 | temp = I915_READ(ADPA); | ||
611 | temp &= ~ADPA_DAC_ENABLE; | ||
612 | I915_WRITE(ADPA, temp); | ||
613 | |||
614 | temp = I915_READ(PORT_HOTPLUG_EN); | ||
615 | temp &= ~CRT_EOS_INT_EN; | ||
616 | I915_WRITE(PORT_HOTPLUG_EN, temp); | ||
617 | |||
618 | temp = I915_READ(PORT_HOTPLUG_STAT); | ||
619 | if (temp & CRT_EOS_INT_STATUS) | ||
620 | I915_WRITE(PORT_HOTPLUG_STAT, | ||
621 | CRT_EOS_INT_STATUS); | ||
622 | } | ||
623 | } | 635 | } |
624 | 636 | ||
625 | I915_WRITE(IIR, iir); | 637 | I915_WRITE(IIR, iir); |
@@ -641,14 +653,22 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
641 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | 653 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
642 | } | 654 | } |
643 | 655 | ||
656 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) | ||
657 | intel_prepare_page_flip(dev, 0); | ||
658 | |||
659 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) | ||
660 | intel_prepare_page_flip(dev, 1); | ||
661 | |||
644 | if (pipea_stats & vblank_status) { | 662 | if (pipea_stats & vblank_status) { |
645 | vblank++; | 663 | vblank++; |
646 | drm_handle_vblank(dev, 0); | 664 | drm_handle_vblank(dev, 0); |
665 | intel_finish_page_flip(dev, 0); | ||
647 | } | 666 | } |
648 | 667 | ||
649 | if (pipeb_stats & vblank_status) { | 668 | if (pipeb_stats & vblank_status) { |
650 | vblank++; | 669 | vblank++; |
651 | drm_handle_vblank(dev, 1); | 670 | drm_handle_vblank(dev, 1); |
671 | intel_finish_page_flip(dev, 1); | ||
652 | } | 672 | } |
653 | 673 | ||
654 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || | 674 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
@@ -684,7 +704,7 @@ static int i915_emit_irq(struct drm_device * dev) | |||
684 | 704 | ||
685 | i915_kernel_lost_context(dev); | 705 | i915_kernel_lost_context(dev); |
686 | 706 | ||
687 | DRM_DEBUG("\n"); | 707 | DRM_DEBUG_DRIVER("\n"); |
688 | 708 | ||
689 | dev_priv->counter++; | 709 | dev_priv->counter++; |
690 | if (dev_priv->counter > 0x7FFFFFFFUL) | 710 | if (dev_priv->counter > 0x7FFFFFFFUL) |
@@ -709,8 +729,8 @@ void i915_user_irq_get(struct drm_device *dev) | |||
709 | 729 | ||
710 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | 730 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
711 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { | 731 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
712 | if (IS_IGDNG(dev)) | 732 | if (IS_IRONLAKE(dev)) |
713 | igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | 733 | ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
714 | else | 734 | else |
715 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | 735 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
716 | } | 736 | } |
@@ -725,8 +745,8 @@ void i915_user_irq_put(struct drm_device *dev) | |||
725 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | 745 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
726 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); | 746 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
727 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { | 747 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
728 | if (IS_IGDNG(dev)) | 748 | if (IS_IRONLAKE(dev)) |
729 | igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | 749 | ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
730 | else | 750 | else |
731 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | 751 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
732 | } | 752 | } |
@@ -749,7 +769,7 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr) | |||
749 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | 769 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
750 | int ret = 0; | 770 | int ret = 0; |
751 | 771 | ||
752 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, | 772 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
753 | READ_BREADCRUMB(dev_priv)); | 773 | READ_BREADCRUMB(dev_priv)); |
754 | 774 | ||
755 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { | 775 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
@@ -832,7 +852,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe) | |||
832 | if (!(pipeconf & PIPEACONF_ENABLE)) | 852 | if (!(pipeconf & PIPEACONF_ENABLE)) |
833 | return -EINVAL; | 853 | return -EINVAL; |
834 | 854 | ||
835 | if (IS_IGDNG(dev)) | 855 | if (IS_IRONLAKE(dev)) |
836 | return 0; | 856 | return 0; |
837 | 857 | ||
838 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | 858 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
@@ -854,7 +874,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe) | |||
854 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 874 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
855 | unsigned long irqflags; | 875 | unsigned long irqflags; |
856 | 876 | ||
857 | if (IS_IGDNG(dev)) | 877 | if (IS_IRONLAKE(dev)) |
858 | return; | 878 | return; |
859 | 879 | ||
860 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | 880 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
@@ -868,7 +888,7 @@ void i915_enable_interrupt (struct drm_device *dev) | |||
868 | { | 888 | { |
869 | struct drm_i915_private *dev_priv = dev->dev_private; | 889 | struct drm_i915_private *dev_priv = dev->dev_private; |
870 | 890 | ||
871 | if (!IS_IGDNG(dev)) | 891 | if (!IS_IRONLAKE(dev)) |
872 | opregion_enable_asle(dev); | 892 | opregion_enable_asle(dev); |
873 | dev_priv->irq_enabled = 1; | 893 | dev_priv->irq_enabled = 1; |
874 | } | 894 | } |
@@ -976,7 +996,7 @@ void i915_hangcheck_elapsed(unsigned long data) | |||
976 | 996 | ||
977 | /* drm_dma.h hooks | 997 | /* drm_dma.h hooks |
978 | */ | 998 | */ |
979 | static void igdng_irq_preinstall(struct drm_device *dev) | 999 | static void ironlake_irq_preinstall(struct drm_device *dev) |
980 | { | 1000 | { |
981 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1001 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
982 | 1002 | ||
@@ -992,14 +1012,21 @@ static void igdng_irq_preinstall(struct drm_device *dev) | |||
992 | I915_WRITE(GTIMR, 0xffffffff); | 1012 | I915_WRITE(GTIMR, 0xffffffff); |
993 | I915_WRITE(GTIER, 0x0); | 1013 | I915_WRITE(GTIER, 0x0); |
994 | (void) I915_READ(GTIER); | 1014 | (void) I915_READ(GTIER); |
1015 | |||
1016 | /* south display irq */ | ||
1017 | I915_WRITE(SDEIMR, 0xffffffff); | ||
1018 | I915_WRITE(SDEIER, 0x0); | ||
1019 | (void) I915_READ(SDEIER); | ||
995 | } | 1020 | } |
996 | 1021 | ||
997 | static int igdng_irq_postinstall(struct drm_device *dev) | 1022 | static int ironlake_irq_postinstall(struct drm_device *dev) |
998 | { | 1023 | { |
999 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1024 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1000 | /* enable kind of interrupts always enabled */ | 1025 | /* enable kind of interrupts always enabled */ |
1001 | u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */; | 1026 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT; |
1002 | u32 render_mask = GT_USER_INTERRUPT; | 1027 | u32 render_mask = GT_USER_INTERRUPT; |
1028 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | ||
1029 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | ||
1003 | 1030 | ||
1004 | dev_priv->irq_mask_reg = ~display_mask; | 1031 | dev_priv->irq_mask_reg = ~display_mask; |
1005 | dev_priv->de_irq_enable_reg = display_mask; | 1032 | dev_priv->de_irq_enable_reg = display_mask; |
@@ -1019,6 +1046,14 @@ static int igdng_irq_postinstall(struct drm_device *dev) | |||
1019 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | 1046 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
1020 | (void) I915_READ(GTIER); | 1047 | (void) I915_READ(GTIER); |
1021 | 1048 | ||
1049 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; | ||
1050 | dev_priv->pch_irq_enable_reg = hotplug_mask; | ||
1051 | |||
1052 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | ||
1053 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | ||
1054 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | ||
1055 | (void) I915_READ(SDEIER); | ||
1056 | |||
1022 | return 0; | 1057 | return 0; |
1023 | } | 1058 | } |
1024 | 1059 | ||
@@ -1031,8 +1066,8 @@ void i915_driver_irq_preinstall(struct drm_device * dev) | |||
1031 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | 1066 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
1032 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); | 1067 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
1033 | 1068 | ||
1034 | if (IS_IGDNG(dev)) { | 1069 | if (IS_IRONLAKE(dev)) { |
1035 | igdng_irq_preinstall(dev); | 1070 | ironlake_irq_preinstall(dev); |
1036 | return; | 1071 | return; |
1037 | } | 1072 | } |
1038 | 1073 | ||
@@ -1059,8 +1094,8 @@ int i915_driver_irq_postinstall(struct drm_device *dev) | |||
1059 | 1094 | ||
1060 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | 1095 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
1061 | 1096 | ||
1062 | if (IS_IGDNG(dev)) | 1097 | if (IS_IRONLAKE(dev)) |
1063 | return igdng_irq_postinstall(dev); | 1098 | return ironlake_irq_postinstall(dev); |
1064 | 1099 | ||
1065 | /* Unmask the interrupts that we always want on. */ | 1100 | /* Unmask the interrupts that we always want on. */ |
1066 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | 1101 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; |
@@ -1120,7 +1155,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev) | |||
1120 | return 0; | 1155 | return 0; |
1121 | } | 1156 | } |
1122 | 1157 | ||
1123 | static void igdng_irq_uninstall(struct drm_device *dev) | 1158 | static void ironlake_irq_uninstall(struct drm_device *dev) |
1124 | { | 1159 | { |
1125 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1160 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1126 | I915_WRITE(HWSTAM, 0xffffffff); | 1161 | I915_WRITE(HWSTAM, 0xffffffff); |
@@ -1143,8 +1178,8 @@ void i915_driver_irq_uninstall(struct drm_device * dev) | |||
1143 | 1178 | ||
1144 | dev_priv->vblank_pipe = 0; | 1179 | dev_priv->vblank_pipe = 0; |
1145 | 1180 | ||
1146 | if (IS_IGDNG(dev)) { | 1181 | if (IS_IRONLAKE(dev)) { |
1147 | igdng_irq_uninstall(dev); | 1182 | ironlake_irq_uninstall(dev); |
1148 | return; | 1183 | return; |
1149 | } | 1184 | } |
1150 | 1185 | ||