diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 370 |
1 files changed, 239 insertions, 131 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index fe843389c7b4..2cd97d1cc920 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -287,6 +287,10 @@ static void i915_hotplug_work_func(struct work_struct *work) | |||
287 | struct drm_mode_config *mode_config = &dev->mode_config; | 287 | struct drm_mode_config *mode_config = &dev->mode_config; |
288 | struct intel_encoder *encoder; | 288 | struct intel_encoder *encoder; |
289 | 289 | ||
290 | /* HPD irq before everything is fully set up. */ | ||
291 | if (!dev_priv->enable_hotplug_processing) | ||
292 | return; | ||
293 | |||
290 | mutex_lock(&mode_config->mutex); | 294 | mutex_lock(&mode_config->mutex); |
291 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | 295 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
292 | 296 | ||
@@ -300,9 +304,6 @@ static void i915_hotplug_work_func(struct work_struct *work) | |||
300 | drm_helper_hpd_irq_event(dev); | 304 | drm_helper_hpd_irq_event(dev); |
301 | } | 305 | } |
302 | 306 | ||
303 | /* defined intel_pm.c */ | ||
304 | extern spinlock_t mchdev_lock; | ||
305 | |||
306 | static void ironlake_handle_rps_change(struct drm_device *dev) | 307 | static void ironlake_handle_rps_change(struct drm_device *dev) |
307 | { | 308 | { |
308 | drm_i915_private_t *dev_priv = dev->dev_private; | 309 | drm_i915_private_t *dev_priv = dev->dev_private; |
@@ -355,8 +356,8 @@ static void notify_ring(struct drm_device *dev, | |||
355 | 356 | ||
356 | wake_up_all(&ring->irq_queue); | 357 | wake_up_all(&ring->irq_queue); |
357 | if (i915_enable_hangcheck) { | 358 | if (i915_enable_hangcheck) { |
358 | dev_priv->hangcheck_count = 0; | 359 | dev_priv->gpu_error.hangcheck_count = 0; |
359 | mod_timer(&dev_priv->hangcheck_timer, | 360 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
360 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | 361 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
361 | } | 362 | } |
362 | } | 363 | } |
@@ -524,6 +525,20 @@ static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, | |||
524 | queue_work(dev_priv->wq, &dev_priv->rps.work); | 525 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
525 | } | 526 | } |
526 | 527 | ||
528 | static void gmbus_irq_handler(struct drm_device *dev) | ||
529 | { | ||
530 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
531 | |||
532 | wake_up_all(&dev_priv->gmbus_wait_queue); | ||
533 | } | ||
534 | |||
535 | static void dp_aux_irq_handler(struct drm_device *dev) | ||
536 | { | ||
537 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
538 | |||
539 | wake_up_all(&dev_priv->gmbus_wait_queue); | ||
540 | } | ||
541 | |||
527 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) | 542 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
528 | { | 543 | { |
529 | struct drm_device *dev = (struct drm_device *) arg; | 544 | struct drm_device *dev = (struct drm_device *) arg; |
@@ -533,7 +548,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) | |||
533 | unsigned long irqflags; | 548 | unsigned long irqflags; |
534 | int pipe; | 549 | int pipe; |
535 | u32 pipe_stats[I915_MAX_PIPES]; | 550 | u32 pipe_stats[I915_MAX_PIPES]; |
536 | bool blc_event; | ||
537 | 551 | ||
538 | atomic_inc(&dev_priv->irq_received); | 552 | atomic_inc(&dev_priv->irq_received); |
539 | 553 | ||
@@ -590,8 +604,8 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) | |||
590 | I915_READ(PORT_HOTPLUG_STAT); | 604 | I915_READ(PORT_HOTPLUG_STAT); |
591 | } | 605 | } |
592 | 606 | ||
593 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | 607 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
594 | blc_event = true; | 608 | gmbus_irq_handler(dev); |
595 | 609 | ||
596 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) | 610 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) |
597 | gen6_queue_rps_work(dev_priv, pm_iir); | 611 | gen6_queue_rps_work(dev_priv, pm_iir); |
@@ -618,8 +632,11 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) | |||
618 | (pch_iir & SDE_AUDIO_POWER_MASK) >> | 632 | (pch_iir & SDE_AUDIO_POWER_MASK) >> |
619 | SDE_AUDIO_POWER_SHIFT); | 633 | SDE_AUDIO_POWER_SHIFT); |
620 | 634 | ||
635 | if (pch_iir & SDE_AUX_MASK) | ||
636 | dp_aux_irq_handler(dev); | ||
637 | |||
621 | if (pch_iir & SDE_GMBUS) | 638 | if (pch_iir & SDE_GMBUS) |
622 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | 639 | gmbus_irq_handler(dev); |
623 | 640 | ||
624 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | 641 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
625 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | 642 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
@@ -662,10 +679,10 @@ static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) | |||
662 | SDE_AUDIO_POWER_SHIFT_CPT); | 679 | SDE_AUDIO_POWER_SHIFT_CPT); |
663 | 680 | ||
664 | if (pch_iir & SDE_AUX_MASK_CPT) | 681 | if (pch_iir & SDE_AUX_MASK_CPT) |
665 | DRM_DEBUG_DRIVER("AUX channel interrupt\n"); | 682 | dp_aux_irq_handler(dev); |
666 | 683 | ||
667 | if (pch_iir & SDE_GMBUS_CPT) | 684 | if (pch_iir & SDE_GMBUS_CPT) |
668 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | 685 | gmbus_irq_handler(dev); |
669 | 686 | ||
670 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | 687 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) |
671 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | 688 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); |
@@ -703,6 +720,9 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg) | |||
703 | 720 | ||
704 | de_iir = I915_READ(DEIIR); | 721 | de_iir = I915_READ(DEIIR); |
705 | if (de_iir) { | 722 | if (de_iir) { |
723 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | ||
724 | dp_aux_irq_handler(dev); | ||
725 | |||
706 | if (de_iir & DE_GSE_IVB) | 726 | if (de_iir & DE_GSE_IVB) |
707 | intel_opregion_gse_intr(dev); | 727 | intel_opregion_gse_intr(dev); |
708 | 728 | ||
@@ -758,7 +778,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) | |||
758 | struct drm_device *dev = (struct drm_device *) arg; | 778 | struct drm_device *dev = (struct drm_device *) arg; |
759 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 779 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
760 | int ret = IRQ_NONE; | 780 | int ret = IRQ_NONE; |
761 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; | 781 | u32 de_iir, gt_iir, de_ier, pm_iir; |
762 | 782 | ||
763 | atomic_inc(&dev_priv->irq_received); | 783 | atomic_inc(&dev_priv->irq_received); |
764 | 784 | ||
@@ -769,11 +789,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) | |||
769 | 789 | ||
770 | de_iir = I915_READ(DEIIR); | 790 | de_iir = I915_READ(DEIIR); |
771 | gt_iir = I915_READ(GTIIR); | 791 | gt_iir = I915_READ(GTIIR); |
772 | pch_iir = I915_READ(SDEIIR); | ||
773 | pm_iir = I915_READ(GEN6_PMIIR); | 792 | pm_iir = I915_READ(GEN6_PMIIR); |
774 | 793 | ||
775 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && | 794 | if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0)) |
776 | (!IS_GEN6(dev) || pm_iir == 0)) | ||
777 | goto done; | 795 | goto done; |
778 | 796 | ||
779 | ret = IRQ_HANDLED; | 797 | ret = IRQ_HANDLED; |
@@ -783,6 +801,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) | |||
783 | else | 801 | else |
784 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | 802 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
785 | 803 | ||
804 | if (de_iir & DE_AUX_CHANNEL_A) | ||
805 | dp_aux_irq_handler(dev); | ||
806 | |||
786 | if (de_iir & DE_GSE) | 807 | if (de_iir & DE_GSE) |
787 | intel_opregion_gse_intr(dev); | 808 | intel_opregion_gse_intr(dev); |
788 | 809 | ||
@@ -804,10 +825,15 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) | |||
804 | 825 | ||
805 | /* check event from PCH */ | 826 | /* check event from PCH */ |
806 | if (de_iir & DE_PCH_EVENT) { | 827 | if (de_iir & DE_PCH_EVENT) { |
828 | u32 pch_iir = I915_READ(SDEIIR); | ||
829 | |||
807 | if (HAS_PCH_CPT(dev)) | 830 | if (HAS_PCH_CPT(dev)) |
808 | cpt_irq_handler(dev, pch_iir); | 831 | cpt_irq_handler(dev, pch_iir); |
809 | else | 832 | else |
810 | ibx_irq_handler(dev, pch_iir); | 833 | ibx_irq_handler(dev, pch_iir); |
834 | |||
835 | /* should clear PCH hotplug event before clear CPU irq */ | ||
836 | I915_WRITE(SDEIIR, pch_iir); | ||
811 | } | 837 | } |
812 | 838 | ||
813 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | 839 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
@@ -816,8 +842,6 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) | |||
816 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) | 842 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) |
817 | gen6_queue_rps_work(dev_priv, pm_iir); | 843 | gen6_queue_rps_work(dev_priv, pm_iir); |
818 | 844 | ||
819 | /* should clear PCH hotplug event before clear CPU irq */ | ||
820 | I915_WRITE(SDEIIR, pch_iir); | ||
821 | I915_WRITE(GTIIR, gt_iir); | 845 | I915_WRITE(GTIIR, gt_iir); |
822 | I915_WRITE(DEIIR, de_iir); | 846 | I915_WRITE(DEIIR, de_iir); |
823 | I915_WRITE(GEN6_PMIIR, pm_iir); | 847 | I915_WRITE(GEN6_PMIIR, pm_iir); |
@@ -838,23 +862,60 @@ done: | |||
838 | */ | 862 | */ |
839 | static void i915_error_work_func(struct work_struct *work) | 863 | static void i915_error_work_func(struct work_struct *work) |
840 | { | 864 | { |
841 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | 865 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
842 | error_work); | 866 | work); |
867 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, | ||
868 | gpu_error); | ||
843 | struct drm_device *dev = dev_priv->dev; | 869 | struct drm_device *dev = dev_priv->dev; |
870 | struct intel_ring_buffer *ring; | ||
844 | char *error_event[] = { "ERROR=1", NULL }; | 871 | char *error_event[] = { "ERROR=1", NULL }; |
845 | char *reset_event[] = { "RESET=1", NULL }; | 872 | char *reset_event[] = { "RESET=1", NULL }; |
846 | char *reset_done_event[] = { "ERROR=0", NULL }; | 873 | char *reset_done_event[] = { "ERROR=0", NULL }; |
874 | int i, ret; | ||
847 | 875 | ||
848 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); | 876 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
849 | 877 | ||
850 | if (atomic_read(&dev_priv->mm.wedged)) { | 878 | /* |
879 | * Note that there's only one work item which does gpu resets, so we | ||
880 | * need not worry about concurrent gpu resets potentially incrementing | ||
881 | * error->reset_counter twice. We only need to take care of another | ||
882 | * racing irq/hangcheck declaring the gpu dead for a second time. A | ||
883 | * quick check for that is good enough: schedule_work ensures the | ||
884 | * correct ordering between hang detection and this work item, and since | ||
885 | * the reset in-progress bit is only ever set by code outside of this | ||
886 | * work we don't need to worry about any other races. | ||
887 | */ | ||
888 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | ||
851 | DRM_DEBUG_DRIVER("resetting chip\n"); | 889 | DRM_DEBUG_DRIVER("resetting chip\n"); |
852 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | 890 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, |
853 | if (!i915_reset(dev)) { | 891 | reset_event); |
854 | atomic_set(&dev_priv->mm.wedged, 0); | 892 | |
855 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | 893 | ret = i915_reset(dev); |
894 | |||
895 | if (ret == 0) { | ||
896 | /* | ||
897 | * After all the gem state is reset, increment the reset | ||
898 | * counter and wake up everyone waiting for the reset to | ||
899 | * complete. | ||
900 | * | ||
901 | * Since unlock operations are a one-sided barrier only, | ||
902 | * we need to insert a barrier here to order any seqno | ||
903 | * updates before | ||
904 | * the counter increment. | ||
905 | */ | ||
906 | smp_mb__before_atomic_inc(); | ||
907 | atomic_inc(&dev_priv->gpu_error.reset_counter); | ||
908 | |||
909 | kobject_uevent_env(&dev->primary->kdev.kobj, | ||
910 | KOBJ_CHANGE, reset_done_event); | ||
911 | } else { | ||
912 | atomic_set(&error->reset_counter, I915_WEDGED); | ||
856 | } | 913 | } |
857 | complete_all(&dev_priv->error_completion); | 914 | |
915 | for_each_ring(ring, dev_priv, i) | ||
916 | wake_up_all(&ring->irq_queue); | ||
917 | |||
918 | wake_up_all(&dev_priv->gpu_error.reset_queue); | ||
858 | } | 919 | } |
859 | } | 920 | } |
860 | 921 | ||
@@ -915,7 +976,7 @@ i915_error_object_create(struct drm_i915_private *dev_priv, | |||
915 | goto unwind; | 976 | goto unwind; |
916 | 977 | ||
917 | local_irq_save(flags); | 978 | local_irq_save(flags); |
918 | if (reloc_offset < dev_priv->mm.gtt_mappable_end && | 979 | if (reloc_offset < dev_priv->gtt.mappable_end && |
919 | src->has_global_gtt_mapping) { | 980 | src->has_global_gtt_mapping) { |
920 | void __iomem *s; | 981 | void __iomem *s; |
921 | 982 | ||
@@ -924,10 +985,18 @@ i915_error_object_create(struct drm_i915_private *dev_priv, | |||
924 | * captures what the GPU read. | 985 | * captures what the GPU read. |
925 | */ | 986 | */ |
926 | 987 | ||
927 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | 988 | s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
928 | reloc_offset); | 989 | reloc_offset); |
929 | memcpy_fromio(d, s, PAGE_SIZE); | 990 | memcpy_fromio(d, s, PAGE_SIZE); |
930 | io_mapping_unmap_atomic(s); | 991 | io_mapping_unmap_atomic(s); |
992 | } else if (src->stolen) { | ||
993 | unsigned long offset; | ||
994 | |||
995 | offset = dev_priv->mm.stolen_base; | ||
996 | offset += src->stolen->start; | ||
997 | offset += i << PAGE_SHIFT; | ||
998 | |||
999 | memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); | ||
931 | } else { | 1000 | } else { |
932 | struct page *page; | 1001 | struct page *page; |
933 | void *s; | 1002 | void *s; |
@@ -1074,6 +1143,8 @@ static void i915_gem_record_fences(struct drm_device *dev, | |||
1074 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | 1143 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); |
1075 | break; | 1144 | break; |
1076 | 1145 | ||
1146 | default: | ||
1147 | BUG(); | ||
1077 | } | 1148 | } |
1078 | } | 1149 | } |
1079 | 1150 | ||
@@ -1222,9 +1293,9 @@ static void i915_capture_error_state(struct drm_device *dev) | |||
1222 | unsigned long flags; | 1293 | unsigned long flags; |
1223 | int i, pipe; | 1294 | int i, pipe; |
1224 | 1295 | ||
1225 | spin_lock_irqsave(&dev_priv->error_lock, flags); | 1296 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1226 | error = dev_priv->first_error; | 1297 | error = dev_priv->gpu_error.first_error; |
1227 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | 1298 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); |
1228 | if (error) | 1299 | if (error) |
1229 | return; | 1300 | return; |
1230 | 1301 | ||
@@ -1235,7 +1306,8 @@ static void i915_capture_error_state(struct drm_device *dev) | |||
1235 | return; | 1306 | return; |
1236 | } | 1307 | } |
1237 | 1308 | ||
1238 | DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", | 1309 | DRM_INFO("capturing error event; look for more information in" |
1310 | "/sys/kernel/debug/dri/%d/i915_error_state\n", | ||
1239 | dev->primary->index); | 1311 | dev->primary->index); |
1240 | 1312 | ||
1241 | kref_init(&error->ref); | 1313 | kref_init(&error->ref); |
@@ -1318,12 +1390,12 @@ static void i915_capture_error_state(struct drm_device *dev) | |||
1318 | error->overlay = intel_overlay_capture_error_state(dev); | 1390 | error->overlay = intel_overlay_capture_error_state(dev); |
1319 | error->display = intel_display_capture_error_state(dev); | 1391 | error->display = intel_display_capture_error_state(dev); |
1320 | 1392 | ||
1321 | spin_lock_irqsave(&dev_priv->error_lock, flags); | 1393 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1322 | if (dev_priv->first_error == NULL) { | 1394 | if (dev_priv->gpu_error.first_error == NULL) { |
1323 | dev_priv->first_error = error; | 1395 | dev_priv->gpu_error.first_error = error; |
1324 | error = NULL; | 1396 | error = NULL; |
1325 | } | 1397 | } |
1326 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | 1398 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); |
1327 | 1399 | ||
1328 | if (error) | 1400 | if (error) |
1329 | i915_error_state_free(&error->ref); | 1401 | i915_error_state_free(&error->ref); |
@@ -1335,10 +1407,10 @@ void i915_destroy_error_state(struct drm_device *dev) | |||
1335 | struct drm_i915_error_state *error; | 1407 | struct drm_i915_error_state *error; |
1336 | unsigned long flags; | 1408 | unsigned long flags; |
1337 | 1409 | ||
1338 | spin_lock_irqsave(&dev_priv->error_lock, flags); | 1410 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1339 | error = dev_priv->first_error; | 1411 | error = dev_priv->gpu_error.first_error; |
1340 | dev_priv->first_error = NULL; | 1412 | dev_priv->gpu_error.first_error = NULL; |
1341 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | 1413 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); |
1342 | 1414 | ||
1343 | if (error) | 1415 | if (error) |
1344 | kref_put(&error->ref, i915_error_state_free); | 1416 | kref_put(&error->ref, i915_error_state_free); |
@@ -1459,17 +1531,18 @@ void i915_handle_error(struct drm_device *dev, bool wedged) | |||
1459 | i915_report_and_clear_eir(dev); | 1531 | i915_report_and_clear_eir(dev); |
1460 | 1532 | ||
1461 | if (wedged) { | 1533 | if (wedged) { |
1462 | INIT_COMPLETION(dev_priv->error_completion); | 1534 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
1463 | atomic_set(&dev_priv->mm.wedged, 1); | 1535 | &dev_priv->gpu_error.reset_counter); |
1464 | 1536 | ||
1465 | /* | 1537 | /* |
1466 | * Wakeup waiting processes so they don't hang | 1538 | * Wakeup waiting processes so that the reset work item |
1539 | * doesn't deadlock trying to grab various locks. | ||
1467 | */ | 1540 | */ |
1468 | for_each_ring(ring, dev_priv, i) | 1541 | for_each_ring(ring, dev_priv, i) |
1469 | wake_up_all(&ring->irq_queue); | 1542 | wake_up_all(&ring->irq_queue); |
1470 | } | 1543 | } |
1471 | 1544 | ||
1472 | queue_work(dev_priv->wq, &dev_priv->error_work); | 1545 | queue_work(dev_priv->wq, &dev_priv->gpu_error.work); |
1473 | } | 1546 | } |
1474 | 1547 | ||
1475 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) | 1548 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
@@ -1700,7 +1773,7 @@ static bool i915_hangcheck_hung(struct drm_device *dev) | |||
1700 | { | 1773 | { |
1701 | drm_i915_private_t *dev_priv = dev->dev_private; | 1774 | drm_i915_private_t *dev_priv = dev->dev_private; |
1702 | 1775 | ||
1703 | if (dev_priv->hangcheck_count++ > 1) { | 1776 | if (dev_priv->gpu_error.hangcheck_count++ > 1) { |
1704 | bool hung = true; | 1777 | bool hung = true; |
1705 | 1778 | ||
1706 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | 1779 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
@@ -1759,25 +1832,29 @@ void i915_hangcheck_elapsed(unsigned long data) | |||
1759 | goto repeat; | 1832 | goto repeat; |
1760 | } | 1833 | } |
1761 | 1834 | ||
1762 | dev_priv->hangcheck_count = 0; | 1835 | dev_priv->gpu_error.hangcheck_count = 0; |
1763 | return; | 1836 | return; |
1764 | } | 1837 | } |
1765 | 1838 | ||
1766 | i915_get_extra_instdone(dev, instdone); | 1839 | i915_get_extra_instdone(dev, instdone); |
1767 | if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 && | 1840 | if (memcmp(dev_priv->gpu_error.last_acthd, acthd, |
1768 | memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) { | 1841 | sizeof(acthd)) == 0 && |
1842 | memcmp(dev_priv->gpu_error.prev_instdone, instdone, | ||
1843 | sizeof(instdone)) == 0) { | ||
1769 | if (i915_hangcheck_hung(dev)) | 1844 | if (i915_hangcheck_hung(dev)) |
1770 | return; | 1845 | return; |
1771 | } else { | 1846 | } else { |
1772 | dev_priv->hangcheck_count = 0; | 1847 | dev_priv->gpu_error.hangcheck_count = 0; |
1773 | 1848 | ||
1774 | memcpy(dev_priv->last_acthd, acthd, sizeof(acthd)); | 1849 | memcpy(dev_priv->gpu_error.last_acthd, acthd, |
1775 | memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone)); | 1850 | sizeof(acthd)); |
1851 | memcpy(dev_priv->gpu_error.prev_instdone, instdone, | ||
1852 | sizeof(instdone)); | ||
1776 | } | 1853 | } |
1777 | 1854 | ||
1778 | repeat: | 1855 | repeat: |
1779 | /* Reset timer case chip hangs without another request being added */ | 1856 | /* Reset timer case chip hangs without another request being added */ |
1780 | mod_timer(&dev_priv->hangcheck_timer, | 1857 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
1781 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | 1858 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
1782 | } | 1859 | } |
1783 | 1860 | ||
@@ -1847,7 +1924,7 @@ static void valleyview_irq_preinstall(struct drm_device *dev) | |||
1847 | * This register is the same on all known PCH chips. | 1924 | * This register is the same on all known PCH chips. |
1848 | */ | 1925 | */ |
1849 | 1926 | ||
1850 | static void ironlake_enable_pch_hotplug(struct drm_device *dev) | 1927 | static void ibx_enable_hotplug(struct drm_device *dev) |
1851 | { | 1928 | { |
1852 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1929 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1853 | u32 hotplug; | 1930 | u32 hotplug; |
@@ -1860,14 +1937,36 @@ static void ironlake_enable_pch_hotplug(struct drm_device *dev) | |||
1860 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | 1937 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
1861 | } | 1938 | } |
1862 | 1939 | ||
1940 | static void ibx_irq_postinstall(struct drm_device *dev) | ||
1941 | { | ||
1942 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
1943 | u32 mask; | ||
1944 | |||
1945 | if (HAS_PCH_IBX(dev)) | ||
1946 | mask = SDE_HOTPLUG_MASK | | ||
1947 | SDE_GMBUS | | ||
1948 | SDE_AUX_MASK; | ||
1949 | else | ||
1950 | mask = SDE_HOTPLUG_MASK_CPT | | ||
1951 | SDE_GMBUS_CPT | | ||
1952 | SDE_AUX_MASK_CPT; | ||
1953 | |||
1954 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | ||
1955 | I915_WRITE(SDEIMR, ~mask); | ||
1956 | I915_WRITE(SDEIER, mask); | ||
1957 | POSTING_READ(SDEIER); | ||
1958 | |||
1959 | ibx_enable_hotplug(dev); | ||
1960 | } | ||
1961 | |||
1863 | static int ironlake_irq_postinstall(struct drm_device *dev) | 1962 | static int ironlake_irq_postinstall(struct drm_device *dev) |
1864 | { | 1963 | { |
1865 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1964 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1866 | /* enable kind of interrupts always enabled */ | 1965 | /* enable kind of interrupts always enabled */ |
1867 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | 1966 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1868 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | 1967 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
1968 | DE_AUX_CHANNEL_A; | ||
1869 | u32 render_irqs; | 1969 | u32 render_irqs; |
1870 | u32 hotplug_mask; | ||
1871 | 1970 | ||
1872 | dev_priv->irq_mask = ~display_mask; | 1971 | dev_priv->irq_mask = ~display_mask; |
1873 | 1972 | ||
@@ -1895,27 +1994,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) | |||
1895 | I915_WRITE(GTIER, render_irqs); | 1994 | I915_WRITE(GTIER, render_irqs); |
1896 | POSTING_READ(GTIER); | 1995 | POSTING_READ(GTIER); |
1897 | 1996 | ||
1898 | if (HAS_PCH_CPT(dev)) { | 1997 | ibx_irq_postinstall(dev); |
1899 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | | ||
1900 | SDE_PORTB_HOTPLUG_CPT | | ||
1901 | SDE_PORTC_HOTPLUG_CPT | | ||
1902 | SDE_PORTD_HOTPLUG_CPT); | ||
1903 | } else { | ||
1904 | hotplug_mask = (SDE_CRT_HOTPLUG | | ||
1905 | SDE_PORTB_HOTPLUG | | ||
1906 | SDE_PORTC_HOTPLUG | | ||
1907 | SDE_PORTD_HOTPLUG | | ||
1908 | SDE_AUX_MASK); | ||
1909 | } | ||
1910 | |||
1911 | dev_priv->pch_irq_mask = ~hotplug_mask; | ||
1912 | |||
1913 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | ||
1914 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); | ||
1915 | I915_WRITE(SDEIER, hotplug_mask); | ||
1916 | POSTING_READ(SDEIER); | ||
1917 | |||
1918 | ironlake_enable_pch_hotplug(dev); | ||
1919 | 1998 | ||
1920 | if (IS_IRONLAKE_M(dev)) { | 1999 | if (IS_IRONLAKE_M(dev)) { |
1921 | /* Clear & enable PCU event interrupts */ | 2000 | /* Clear & enable PCU event interrupts */ |
@@ -1935,9 +2014,9 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) | |||
1935 | DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | | 2014 | DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | |
1936 | DE_PLANEC_FLIP_DONE_IVB | | 2015 | DE_PLANEC_FLIP_DONE_IVB | |
1937 | DE_PLANEB_FLIP_DONE_IVB | | 2016 | DE_PLANEB_FLIP_DONE_IVB | |
1938 | DE_PLANEA_FLIP_DONE_IVB; | 2017 | DE_PLANEA_FLIP_DONE_IVB | |
2018 | DE_AUX_CHANNEL_A_IVB; | ||
1939 | u32 render_irqs; | 2019 | u32 render_irqs; |
1940 | u32 hotplug_mask; | ||
1941 | 2020 | ||
1942 | dev_priv->irq_mask = ~display_mask; | 2021 | dev_priv->irq_mask = ~display_mask; |
1943 | 2022 | ||
@@ -1961,18 +2040,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) | |||
1961 | I915_WRITE(GTIER, render_irqs); | 2040 | I915_WRITE(GTIER, render_irqs); |
1962 | POSTING_READ(GTIER); | 2041 | POSTING_READ(GTIER); |
1963 | 2042 | ||
1964 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | | 2043 | ibx_irq_postinstall(dev); |
1965 | SDE_PORTB_HOTPLUG_CPT | | ||
1966 | SDE_PORTC_HOTPLUG_CPT | | ||
1967 | SDE_PORTD_HOTPLUG_CPT); | ||
1968 | dev_priv->pch_irq_mask = ~hotplug_mask; | ||
1969 | |||
1970 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | ||
1971 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); | ||
1972 | I915_WRITE(SDEIER, hotplug_mask); | ||
1973 | POSTING_READ(SDEIER); | ||
1974 | |||
1975 | ironlake_enable_pch_hotplug(dev); | ||
1976 | 2044 | ||
1977 | return 0; | 2045 | return 0; |
1978 | } | 2046 | } |
@@ -1981,7 +2049,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev) | |||
1981 | { | 2049 | { |
1982 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 2050 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1983 | u32 enable_mask; | 2051 | u32 enable_mask; |
1984 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | ||
1985 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; | 2052 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; |
1986 | u32 render_irqs; | 2053 | u32 render_irqs; |
1987 | u16 msid; | 2054 | u16 msid; |
@@ -2010,6 +2077,9 @@ static int valleyview_irq_postinstall(struct drm_device *dev) | |||
2010 | msid |= (1<<14); | 2077 | msid |= (1<<14); |
2011 | pci_write_config_word(dev_priv->dev->pdev, 0x98, msid); | 2078 | pci_write_config_word(dev_priv->dev->pdev, 0x98, msid); |
2012 | 2079 | ||
2080 | I915_WRITE(PORT_HOTPLUG_EN, 0); | ||
2081 | POSTING_READ(PORT_HOTPLUG_EN); | ||
2082 | |||
2013 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | 2083 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
2014 | I915_WRITE(VLV_IER, enable_mask); | 2084 | I915_WRITE(VLV_IER, enable_mask); |
2015 | I915_WRITE(VLV_IIR, 0xffffffff); | 2085 | I915_WRITE(VLV_IIR, 0xffffffff); |
@@ -2018,6 +2088,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev) | |||
2018 | POSTING_READ(VLV_IER); | 2088 | POSTING_READ(VLV_IER); |
2019 | 2089 | ||
2020 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); | 2090 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); |
2091 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); | ||
2021 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); | 2092 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); |
2022 | 2093 | ||
2023 | I915_WRITE(VLV_IIR, 0xffffffff); | 2094 | I915_WRITE(VLV_IIR, 0xffffffff); |
@@ -2038,13 +2109,22 @@ static int valleyview_irq_postinstall(struct drm_device *dev) | |||
2038 | #endif | 2109 | #endif |
2039 | 2110 | ||
2040 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | 2111 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
2112 | |||
2113 | return 0; | ||
2114 | } | ||
2115 | |||
2116 | static void valleyview_hpd_irq_setup(struct drm_device *dev) | ||
2117 | { | ||
2118 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
2119 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | ||
2120 | |||
2041 | /* Note HDMI and DP share bits */ | 2121 | /* Note HDMI and DP share bits */ |
2042 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | 2122 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2043 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | 2123 | hotplug_en |= PORTB_HOTPLUG_INT_EN; |
2044 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | 2124 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) |
2045 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | 2125 | hotplug_en |= PORTC_HOTPLUG_INT_EN; |
2046 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | 2126 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) |
2047 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | 2127 | hotplug_en |= PORTD_HOTPLUG_INT_EN; |
2048 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) | 2128 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) |
2049 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | 2129 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
2050 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) | 2130 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) |
@@ -2055,8 +2135,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev) | |||
2055 | } | 2135 | } |
2056 | 2136 | ||
2057 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | 2137 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
2058 | |||
2059 | return 0; | ||
2060 | } | 2138 | } |
2061 | 2139 | ||
2062 | static void valleyview_irq_uninstall(struct drm_device *dev) | 2140 | static void valleyview_irq_uninstall(struct drm_device *dev) |
@@ -2286,6 +2364,9 @@ static int i915_irq_postinstall(struct drm_device *dev) | |||
2286 | I915_USER_INTERRUPT; | 2364 | I915_USER_INTERRUPT; |
2287 | 2365 | ||
2288 | if (I915_HAS_HOTPLUG(dev)) { | 2366 | if (I915_HAS_HOTPLUG(dev)) { |
2367 | I915_WRITE(PORT_HOTPLUG_EN, 0); | ||
2368 | POSTING_READ(PORT_HOTPLUG_EN); | ||
2369 | |||
2289 | /* Enable in IER... */ | 2370 | /* Enable in IER... */ |
2290 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | 2371 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
2291 | /* and unmask in IMR */ | 2372 | /* and unmask in IMR */ |
@@ -2296,15 +2377,25 @@ static int i915_irq_postinstall(struct drm_device *dev) | |||
2296 | I915_WRITE(IER, enable_mask); | 2377 | I915_WRITE(IER, enable_mask); |
2297 | POSTING_READ(IER); | 2378 | POSTING_READ(IER); |
2298 | 2379 | ||
2380 | intel_opregion_enable_asle(dev); | ||
2381 | |||
2382 | return 0; | ||
2383 | } | ||
2384 | |||
2385 | static void i915_hpd_irq_setup(struct drm_device *dev) | ||
2386 | { | ||
2387 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
2388 | u32 hotplug_en; | ||
2389 | |||
2299 | if (I915_HAS_HOTPLUG(dev)) { | 2390 | if (I915_HAS_HOTPLUG(dev)) { |
2300 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | 2391 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
2301 | 2392 | ||
2302 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | 2393 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2303 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | 2394 | hotplug_en |= PORTB_HOTPLUG_INT_EN; |
2304 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | 2395 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) |
2305 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | 2396 | hotplug_en |= PORTC_HOTPLUG_INT_EN; |
2306 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | 2397 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) |
2307 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | 2398 | hotplug_en |= PORTD_HOTPLUG_INT_EN; |
2308 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) | 2399 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) |
2309 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | 2400 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
2310 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) | 2401 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) |
@@ -2318,10 +2409,6 @@ static int i915_irq_postinstall(struct drm_device *dev) | |||
2318 | 2409 | ||
2319 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | 2410 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
2320 | } | 2411 | } |
2321 | |||
2322 | intel_opregion_enable_asle(dev); | ||
2323 | |||
2324 | return 0; | ||
2325 | } | 2412 | } |
2326 | 2413 | ||
2327 | static irqreturn_t i915_irq_handler(int irq, void *arg) | 2414 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
@@ -2481,7 +2568,6 @@ static void i965_irq_preinstall(struct drm_device * dev) | |||
2481 | static int i965_irq_postinstall(struct drm_device *dev) | 2568 | static int i965_irq_postinstall(struct drm_device *dev) |
2482 | { | 2569 | { |
2483 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 2570 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
2484 | u32 hotplug_en; | ||
2485 | u32 enable_mask; | 2571 | u32 enable_mask; |
2486 | u32 error_mask; | 2572 | u32 error_mask; |
2487 | 2573 | ||
@@ -2502,6 +2588,7 @@ static int i965_irq_postinstall(struct drm_device *dev) | |||
2502 | 2588 | ||
2503 | dev_priv->pipestat[0] = 0; | 2589 | dev_priv->pipestat[0] = 0; |
2504 | dev_priv->pipestat[1] = 0; | 2590 | dev_priv->pipestat[1] = 0; |
2591 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); | ||
2505 | 2592 | ||
2506 | /* | 2593 | /* |
2507 | * Enable some error detection, note the instruction error mask | 2594 | * Enable some error detection, note the instruction error mask |
@@ -2522,14 +2609,27 @@ static int i965_irq_postinstall(struct drm_device *dev) | |||
2522 | I915_WRITE(IER, enable_mask); | 2609 | I915_WRITE(IER, enable_mask); |
2523 | POSTING_READ(IER); | 2610 | POSTING_READ(IER); |
2524 | 2611 | ||
2612 | I915_WRITE(PORT_HOTPLUG_EN, 0); | ||
2613 | POSTING_READ(PORT_HOTPLUG_EN); | ||
2614 | |||
2615 | intel_opregion_enable_asle(dev); | ||
2616 | |||
2617 | return 0; | ||
2618 | } | ||
2619 | |||
2620 | static void i965_hpd_irq_setup(struct drm_device *dev) | ||
2621 | { | ||
2622 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
2623 | u32 hotplug_en; | ||
2624 | |||
2525 | /* Note HDMI and DP share hotplug bits */ | 2625 | /* Note HDMI and DP share hotplug bits */ |
2526 | hotplug_en = 0; | 2626 | hotplug_en = 0; |
2527 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | 2627 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2528 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | 2628 | hotplug_en |= PORTB_HOTPLUG_INT_EN; |
2529 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | 2629 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) |
2530 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | 2630 | hotplug_en |= PORTC_HOTPLUG_INT_EN; |
2531 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | 2631 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) |
2532 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | 2632 | hotplug_en |= PORTD_HOTPLUG_INT_EN; |
2533 | if (IS_G4X(dev)) { | 2633 | if (IS_G4X(dev)) { |
2534 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) | 2634 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) |
2535 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | 2635 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
@@ -2556,10 +2656,6 @@ static int i965_irq_postinstall(struct drm_device *dev) | |||
2556 | /* Ignore TV since it's buggy */ | 2656 | /* Ignore TV since it's buggy */ |
2557 | 2657 | ||
2558 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | 2658 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
2559 | |||
2560 | intel_opregion_enable_asle(dev); | ||
2561 | |||
2562 | return 0; | ||
2563 | } | 2659 | } |
2564 | 2660 | ||
2565 | static irqreturn_t i965_irq_handler(int irq, void *arg) | 2661 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
@@ -2655,6 +2751,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) | |||
2655 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | 2751 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
2656 | intel_opregion_asle_intr(dev); | 2752 | intel_opregion_asle_intr(dev); |
2657 | 2753 | ||
2754 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | ||
2755 | gmbus_irq_handler(dev); | ||
2756 | |||
2658 | /* With MSI, interrupts are only generated when iir | 2757 | /* With MSI, interrupts are only generated when iir |
2659 | * transitions from zero to nonzero. If another bit got | 2758 | * transitions from zero to nonzero. If another bit got |
2660 | * set while we were handling the existing iir bits, then | 2759 | * set while we were handling the existing iir bits, then |
@@ -2706,10 +2805,16 @@ void intel_irq_init(struct drm_device *dev) | |||
2706 | struct drm_i915_private *dev_priv = dev->dev_private; | 2805 | struct drm_i915_private *dev_priv = dev->dev_private; |
2707 | 2806 | ||
2708 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | 2807 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
2709 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); | 2808 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
2710 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); | 2809 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
2711 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); | 2810 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
2712 | 2811 | ||
2812 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, | ||
2813 | i915_hangcheck_elapsed, | ||
2814 | (unsigned long) dev); | ||
2815 | |||
2816 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); | ||
2817 | |||
2713 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | 2818 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
2714 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | 2819 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
2715 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | 2820 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
@@ -2730,7 +2835,8 @@ void intel_irq_init(struct drm_device *dev) | |||
2730 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | 2835 | dev->driver->irq_uninstall = valleyview_irq_uninstall; |
2731 | dev->driver->enable_vblank = valleyview_enable_vblank; | 2836 | dev->driver->enable_vblank = valleyview_enable_vblank; |
2732 | dev->driver->disable_vblank = valleyview_disable_vblank; | 2837 | dev->driver->disable_vblank = valleyview_disable_vblank; |
2733 | } else if (IS_IVYBRIDGE(dev)) { | 2838 | dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup; |
2839 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | ||
2734 | /* Share pre & uninstall handlers with ILK/SNB */ | 2840 | /* Share pre & uninstall handlers with ILK/SNB */ |
2735 | dev->driver->irq_handler = ivybridge_irq_handler; | 2841 | dev->driver->irq_handler = ivybridge_irq_handler; |
2736 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | 2842 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
@@ -2738,14 +2844,6 @@ void intel_irq_init(struct drm_device *dev) | |||
2738 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | 2844 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
2739 | dev->driver->enable_vblank = ivybridge_enable_vblank; | 2845 | dev->driver->enable_vblank = ivybridge_enable_vblank; |
2740 | dev->driver->disable_vblank = ivybridge_disable_vblank; | 2846 | dev->driver->disable_vblank = ivybridge_disable_vblank; |
2741 | } else if (IS_HASWELL(dev)) { | ||
2742 | /* Share interrupts handling with IVB */ | ||
2743 | dev->driver->irq_handler = ivybridge_irq_handler; | ||
2744 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | ||
2745 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; | ||
2746 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | ||
2747 | dev->driver->enable_vblank = ivybridge_enable_vblank; | ||
2748 | dev->driver->disable_vblank = ivybridge_disable_vblank; | ||
2749 | } else if (HAS_PCH_SPLIT(dev)) { | 2847 | } else if (HAS_PCH_SPLIT(dev)) { |
2750 | dev->driver->irq_handler = ironlake_irq_handler; | 2848 | dev->driver->irq_handler = ironlake_irq_handler; |
2751 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | 2849 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
@@ -2764,13 +2862,23 @@ void intel_irq_init(struct drm_device *dev) | |||
2764 | dev->driver->irq_postinstall = i915_irq_postinstall; | 2862 | dev->driver->irq_postinstall = i915_irq_postinstall; |
2765 | dev->driver->irq_uninstall = i915_irq_uninstall; | 2863 | dev->driver->irq_uninstall = i915_irq_uninstall; |
2766 | dev->driver->irq_handler = i915_irq_handler; | 2864 | dev->driver->irq_handler = i915_irq_handler; |
2865 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | ||
2767 | } else { | 2866 | } else { |
2768 | dev->driver->irq_preinstall = i965_irq_preinstall; | 2867 | dev->driver->irq_preinstall = i965_irq_preinstall; |
2769 | dev->driver->irq_postinstall = i965_irq_postinstall; | 2868 | dev->driver->irq_postinstall = i965_irq_postinstall; |
2770 | dev->driver->irq_uninstall = i965_irq_uninstall; | 2869 | dev->driver->irq_uninstall = i965_irq_uninstall; |
2771 | dev->driver->irq_handler = i965_irq_handler; | 2870 | dev->driver->irq_handler = i965_irq_handler; |
2871 | dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup; | ||
2772 | } | 2872 | } |
2773 | dev->driver->enable_vblank = i915_enable_vblank; | 2873 | dev->driver->enable_vblank = i915_enable_vblank; |
2774 | dev->driver->disable_vblank = i915_disable_vblank; | 2874 | dev->driver->disable_vblank = i915_disable_vblank; |
2775 | } | 2875 | } |
2776 | } | 2876 | } |
2877 | |||
2878 | void intel_hpd_init(struct drm_device *dev) | ||
2879 | { | ||
2880 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
2881 | |||
2882 | if (dev_priv->display.hpd_irq_setup) | ||
2883 | dev_priv->display.hpd_irq_setup(dev); | ||
2884 | } | ||