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path: root/drivers/gpu/drm/i915/i915_irq.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c25
1 files changed, 13 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1c00751eca69..acf1ab3ff0d9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1075,7 +1075,7 @@ void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
1075 u32 pm_iir, int new_delay) 1075 u32 pm_iir, int new_delay)
1076{ 1076{
1077 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 1077 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1078 if (new_delay >= dev_priv->rps.max_delay) { 1078 if (new_delay >= dev_priv->rps.max_freq_softlimit) {
1079 /* Mask UP THRESHOLD Interrupts */ 1079 /* Mask UP THRESHOLD Interrupts */
1080 I915_WRITE(GEN6_PMINTRMSK, 1080 I915_WRITE(GEN6_PMINTRMSK,
1081 I915_READ(GEN6_PMINTRMSK) | 1081 I915_READ(GEN6_PMINTRMSK) |
@@ -1090,7 +1090,7 @@ void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
1090 dev_priv->rps.rp_down_masked = false; 1090 dev_priv->rps.rp_down_masked = false;
1091 } 1091 }
1092 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { 1092 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1093 if (new_delay <= dev_priv->rps.min_delay) { 1093 if (new_delay <= dev_priv->rps.min_freq_softlimit) {
1094 /* Mask DOWN THRESHOLD Interrupts */ 1094 /* Mask DOWN THRESHOLD Interrupts */
1095 I915_WRITE(GEN6_PMINTRMSK, 1095 I915_WRITE(GEN6_PMINTRMSK,
1096 I915_READ(GEN6_PMINTRMSK) | 1096 I915_READ(GEN6_PMINTRMSK) |
@@ -1136,38 +1136,39 @@ static void gen6_pm_rps_work(struct work_struct *work)
1136 adj *= 2; 1136 adj *= 2;
1137 else 1137 else
1138 adj = 1; 1138 adj = 1;
1139 new_delay = dev_priv->rps.cur_delay + adj; 1139 new_delay = dev_priv->rps.cur_freq + adj;
1140 1140
1141 /* 1141 /*
1142 * For better performance, jump directly 1142 * For better performance, jump directly
1143 * to RPe if we're below it. 1143 * to RPe if we're below it.
1144 */ 1144 */
1145 if (new_delay < dev_priv->rps.rpe_delay) 1145 if (new_delay < dev_priv->rps.efficient_freq)
1146 new_delay = dev_priv->rps.rpe_delay; 1146 new_delay = dev_priv->rps.efficient_freq;
1147 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { 1147 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1148 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) 1148 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1149 new_delay = dev_priv->rps.rpe_delay; 1149 new_delay = dev_priv->rps.efficient_freq;
1150 else 1150 else
1151 new_delay = dev_priv->rps.min_delay; 1151 new_delay = dev_priv->rps.min_freq_softlimit;
1152 adj = 0; 1152 adj = 0;
1153 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { 1153 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1154 if (adj < 0) 1154 if (adj < 0)
1155 adj *= 2; 1155 adj *= 2;
1156 else 1156 else
1157 adj = -1; 1157 adj = -1;
1158 new_delay = dev_priv->rps.cur_delay + adj; 1158 new_delay = dev_priv->rps.cur_freq + adj;
1159 } else { /* unknown event */ 1159 } else { /* unknown event */
1160 new_delay = dev_priv->rps.cur_delay; 1160 new_delay = dev_priv->rps.cur_freq;
1161 } 1161 }
1162 1162
1163 /* sysfs frequency interfaces may have snuck in while servicing the 1163 /* sysfs frequency interfaces may have snuck in while servicing the
1164 * interrupt 1164 * interrupt
1165 */ 1165 */
1166 new_delay = clamp_t(int, new_delay, 1166 new_delay = clamp_t(int, new_delay,
1167 dev_priv->rps.min_delay, dev_priv->rps.max_delay); 1167 dev_priv->rps.min_freq_softlimit,
1168 dev_priv->rps.max_freq_softlimit);
1168 1169
1169 gen6_set_pm_mask(dev_priv, pm_iir, new_delay); 1170 gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
1170 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; 1171 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1171 1172
1172 if (IS_VALLEYVIEW(dev_priv->dev)) 1173 if (IS_VALLEYVIEW(dev_priv->dev))
1173 valleyview_set_rps(dev_priv->dev, new_delay); 1174 valleyview_set_rps(dev_priv->dev, new_delay);