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path: root/drivers/gpu/drm/i915/i915_irq.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c1000
1 files changed, 367 insertions, 633 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f66392b6e287..981834b0f9b6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -37,6 +37,14 @@
37#include "i915_trace.h" 37#include "i915_trace.h"
38#include "intel_drv.h" 38#include "intel_drv.h"
39 39
40/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
40static const u32 hpd_ibx[] = { 48static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG, 49 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
@@ -118,20 +126,22 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
118 126
119#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ 127#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ 128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ 129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \ 130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
124} while (0) 132} while (0)
125 133
126#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ 134#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ 135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \ 136 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \ 137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
131} while (0) 139} while (0)
132 140
141static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
142
133/* For display hotplug interrupt */ 143/* For display hotplug interrupt */
134static void 144void
135ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) 145ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
136{ 146{
137 assert_spin_locked(&dev_priv->irq_lock); 147 assert_spin_locked(&dev_priv->irq_lock);
@@ -146,7 +156,7 @@ ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
146 } 156 }
147} 157}
148 158
149static void 159void
150ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) 160ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
151{ 161{
152 assert_spin_locked(&dev_priv->irq_lock); 162 assert_spin_locked(&dev_priv->irq_lock);
@@ -192,71 +202,28 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
192 ilk_update_gt_irq(dev_priv, mask, 0); 202 ilk_update_gt_irq(dev_priv, mask, 0);
193} 203}
194 204
195/** 205static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204{
205 uint32_t new_val;
206
207 assert_spin_locked(&dev_priv->irq_lock);
208
209 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
210 return;
211
212 new_val = dev_priv->pm_irq_mask;
213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
219 POSTING_READ(GEN6_PMIMR);
220 }
221}
222
223void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
224{ 206{
225 snb_update_pm_irq(dev_priv, mask, mask); 207 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
226} 208}
227 209
228void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 210static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
229{ 211{
230 snb_update_pm_irq(dev_priv, mask, 0); 212 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
231} 213}
232 214
233static bool ivb_can_enable_err_int(struct drm_device *dev) 215static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
234{ 216{
235 struct drm_i915_private *dev_priv = dev->dev_private; 217 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
239 assert_spin_locked(&dev_priv->irq_lock);
240
241 for_each_pipe(dev_priv, pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249} 218}
250 219
251/** 220/**
252 * bdw_update_pm_irq - update GT interrupt 2 221 * snb_update_pm_irq - update GEN6_PMIMR
253 * @dev_priv: driver private 222 * @dev_priv: driver private
254 * @interrupt_mask: mask of interrupt bits to update 223 * @interrupt_mask: mask of interrupt bits to update
255 * @enabled_irq_mask: mask of interrupt bits to enable 224 * @enabled_irq_mask: mask of interrupt bits to enable
256 *
257 * Copied from the snb function, updated with relevant register offsets
258 */ 225 */
259static void bdw_update_pm_irq(struct drm_i915_private *dev_priv, 226static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
260 uint32_t interrupt_mask, 227 uint32_t interrupt_mask,
261 uint32_t enabled_irq_mask) 228 uint32_t enabled_irq_mask)
262{ 229{
@@ -264,144 +231,87 @@ static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
264 231
265 assert_spin_locked(&dev_priv->irq_lock); 232 assert_spin_locked(&dev_priv->irq_lock);
266 233
267 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
268 return;
269
270 new_val = dev_priv->pm_irq_mask; 234 new_val = dev_priv->pm_irq_mask;
271 new_val &= ~interrupt_mask; 235 new_val &= ~interrupt_mask;
272 new_val |= (~enabled_irq_mask & interrupt_mask); 236 new_val |= (~enabled_irq_mask & interrupt_mask);
273 237
274 if (new_val != dev_priv->pm_irq_mask) { 238 if (new_val != dev_priv->pm_irq_mask) {
275 dev_priv->pm_irq_mask = new_val; 239 dev_priv->pm_irq_mask = new_val;
276 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask); 240 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
277 POSTING_READ(GEN8_GT_IMR(2)); 241 POSTING_READ(gen6_pm_imr(dev_priv));
278 } 242 }
279} 243}
280 244
281void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 245void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
282{ 246{
283 bdw_update_pm_irq(dev_priv, mask, mask); 247 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
284} 248 return;
285 249
286void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 250 snb_update_pm_irq(dev_priv, mask, mask);
287{
288 bdw_update_pm_irq(dev_priv, mask, 0);
289} 251}
290 252
291static bool cpt_can_enable_serr_int(struct drm_device *dev) 253static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
254 uint32_t mask)
292{ 255{
293 struct drm_i915_private *dev_priv = dev->dev_private; 256 snb_update_pm_irq(dev_priv, mask, 0);
294 enum pipe pipe;
295 struct intel_crtc *crtc;
296
297 assert_spin_locked(&dev_priv->irq_lock);
298
299 for_each_pipe(dev_priv, pipe) {
300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
301
302 if (crtc->pch_fifo_underrun_disabled)
303 return false;
304 }
305
306 return true;
307} 257}
308 258
309void i9xx_check_fifo_underruns(struct drm_device *dev) 259void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
310{ 260{
311 struct drm_i915_private *dev_priv = dev->dev_private; 261 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
312 struct intel_crtc *crtc; 262 return;
313 unsigned long flags;
314
315 spin_lock_irqsave(&dev_priv->irq_lock, flags);
316
317 for_each_intel_crtc(dev, crtc) {
318 u32 reg = PIPESTAT(crtc->pipe);
319 u32 pipestat;
320
321 if (crtc->cpu_fifo_underrun_disabled)
322 continue;
323
324 pipestat = I915_READ(reg) & 0xffff0000;
325 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
326 continue;
327
328 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
329 POSTING_READ(reg);
330
331 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
332 }
333 263
334 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 264 __gen6_disable_pm_irq(dev_priv, mask);
335} 265}
336 266
337static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, 267void gen6_reset_rps_interrupts(struct drm_device *dev)
338 enum pipe pipe,
339 bool enable, bool old)
340{ 268{
341 struct drm_i915_private *dev_priv = dev->dev_private; 269 struct drm_i915_private *dev_priv = dev->dev_private;
342 u32 reg = PIPESTAT(pipe); 270 uint32_t reg = gen6_pm_iir(dev_priv);
343 u32 pipestat = I915_READ(reg) & 0xffff0000;
344
345 assert_spin_locked(&dev_priv->irq_lock);
346 271
347 if (enable) { 272 spin_lock_irq(&dev_priv->irq_lock);
348 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); 273 I915_WRITE(reg, dev_priv->pm_rps_events);
349 POSTING_READ(reg); 274 I915_WRITE(reg, dev_priv->pm_rps_events);
350 } else { 275 POSTING_READ(reg);
351 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) 276 spin_unlock_irq(&dev_priv->irq_lock);
352 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
353 }
354} 277}
355 278
356static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, 279void gen6_enable_rps_interrupts(struct drm_device *dev)
357 enum pipe pipe, bool enable)
358{ 280{
359 struct drm_i915_private *dev_priv = dev->dev_private; 281 struct drm_i915_private *dev_priv = dev->dev_private;
360 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
361 DE_PIPEB_FIFO_UNDERRUN;
362 282
363 if (enable) 283 spin_lock_irq(&dev_priv->irq_lock);
364 ironlake_enable_display_irq(dev_priv, bit); 284 WARN_ON(dev_priv->rps.pm_iir);
365 else 285 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
366 ironlake_disable_display_irq(dev_priv, bit); 286 dev_priv->rps.interrupts_enabled = true;
287 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
288 spin_unlock_irq(&dev_priv->irq_lock);
367} 289}
368 290
369static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, 291void gen6_disable_rps_interrupts(struct drm_device *dev)
370 enum pipe pipe,
371 bool enable, bool old)
372{ 292{
373 struct drm_i915_private *dev_priv = dev->dev_private; 293 struct drm_i915_private *dev_priv = dev->dev_private;
374 if (enable) {
375 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
376 294
377 if (!ivb_can_enable_err_int(dev)) 295 spin_lock_irq(&dev_priv->irq_lock);
378 return; 296 dev_priv->rps.interrupts_enabled = false;
297 spin_unlock_irq(&dev_priv->irq_lock);
379 298
380 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 299 cancel_work_sync(&dev_priv->rps.work);
381 } else {
382 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
383 300
384 if (old && 301 spin_lock_irq(&dev_priv->irq_lock);
385 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
386 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
387 pipe_name(pipe));
388 }
389 }
390}
391 302
392static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, 303 I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?
393 enum pipe pipe, bool enable) 304 ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);
394{
395 struct drm_i915_private *dev_priv = dev->dev_private;
396 305
397 assert_spin_locked(&dev_priv->irq_lock); 306 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
307 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
308 ~dev_priv->pm_rps_events);
309 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
310 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
398 311
399 if (enable) 312 dev_priv->rps.pm_iir = 0;
400 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; 313
401 else 314 spin_unlock_irq(&dev_priv->irq_lock);
402 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
403 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
404 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
405} 315}
406 316
407/** 317/**
@@ -410,9 +320,9 @@ static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
410 * @interrupt_mask: mask of interrupt bits to update 320 * @interrupt_mask: mask of interrupt bits to update
411 * @enabled_irq_mask: mask of interrupt bits to enable 321 * @enabled_irq_mask: mask of interrupt bits to enable
412 */ 322 */
413static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 323void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
414 uint32_t interrupt_mask, 324 uint32_t interrupt_mask,
415 uint32_t enabled_irq_mask) 325 uint32_t enabled_irq_mask)
416{ 326{
417 uint32_t sdeimr = I915_READ(SDEIMR); 327 uint32_t sdeimr = I915_READ(SDEIMR);
418 sdeimr &= ~interrupt_mask; 328 sdeimr &= ~interrupt_mask;
@@ -426,160 +336,6 @@ static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
426 I915_WRITE(SDEIMR, sdeimr); 336 I915_WRITE(SDEIMR, sdeimr);
427 POSTING_READ(SDEIMR); 337 POSTING_READ(SDEIMR);
428} 338}
429#define ibx_enable_display_interrupt(dev_priv, bits) \
430 ibx_display_interrupt_update((dev_priv), (bits), (bits))
431#define ibx_disable_display_interrupt(dev_priv, bits) \
432 ibx_display_interrupt_update((dev_priv), (bits), 0)
433
434static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
435 enum transcoder pch_transcoder,
436 bool enable)
437{
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
440 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
441
442 if (enable)
443 ibx_enable_display_interrupt(dev_priv, bit);
444 else
445 ibx_disable_display_interrupt(dev_priv, bit);
446}
447
448static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
449 enum transcoder pch_transcoder,
450 bool enable, bool old)
451{
452 struct drm_i915_private *dev_priv = dev->dev_private;
453
454 if (enable) {
455 I915_WRITE(SERR_INT,
456 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
457
458 if (!cpt_can_enable_serr_int(dev))
459 return;
460
461 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
462 } else {
463 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
464
465 if (old && I915_READ(SERR_INT) &
466 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
467 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
468 transcoder_name(pch_transcoder));
469 }
470 }
471}
472
473/**
474 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
475 * @dev: drm device
476 * @pipe: pipe
477 * @enable: true if we want to report FIFO underrun errors, false otherwise
478 *
479 * This function makes us disable or enable CPU fifo underruns for a specific
480 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
481 * reporting for one pipe may also disable all the other CPU error interruts for
482 * the other pipes, due to the fact that there's just one interrupt mask/enable
483 * bit for all the pipes.
484 *
485 * Returns the previous state of underrun reporting.
486 */
487static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
488 enum pipe pipe, bool enable)
489{
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
493 bool old;
494
495 assert_spin_locked(&dev_priv->irq_lock);
496
497 old = !intel_crtc->cpu_fifo_underrun_disabled;
498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
499
500 if (HAS_GMCH_DISPLAY(dev))
501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
502 else if (IS_GEN5(dev) || IS_GEN6(dev))
503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
504 else if (IS_GEN7(dev))
505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
506 else if (IS_GEN8(dev))
507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
508
509 return old;
510}
511
512bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
513 enum pipe pipe, bool enable)
514{
515 struct drm_i915_private *dev_priv = dev->dev_private;
516 unsigned long flags;
517 bool ret;
518
519 spin_lock_irqsave(&dev_priv->irq_lock, flags);
520 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
521 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
522
523 return ret;
524}
525
526static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
527 enum pipe pipe)
528{
529 struct drm_i915_private *dev_priv = dev->dev_private;
530 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
532
533 return !intel_crtc->cpu_fifo_underrun_disabled;
534}
535
536/**
537 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
538 * @dev: drm device
539 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
540 * @enable: true if we want to report FIFO underrun errors, false otherwise
541 *
542 * This function makes us disable or enable PCH fifo underruns for a specific
543 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
544 * underrun reporting for one transcoder may also disable all the other PCH
545 * error interruts for the other transcoders, due to the fact that there's just
546 * one interrupt mask/enable bit for all the transcoders.
547 *
548 * Returns the previous state of underrun reporting.
549 */
550bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
551 enum transcoder pch_transcoder,
552 bool enable)
553{
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
557 unsigned long flags;
558 bool old;
559
560 /*
561 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
562 * has only one pch transcoder A that all pipes can use. To avoid racy
563 * pch transcoder -> pipe lookups from interrupt code simply store the
564 * underrun statistics in crtc A. Since we never expose this anywhere
565 * nor use it outside of the fifo underrun code here using the "wrong"
566 * crtc on LPT won't cause issues.
567 */
568
569 spin_lock_irqsave(&dev_priv->irq_lock, flags);
570
571 old = !intel_crtc->pch_fifo_underrun_disabled;
572 intel_crtc->pch_fifo_underrun_disabled = !enable;
573
574 if (HAS_PCH_IBX(dev))
575 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
576 else
577 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
578
579 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
580 return old;
581}
582
583 339
584static void 340static void
585__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 341__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
@@ -589,6 +345,7 @@ __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
589 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; 345 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
590 346
591 assert_spin_locked(&dev_priv->irq_lock); 347 assert_spin_locked(&dev_priv->irq_lock);
348 WARN_ON(!intel_irqs_enabled(dev_priv));
592 349
593 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 350 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
594 status_mask & ~PIPESTAT_INT_STATUS_MASK, 351 status_mask & ~PIPESTAT_INT_STATUS_MASK,
@@ -615,6 +372,7 @@ __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
615 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; 372 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
616 373
617 assert_spin_locked(&dev_priv->irq_lock); 374 assert_spin_locked(&dev_priv->irq_lock);
375 WARN_ON(!intel_irqs_enabled(dev_priv));
618 376
619 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 377 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
620 status_mask & ~PIPESTAT_INT_STATUS_MASK, 378 status_mask & ~PIPESTAT_INT_STATUS_MASK,
@@ -694,19 +452,18 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
694static void i915_enable_asle_pipestat(struct drm_device *dev) 452static void i915_enable_asle_pipestat(struct drm_device *dev)
695{ 453{
696 struct drm_i915_private *dev_priv = dev->dev_private; 454 struct drm_i915_private *dev_priv = dev->dev_private;
697 unsigned long irqflags;
698 455
699 if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) 456 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
700 return; 457 return;
701 458
702 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 459 spin_lock_irq(&dev_priv->irq_lock);
703 460
704 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 461 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
705 if (INTEL_INFO(dev)->gen >= 4) 462 if (INTEL_INFO(dev)->gen >= 4)
706 i915_enable_pipestat(dev_priv, PIPE_A, 463 i915_enable_pipestat(dev_priv, PIPE_A,
707 PIPE_LEGACY_BLC_EVENT_STATUS); 464 PIPE_LEGACY_BLC_EVENT_STATUS);
708 465
709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 466 spin_unlock_irq(&dev_priv->irq_lock);
710} 467}
711 468
712/** 469/**
@@ -1094,18 +851,17 @@ static void i915_digport_work_func(struct work_struct *work)
1094{ 851{
1095 struct drm_i915_private *dev_priv = 852 struct drm_i915_private *dev_priv =
1096 container_of(work, struct drm_i915_private, dig_port_work); 853 container_of(work, struct drm_i915_private, dig_port_work);
1097 unsigned long irqflags;
1098 u32 long_port_mask, short_port_mask; 854 u32 long_port_mask, short_port_mask;
1099 struct intel_digital_port *intel_dig_port; 855 struct intel_digital_port *intel_dig_port;
1100 int i, ret; 856 int i, ret;
1101 u32 old_bits = 0; 857 u32 old_bits = 0;
1102 858
1103 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 859 spin_lock_irq(&dev_priv->irq_lock);
1104 long_port_mask = dev_priv->long_hpd_port_mask; 860 long_port_mask = dev_priv->long_hpd_port_mask;
1105 dev_priv->long_hpd_port_mask = 0; 861 dev_priv->long_hpd_port_mask = 0;
1106 short_port_mask = dev_priv->short_hpd_port_mask; 862 short_port_mask = dev_priv->short_hpd_port_mask;
1107 dev_priv->short_hpd_port_mask = 0; 863 dev_priv->short_hpd_port_mask = 0;
1108 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 864 spin_unlock_irq(&dev_priv->irq_lock);
1109 865
1110 for (i = 0; i < I915_MAX_PORTS; i++) { 866 for (i = 0; i < I915_MAX_PORTS; i++) {
1111 bool valid = false; 867 bool valid = false;
@@ -1130,9 +886,9 @@ static void i915_digport_work_func(struct work_struct *work)
1130 } 886 }
1131 887
1132 if (old_bits) { 888 if (old_bits) {
1133 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 889 spin_lock_irq(&dev_priv->irq_lock);
1134 dev_priv->hpd_event_bits |= old_bits; 890 dev_priv->hpd_event_bits |= old_bits;
1135 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 891 spin_unlock_irq(&dev_priv->irq_lock);
1136 schedule_work(&dev_priv->hotplug_work); 892 schedule_work(&dev_priv->hotplug_work);
1137 } 893 }
1138} 894}
@@ -1151,7 +907,6 @@ static void i915_hotplug_work_func(struct work_struct *work)
1151 struct intel_connector *intel_connector; 907 struct intel_connector *intel_connector;
1152 struct intel_encoder *intel_encoder; 908 struct intel_encoder *intel_encoder;
1153 struct drm_connector *connector; 909 struct drm_connector *connector;
1154 unsigned long irqflags;
1155 bool hpd_disabled = false; 910 bool hpd_disabled = false;
1156 bool changed = false; 911 bool changed = false;
1157 u32 hpd_event_bits; 912 u32 hpd_event_bits;
@@ -1159,7 +914,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
1159 mutex_lock(&mode_config->mutex); 914 mutex_lock(&mode_config->mutex);
1160 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 915 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1161 916
1162 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 917 spin_lock_irq(&dev_priv->irq_lock);
1163 918
1164 hpd_event_bits = dev_priv->hpd_event_bits; 919 hpd_event_bits = dev_priv->hpd_event_bits;
1165 dev_priv->hpd_event_bits = 0; 920 dev_priv->hpd_event_bits = 0;
@@ -1193,7 +948,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
1193 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); 948 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1194 } 949 }
1195 950
1196 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 951 spin_unlock_irq(&dev_priv->irq_lock);
1197 952
1198 list_for_each_entry(connector, &mode_config->connector_list, head) { 953 list_for_each_entry(connector, &mode_config->connector_list, head) {
1199 intel_connector = to_intel_connector(connector); 954 intel_connector = to_intel_connector(connector);
@@ -1260,11 +1015,7 @@ static void notify_ring(struct drm_device *dev,
1260 1015
1261 trace_i915_gem_request_complete(ring); 1016 trace_i915_gem_request_complete(ring);
1262 1017
1263 if (drm_core_check_feature(dev, DRIVER_MODESET))
1264 intel_notify_mmio_flip(ring);
1265
1266 wake_up_all(&ring->irq_queue); 1018 wake_up_all(&ring->irq_queue);
1267 i915_queue_hangcheck(dev);
1268} 1019}
1269 1020
1270static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, 1021static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
@@ -1400,14 +1151,15 @@ static void gen6_pm_rps_work(struct work_struct *work)
1400 int new_delay, adj; 1151 int new_delay, adj;
1401 1152
1402 spin_lock_irq(&dev_priv->irq_lock); 1153 spin_lock_irq(&dev_priv->irq_lock);
1154 /* Speed up work cancelation during disabling rps interrupts. */
1155 if (!dev_priv->rps.interrupts_enabled) {
1156 spin_unlock_irq(&dev_priv->irq_lock);
1157 return;
1158 }
1403 pm_iir = dev_priv->rps.pm_iir; 1159 pm_iir = dev_priv->rps.pm_iir;
1404 dev_priv->rps.pm_iir = 0; 1160 dev_priv->rps.pm_iir = 0;
1405 if (INTEL_INFO(dev_priv->dev)->gen >= 8) 1161 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1406 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); 1162 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1407 else {
1408 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1409 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1410 }
1411 spin_unlock_irq(&dev_priv->irq_lock); 1163 spin_unlock_irq(&dev_priv->irq_lock);
1412 1164
1413 /* Make sure we didn't queue anything we're not going to process. */ 1165 /* Make sure we didn't queue anything we're not going to process. */
@@ -1488,7 +1240,6 @@ static void ivybridge_parity_work(struct work_struct *work)
1488 u32 error_status, row, bank, subbank; 1240 u32 error_status, row, bank, subbank;
1489 char *parity_event[6]; 1241 char *parity_event[6];
1490 uint32_t misccpctl; 1242 uint32_t misccpctl;
1491 unsigned long flags;
1492 uint8_t slice = 0; 1243 uint8_t slice = 0;
1493 1244
1494 /* We must turn off DOP level clock gating to access the L3 registers. 1245 /* We must turn off DOP level clock gating to access the L3 registers.
@@ -1547,9 +1298,9 @@ static void ivybridge_parity_work(struct work_struct *work)
1547 1298
1548out: 1299out:
1549 WARN_ON(dev_priv->l3_parity.which_slice); 1300 WARN_ON(dev_priv->l3_parity.which_slice);
1550 spin_lock_irqsave(&dev_priv->irq_lock, flags); 1301 spin_lock_irq(&dev_priv->irq_lock);
1551 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); 1302 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1552 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 1303 spin_unlock_irq(&dev_priv->irq_lock);
1553 1304
1554 mutex_unlock(&dev_priv->dev->struct_mutex); 1305 mutex_unlock(&dev_priv->dev->struct_mutex);
1555} 1306}
@@ -1601,28 +1352,13 @@ static void snb_gt_irq_handler(struct drm_device *dev,
1601 1352
1602 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 1353 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1603 GT_BSD_CS_ERROR_INTERRUPT | 1354 GT_BSD_CS_ERROR_INTERRUPT |
1604 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { 1355 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1605 i915_handle_error(dev, false, "GT error interrupt 0x%08x", 1356 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1606 gt_iir);
1607 }
1608 1357
1609 if (gt_iir & GT_PARITY_ERROR(dev)) 1358 if (gt_iir & GT_PARITY_ERROR(dev))
1610 ivybridge_parity_error_irq_handler(dev, gt_iir); 1359 ivybridge_parity_error_irq_handler(dev, gt_iir);
1611} 1360}
1612 1361
1613static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1614{
1615 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1616 return;
1617
1618 spin_lock(&dev_priv->irq_lock);
1619 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1620 gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1621 spin_unlock(&dev_priv->irq_lock);
1622
1623 queue_work(dev_priv->wq, &dev_priv->rps.work);
1624}
1625
1626static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, 1362static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1627 struct drm_i915_private *dev_priv, 1363 struct drm_i915_private *dev_priv,
1628 u32 master_ctl) 1364 u32 master_ctl)
@@ -1684,7 +1420,7 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1684 I915_WRITE(GEN8_GT_IIR(2), 1420 I915_WRITE(GEN8_GT_IIR(2),
1685 tmp & dev_priv->pm_rps_events); 1421 tmp & dev_priv->pm_rps_events);
1686 ret = IRQ_HANDLED; 1422 ret = IRQ_HANDLED;
1687 gen8_rps_irq_handler(dev_priv, tmp); 1423 gen6_rps_irq_handler(dev_priv, tmp);
1688 } else 1424 } else
1689 DRM_ERROR("The master control interrupt lied (PM)!\n"); 1425 DRM_ERROR("The master control interrupt lied (PM)!\n");
1690 } 1426 }
@@ -1898,7 +1634,7 @@ static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1898 1634
1899 if (!pipe_crc->entries) { 1635 if (!pipe_crc->entries) {
1900 spin_unlock(&pipe_crc->lock); 1636 spin_unlock(&pipe_crc->lock);
1901 DRM_ERROR("spurious interrupt\n"); 1637 DRM_DEBUG_KMS("spurious interrupt\n");
1902 return; 1638 return;
1903 } 1639 }
1904 1640
@@ -1984,24 +1720,30 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1984 * the work queue. */ 1720 * the work queue. */
1985static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) 1721static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1986{ 1722{
1723 /* TODO: RPS on GEN9+ is not supported yet. */
1724 if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
1725 "GEN9+: unexpected RPS IRQ\n"))
1726 return;
1727
1987 if (pm_iir & dev_priv->pm_rps_events) { 1728 if (pm_iir & dev_priv->pm_rps_events) {
1988 spin_lock(&dev_priv->irq_lock); 1729 spin_lock(&dev_priv->irq_lock);
1989 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1990 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); 1730 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1731 if (dev_priv->rps.interrupts_enabled) {
1732 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1733 queue_work(dev_priv->wq, &dev_priv->rps.work);
1734 }
1991 spin_unlock(&dev_priv->irq_lock); 1735 spin_unlock(&dev_priv->irq_lock);
1992
1993 queue_work(dev_priv->wq, &dev_priv->rps.work);
1994 } 1736 }
1995 1737
1738 if (INTEL_INFO(dev_priv)->gen >= 8)
1739 return;
1740
1996 if (HAS_VEBOX(dev_priv->dev)) { 1741 if (HAS_VEBOX(dev_priv->dev)) {
1997 if (pm_iir & PM_VEBOX_USER_INTERRUPT) 1742 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1998 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); 1743 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1999 1744
2000 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { 1745 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
2001 i915_handle_error(dev_priv->dev, false, 1746 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
2002 "VEBOX CS error interrupt 0x%08x",
2003 pm_iir);
2004 }
2005 } 1747 }
2006} 1748}
2007 1749
@@ -2031,9 +1773,9 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
2031 * we need to be careful that we only handle what we want to 1773 * we need to be careful that we only handle what we want to
2032 * handle. 1774 * handle.
2033 */ 1775 */
2034 mask = 0; 1776
2035 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) 1777 /* fifo underruns are filterered in the underrun handler. */
2036 mask |= PIPE_FIFO_UNDERRUN_STATUS; 1778 mask = PIPE_FIFO_UNDERRUN_STATUS;
2037 1779
2038 switch (pipe) { 1780 switch (pipe) {
2039 case PIPE_A: 1781 case PIPE_A:
@@ -2078,9 +1820,8 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
2078 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1820 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2079 i9xx_pipe_crc_irq_handler(dev, pipe); 1821 i9xx_pipe_crc_irq_handler(dev, pipe);
2080 1822
2081 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 1823 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2082 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 1824 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2083 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
2084 } 1825 }
2085 1826
2086 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 1827 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
@@ -2247,14 +1988,10 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
2247 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 1988 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2248 1989
2249 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 1990 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2250 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 1991 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2251 false))
2252 DRM_ERROR("PCH transcoder A FIFO underrun\n");
2253 1992
2254 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 1993 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2255 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 1994 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2256 false))
2257 DRM_ERROR("PCH transcoder B FIFO underrun\n");
2258} 1995}
2259 1996
2260static void ivb_err_int_handler(struct drm_device *dev) 1997static void ivb_err_int_handler(struct drm_device *dev)
@@ -2267,12 +2004,8 @@ static void ivb_err_int_handler(struct drm_device *dev)
2267 DRM_ERROR("Poison interrupt\n"); 2004 DRM_ERROR("Poison interrupt\n");
2268 2005
2269 for_each_pipe(dev_priv, pipe) { 2006 for_each_pipe(dev_priv, pipe) {
2270 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { 2007 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2271 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 2008 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2272 false))
2273 DRM_ERROR("Pipe %c FIFO underrun\n",
2274 pipe_name(pipe));
2275 }
2276 2009
2277 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 2010 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2278 if (IS_IVYBRIDGE(dev)) 2011 if (IS_IVYBRIDGE(dev))
@@ -2294,19 +2027,13 @@ static void cpt_serr_int_handler(struct drm_device *dev)
2294 DRM_ERROR("PCH poison interrupt\n"); 2027 DRM_ERROR("PCH poison interrupt\n");
2295 2028
2296 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) 2029 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2297 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 2030 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2298 false))
2299 DRM_ERROR("PCH transcoder A FIFO underrun\n");
2300 2031
2301 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) 2032 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2302 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 2033 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2303 false))
2304 DRM_ERROR("PCH transcoder B FIFO underrun\n");
2305 2034
2306 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) 2035 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2307 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, 2036 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2308 false))
2309 DRM_ERROR("PCH transcoder C FIFO underrun\n");
2310 2037
2311 I915_WRITE(SERR_INT, serr_int); 2038 I915_WRITE(SERR_INT, serr_int);
2312} 2039}
@@ -2372,9 +2099,7 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2372 intel_check_page_flip(dev, pipe); 2099 intel_check_page_flip(dev, pipe);
2373 2100
2374 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 2101 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2375 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 2102 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2376 DRM_ERROR("Pipe %c FIFO underrun\n",
2377 pipe_name(pipe));
2378 2103
2379 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 2104 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2380 i9xx_pipe_crc_irq_handler(dev, pipe); 2105 i9xx_pipe_crc_irq_handler(dev, pipe);
@@ -2524,6 +2249,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2524 irqreturn_t ret = IRQ_NONE; 2249 irqreturn_t ret = IRQ_NONE;
2525 uint32_t tmp = 0; 2250 uint32_t tmp = 0;
2526 enum pipe pipe; 2251 enum pipe pipe;
2252 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2253
2254 if (IS_GEN9(dev))
2255 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2256 GEN9_AUX_CHANNEL_D;
2527 2257
2528 master_ctl = I915_READ(GEN8_MASTER_IRQ); 2258 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2529 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; 2259 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
@@ -2556,7 +2286,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2556 if (tmp) { 2286 if (tmp) {
2557 I915_WRITE(GEN8_DE_PORT_IIR, tmp); 2287 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2558 ret = IRQ_HANDLED; 2288 ret = IRQ_HANDLED;
2559 if (tmp & GEN8_AUX_CHANNEL_A) 2289
2290 if (tmp & aux_mask)
2560 dp_aux_irq_handler(dev); 2291 dp_aux_irq_handler(dev);
2561 else 2292 else
2562 DRM_ERROR("Unexpected DE Port interrupt\n"); 2293 DRM_ERROR("Unexpected DE Port interrupt\n");
@@ -2566,7 +2297,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2566 } 2297 }
2567 2298
2568 for_each_pipe(dev_priv, pipe) { 2299 for_each_pipe(dev_priv, pipe) {
2569 uint32_t pipe_iir; 2300 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2570 2301
2571 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 2302 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2572 continue; 2303 continue;
@@ -2575,11 +2306,17 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2575 if (pipe_iir) { 2306 if (pipe_iir) {
2576 ret = IRQ_HANDLED; 2307 ret = IRQ_HANDLED;
2577 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); 2308 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2309
2578 if (pipe_iir & GEN8_PIPE_VBLANK && 2310 if (pipe_iir & GEN8_PIPE_VBLANK &&
2579 intel_pipe_handle_vblank(dev, pipe)) 2311 intel_pipe_handle_vblank(dev, pipe))
2580 intel_check_page_flip(dev, pipe); 2312 intel_check_page_flip(dev, pipe);
2581 2313
2582 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) { 2314 if (IS_GEN9(dev))
2315 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2316 else
2317 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2318
2319 if (flip_done) {
2583 intel_prepare_page_flip(dev, pipe); 2320 intel_prepare_page_flip(dev, pipe);
2584 intel_finish_page_flip_plane(dev, pipe); 2321 intel_finish_page_flip_plane(dev, pipe);
2585 } 2322 }
@@ -2587,18 +2324,20 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2587 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) 2324 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2588 hsw_pipe_crc_irq_handler(dev, pipe); 2325 hsw_pipe_crc_irq_handler(dev, pipe);
2589 2326
2590 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { 2327 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2591 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 2328 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2592 false)) 2329 pipe);
2593 DRM_ERROR("Pipe %c FIFO underrun\n", 2330
2594 pipe_name(pipe));
2595 }
2596 2331
2597 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { 2332 if (IS_GEN9(dev))
2333 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2334 else
2335 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2336
2337 if (fault_errors)
2598 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", 2338 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2599 pipe_name(pipe), 2339 pipe_name(pipe),
2600 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); 2340 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2601 }
2602 } else 2341 } else
2603 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); 2342 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2604 } 2343 }
@@ -2697,6 +2436,9 @@ static void i915_error_work_func(struct work_struct *work)
2697 * simulated reset via debugs, so get an RPM reference. 2436 * simulated reset via debugs, so get an RPM reference.
2698 */ 2437 */
2699 intel_runtime_pm_get(dev_priv); 2438 intel_runtime_pm_get(dev_priv);
2439
2440 intel_prepare_reset(dev);
2441
2700 /* 2442 /*
2701 * All state reset _must_ be completed before we update the 2443 * All state reset _must_ be completed before we update the
2702 * reset counter, for otherwise waiters might miss the reset 2444 * reset counter, for otherwise waiters might miss the reset
@@ -2705,7 +2447,7 @@ static void i915_error_work_func(struct work_struct *work)
2705 */ 2447 */
2706 ret = i915_reset(dev); 2448 ret = i915_reset(dev);
2707 2449
2708 intel_display_handle_reset(dev); 2450 intel_finish_reset(dev);
2709 2451
2710 intel_runtime_pm_put(dev_priv); 2452 intel_runtime_pm_put(dev_priv);
2711 2453
@@ -3330,10 +3072,15 @@ static void i915_hangcheck_elapsed(unsigned long data)
3330void i915_queue_hangcheck(struct drm_device *dev) 3072void i915_queue_hangcheck(struct drm_device *dev)
3331{ 3073{
3332 struct drm_i915_private *dev_priv = dev->dev_private; 3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;
3076
3333 if (!i915.enable_hangcheck) 3077 if (!i915.enable_hangcheck)
3334 return; 3078 return;
3335 3079
3336 mod_timer(&dev_priv->gpu_error.hangcheck_timer, 3080 /* Don't continually defer the hangcheck, but make sure it is active */
3081 if (timer_pending(timer))
3082 return;
3083 mod_timer(timer,
3337 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 3084 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3338} 3085}
3339 3086
@@ -3396,10 +3143,22 @@ static void ironlake_irq_reset(struct drm_device *dev)
3396 ibx_irq_reset(dev); 3143 ibx_irq_reset(dev);
3397} 3144}
3398 3145
3146static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3147{
3148 enum pipe pipe;
3149
3150 I915_WRITE(PORT_HOTPLUG_EN, 0);
3151 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3152
3153 for_each_pipe(dev_priv, pipe)
3154 I915_WRITE(PIPESTAT(pipe), 0xffff);
3155
3156 GEN5_IRQ_RESET(VLV_);
3157}
3158
3399static void valleyview_irq_preinstall(struct drm_device *dev) 3159static void valleyview_irq_preinstall(struct drm_device *dev)
3400{ 3160{
3401 struct drm_i915_private *dev_priv = dev->dev_private; 3161 struct drm_i915_private *dev_priv = dev->dev_private;
3402 int pipe;
3403 3162
3404 /* VLV magic */ 3163 /* VLV magic */
3405 I915_WRITE(VLV_IMR, 0); 3164 I915_WRITE(VLV_IMR, 0);
@@ -3407,22 +3166,11 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
3407 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); 3166 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3408 I915_WRITE(RING_IMR(BLT_RING_BASE), 0); 3167 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3409 3168
3410 /* and GT */
3411 I915_WRITE(GTIIR, I915_READ(GTIIR));
3412 I915_WRITE(GTIIR, I915_READ(GTIIR));
3413
3414 gen5_gt_irq_reset(dev); 3169 gen5_gt_irq_reset(dev);
3415 3170
3416 I915_WRITE(DPINVGTT, 0xff); 3171 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3417 3172
3418 I915_WRITE(PORT_HOTPLUG_EN, 0); 3173 vlv_display_irq_reset(dev_priv);
3419 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3420 for_each_pipe(dev_priv, pipe)
3421 I915_WRITE(PIPESTAT(pipe), 0xffff);
3422 I915_WRITE(VLV_IIR, 0xffffffff);
3423 I915_WRITE(VLV_IMR, 0xffffffff);
3424 I915_WRITE(VLV_IER, 0x0);
3425 POSTING_READ(VLV_IER);
3426} 3174}
3427 3175
3428static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) 3176static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
@@ -3444,8 +3192,8 @@ static void gen8_irq_reset(struct drm_device *dev)
3444 gen8_gt_irq_reset(dev_priv); 3192 gen8_gt_irq_reset(dev_priv);
3445 3193
3446 for_each_pipe(dev_priv, pipe) 3194 for_each_pipe(dev_priv, pipe)
3447 if (intel_display_power_enabled(dev_priv, 3195 if (intel_display_power_is_enabled(dev_priv,
3448 POWER_DOMAIN_PIPE(pipe))) 3196 POWER_DOMAIN_PIPE(pipe)))
3449 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); 3197 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3450 3198
3451 GEN5_IRQ_RESET(GEN8_DE_PORT_); 3199 GEN5_IRQ_RESET(GEN8_DE_PORT_);
@@ -3457,21 +3205,19 @@ static void gen8_irq_reset(struct drm_device *dev)
3457 3205
3458void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) 3206void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3459{ 3207{
3460 unsigned long irqflags;
3461 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; 3208 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3462 3209
3463 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3210 spin_lock_irq(&dev_priv->irq_lock);
3464 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], 3211 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3465 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); 3212 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3466 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], 3213 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3467 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); 3214 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3468 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3215 spin_unlock_irq(&dev_priv->irq_lock);
3469} 3216}
3470 3217
3471static void cherryview_irq_preinstall(struct drm_device *dev) 3218static void cherryview_irq_preinstall(struct drm_device *dev)
3472{ 3219{
3473 struct drm_i915_private *dev_priv = dev->dev_private; 3220 struct drm_i915_private *dev_priv = dev->dev_private;
3474 int pipe;
3475 3221
3476 I915_WRITE(GEN8_MASTER_IRQ, 0); 3222 I915_WRITE(GEN8_MASTER_IRQ, 0);
3477 POSTING_READ(GEN8_MASTER_IRQ); 3223 POSTING_READ(GEN8_MASTER_IRQ);
@@ -3480,20 +3226,9 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
3480 3226
3481 GEN5_IRQ_RESET(GEN8_PCU_); 3227 GEN5_IRQ_RESET(GEN8_PCU_);
3482 3228
3483 POSTING_READ(GEN8_PCU_IIR);
3484
3485 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); 3229 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3486 3230
3487 I915_WRITE(PORT_HOTPLUG_EN, 0); 3231 vlv_display_irq_reset(dev_priv);
3488 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3489
3490 for_each_pipe(dev_priv, pipe)
3491 I915_WRITE(PIPESTAT(pipe), 0xffff);
3492
3493 I915_WRITE(VLV_IMR, 0xffffffff);
3494 I915_WRITE(VLV_IER, 0x0);
3495 I915_WRITE(VLV_IIR, 0xffffffff);
3496 POSTING_READ(VLV_IIR);
3497} 3232}
3498 3233
3499static void ibx_hpd_irq_setup(struct drm_device *dev) 3234static void ibx_hpd_irq_setup(struct drm_device *dev)
@@ -3584,7 +3319,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
3584 3319
3585static int ironlake_irq_postinstall(struct drm_device *dev) 3320static int ironlake_irq_postinstall(struct drm_device *dev)
3586{ 3321{
3587 unsigned long irqflags;
3588 struct drm_i915_private *dev_priv = dev->dev_private; 3322 struct drm_i915_private *dev_priv = dev->dev_private;
3589 u32 display_mask, extra_mask; 3323 u32 display_mask, extra_mask;
3590 3324
@@ -3623,9 +3357,9 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
3623 * spinlocking not required here for correctness since interrupt 3357 * spinlocking not required here for correctness since interrupt
3624 * setup is guaranteed to run in single-threaded context. But we 3358 * setup is guaranteed to run in single-threaded context. But we
3625 * need it to make the assert_spin_locked happy. */ 3359 * need it to make the assert_spin_locked happy. */
3626 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3360 spin_lock_irq(&dev_priv->irq_lock);
3627 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 3361 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3628 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3362 spin_unlock_irq(&dev_priv->irq_lock);
3629 } 3363 }
3630 3364
3631 return 0; 3365 return 0;
@@ -3635,45 +3369,51 @@ static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3635{ 3369{
3636 u32 pipestat_mask; 3370 u32 pipestat_mask;
3637 u32 iir_mask; 3371 u32 iir_mask;
3372 enum pipe pipe;
3638 3373
3639 pipestat_mask = PIPESTAT_INT_STATUS_MASK | 3374 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3640 PIPE_FIFO_UNDERRUN_STATUS; 3375 PIPE_FIFO_UNDERRUN_STATUS;
3641 3376
3642 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); 3377 for_each_pipe(dev_priv, pipe)
3643 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); 3378 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3644 POSTING_READ(PIPESTAT(PIPE_A)); 3379 POSTING_READ(PIPESTAT(PIPE_A));
3645 3380
3646 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | 3381 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3647 PIPE_CRC_DONE_INTERRUPT_STATUS; 3382 PIPE_CRC_DONE_INTERRUPT_STATUS;
3648 3383
3649 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | 3384 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3650 PIPE_GMBUS_INTERRUPT_STATUS); 3385 for_each_pipe(dev_priv, pipe)
3651 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); 3386 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3652 3387
3653 iir_mask = I915_DISPLAY_PORT_INTERRUPT | 3388 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3654 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3389 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3655 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 3390 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3391 if (IS_CHERRYVIEW(dev_priv))
3392 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3656 dev_priv->irq_mask &= ~iir_mask; 3393 dev_priv->irq_mask &= ~iir_mask;
3657 3394
3658 I915_WRITE(VLV_IIR, iir_mask); 3395 I915_WRITE(VLV_IIR, iir_mask);
3659 I915_WRITE(VLV_IIR, iir_mask); 3396 I915_WRITE(VLV_IIR, iir_mask);
3660 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3661 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); 3397 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3662 POSTING_READ(VLV_IER); 3398 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3399 POSTING_READ(VLV_IMR);
3663} 3400}
3664 3401
3665static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) 3402static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3666{ 3403{
3667 u32 pipestat_mask; 3404 u32 pipestat_mask;
3668 u32 iir_mask; 3405 u32 iir_mask;
3406 enum pipe pipe;
3669 3407
3670 iir_mask = I915_DISPLAY_PORT_INTERRUPT | 3408 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3671 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3409 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3672 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 3410 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3411 if (IS_CHERRYVIEW(dev_priv))
3412 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3673 3413
3674 dev_priv->irq_mask |= iir_mask; 3414 dev_priv->irq_mask |= iir_mask;
3675 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3676 I915_WRITE(VLV_IMR, dev_priv->irq_mask); 3415 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3416 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3677 I915_WRITE(VLV_IIR, iir_mask); 3417 I915_WRITE(VLV_IIR, iir_mask);
3678 I915_WRITE(VLV_IIR, iir_mask); 3418 I915_WRITE(VLV_IIR, iir_mask);
3679 POSTING_READ(VLV_IIR); 3419 POSTING_READ(VLV_IIR);
@@ -3681,14 +3421,15 @@ static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3681 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | 3421 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3682 PIPE_CRC_DONE_INTERRUPT_STATUS; 3422 PIPE_CRC_DONE_INTERRUPT_STATUS;
3683 3423
3684 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | 3424 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3685 PIPE_GMBUS_INTERRUPT_STATUS); 3425 for_each_pipe(dev_priv, pipe)
3686 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); 3426 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3687 3427
3688 pipestat_mask = PIPESTAT_INT_STATUS_MASK | 3428 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3689 PIPE_FIFO_UNDERRUN_STATUS; 3429 PIPE_FIFO_UNDERRUN_STATUS;
3690 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); 3430
3691 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); 3431 for_each_pipe(dev_priv, pipe)
3432 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3692 POSTING_READ(PIPESTAT(PIPE_A)); 3433 POSTING_READ(PIPESTAT(PIPE_A));
3693} 3434}
3694 3435
@@ -3701,7 +3442,7 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3701 3442
3702 dev_priv->display_irqs_enabled = true; 3443 dev_priv->display_irqs_enabled = true;
3703 3444
3704 if (dev_priv->dev->irq_enabled) 3445 if (intel_irqs_enabled(dev_priv))
3705 valleyview_display_irqs_install(dev_priv); 3446 valleyview_display_irqs_install(dev_priv);
3706} 3447}
3707 3448
@@ -3714,34 +3455,36 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3714 3455
3715 dev_priv->display_irqs_enabled = false; 3456 dev_priv->display_irqs_enabled = false;
3716 3457
3717 if (dev_priv->dev->irq_enabled) 3458 if (intel_irqs_enabled(dev_priv))
3718 valleyview_display_irqs_uninstall(dev_priv); 3459 valleyview_display_irqs_uninstall(dev_priv);
3719} 3460}
3720 3461
3721static int valleyview_irq_postinstall(struct drm_device *dev) 3462static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3722{ 3463{
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 unsigned long irqflags;
3725
3726 dev_priv->irq_mask = ~0; 3464 dev_priv->irq_mask = ~0;
3727 3465
3728 I915_WRITE(PORT_HOTPLUG_EN, 0); 3466 I915_WRITE(PORT_HOTPLUG_EN, 0);
3729 POSTING_READ(PORT_HOTPLUG_EN); 3467 POSTING_READ(PORT_HOTPLUG_EN);
3730 3468
3731 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3732 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3733 I915_WRITE(VLV_IIR, 0xffffffff); 3469 I915_WRITE(VLV_IIR, 0xffffffff);
3734 POSTING_READ(VLV_IER); 3470 I915_WRITE(VLV_IIR, 0xffffffff);
3471 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3472 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3473 POSTING_READ(VLV_IMR);
3735 3474
3736 /* Interrupt setup is already guaranteed to be single-threaded, this is 3475 /* Interrupt setup is already guaranteed to be single-threaded, this is
3737 * just to make the assert_spin_locked check happy. */ 3476 * just to make the assert_spin_locked check happy. */
3738 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3477 spin_lock_irq(&dev_priv->irq_lock);
3739 if (dev_priv->display_irqs_enabled) 3478 if (dev_priv->display_irqs_enabled)
3740 valleyview_display_irqs_install(dev_priv); 3479 valleyview_display_irqs_install(dev_priv);
3741 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3480 spin_unlock_irq(&dev_priv->irq_lock);
3481}
3742 3482
3743 I915_WRITE(VLV_IIR, 0xffffffff); 3483static int valleyview_irq_postinstall(struct drm_device *dev)
3744 I915_WRITE(VLV_IIR, 0xffffffff); 3484{
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486
3487 vlv_display_irq_postinstall(dev_priv);
3745 3488
3746 gen5_gt_irq_postinstall(dev); 3489 gen5_gt_irq_postinstall(dev);
3747 3490
@@ -3783,24 +3526,35 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3783 3526
3784static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 3527static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3785{ 3528{
3786 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE | 3529 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3787 GEN8_PIPE_CDCLK_CRC_DONE | 3530 uint32_t de_pipe_enables;
3788 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3789 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3790 GEN8_PIPE_FIFO_UNDERRUN;
3791 int pipe; 3531 int pipe;
3532 u32 aux_en = GEN8_AUX_CHANNEL_A;
3533
3534 if (IS_GEN9(dev_priv)) {
3535 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3536 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3537 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3538 GEN9_AUX_CHANNEL_D;
3539 } else
3540 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3541 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3542
3543 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3544 GEN8_PIPE_FIFO_UNDERRUN;
3545
3792 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; 3546 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3793 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; 3547 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3794 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; 3548 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3795 3549
3796 for_each_pipe(dev_priv, pipe) 3550 for_each_pipe(dev_priv, pipe)
3797 if (intel_display_power_enabled(dev_priv, 3551 if (intel_display_power_is_enabled(dev_priv,
3798 POWER_DOMAIN_PIPE(pipe))) 3552 POWER_DOMAIN_PIPE(pipe)))
3799 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, 3553 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3800 dev_priv->de_irq_mask[pipe], 3554 dev_priv->de_irq_mask[pipe],
3801 de_pipe_enables); 3555 de_pipe_enables);
3802 3556
3803 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); 3557 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3804} 3558}
3805 3559
3806static int gen8_irq_postinstall(struct drm_device *dev) 3560static int gen8_irq_postinstall(struct drm_device *dev)
@@ -3823,33 +3577,8 @@ static int gen8_irq_postinstall(struct drm_device *dev)
3823static int cherryview_irq_postinstall(struct drm_device *dev) 3577static int cherryview_irq_postinstall(struct drm_device *dev)
3824{ 3578{
3825 struct drm_i915_private *dev_priv = dev->dev_private; 3579 struct drm_i915_private *dev_priv = dev->dev_private;
3826 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3827 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3828 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3829 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3830 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3831 PIPE_CRC_DONE_INTERRUPT_STATUS;
3832 unsigned long irqflags;
3833 int pipe;
3834 3580
3835 /* 3581 vlv_display_irq_postinstall(dev_priv);
3836 * Leave vblank interrupts masked initially. enable/disable will
3837 * toggle them based on usage.
3838 */
3839 dev_priv->irq_mask = ~enable_mask;
3840
3841 for_each_pipe(dev_priv, pipe)
3842 I915_WRITE(PIPESTAT(pipe), 0xffff);
3843
3844 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3845 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3846 for_each_pipe(dev_priv, pipe)
3847 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3848 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3849
3850 I915_WRITE(VLV_IIR, 0xffffffff);
3851 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3852 I915_WRITE(VLV_IER, enable_mask);
3853 3582
3854 gen8_gt_irq_postinstall(dev_priv); 3583 gen8_gt_irq_postinstall(dev_priv);
3855 3584
@@ -3869,41 +3598,39 @@ static void gen8_irq_uninstall(struct drm_device *dev)
3869 gen8_irq_reset(dev); 3598 gen8_irq_reset(dev);
3870} 3599}
3871 3600
3601static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3602{
3603 /* Interrupt setup is already guaranteed to be single-threaded, this is
3604 * just to make the assert_spin_locked check happy. */
3605 spin_lock_irq(&dev_priv->irq_lock);
3606 if (dev_priv->display_irqs_enabled)
3607 valleyview_display_irqs_uninstall(dev_priv);
3608 spin_unlock_irq(&dev_priv->irq_lock);
3609
3610 vlv_display_irq_reset(dev_priv);
3611
3612 dev_priv->irq_mask = 0;
3613}
3614
3872static void valleyview_irq_uninstall(struct drm_device *dev) 3615static void valleyview_irq_uninstall(struct drm_device *dev)
3873{ 3616{
3874 struct drm_i915_private *dev_priv = dev->dev_private; 3617 struct drm_i915_private *dev_priv = dev->dev_private;
3875 unsigned long irqflags;
3876 int pipe;
3877 3618
3878 if (!dev_priv) 3619 if (!dev_priv)
3879 return; 3620 return;
3880 3621
3881 I915_WRITE(VLV_MASTER_IER, 0); 3622 I915_WRITE(VLV_MASTER_IER, 0);
3882 3623
3883 for_each_pipe(dev_priv, pipe) 3624 gen5_gt_irq_reset(dev);
3884 I915_WRITE(PIPESTAT(pipe), 0xffff);
3885 3625
3886 I915_WRITE(HWSTAM, 0xffffffff); 3626 I915_WRITE(HWSTAM, 0xffffffff);
3887 I915_WRITE(PORT_HOTPLUG_EN, 0);
3888 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3889
3890 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3891 if (dev_priv->display_irqs_enabled)
3892 valleyview_display_irqs_uninstall(dev_priv);
3893 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3894 3627
3895 dev_priv->irq_mask = 0; 3628 vlv_display_irq_uninstall(dev_priv);
3896
3897 I915_WRITE(VLV_IIR, 0xffffffff);
3898 I915_WRITE(VLV_IMR, 0xffffffff);
3899 I915_WRITE(VLV_IER, 0x0);
3900 POSTING_READ(VLV_IER);
3901} 3629}
3902 3630
3903static void cherryview_irq_uninstall(struct drm_device *dev) 3631static void cherryview_irq_uninstall(struct drm_device *dev)
3904{ 3632{
3905 struct drm_i915_private *dev_priv = dev->dev_private; 3633 struct drm_i915_private *dev_priv = dev->dev_private;
3906 int pipe;
3907 3634
3908 if (!dev_priv) 3635 if (!dev_priv)
3909 return; 3636 return;
@@ -3911,44 +3638,11 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
3911 I915_WRITE(GEN8_MASTER_IRQ, 0); 3638 I915_WRITE(GEN8_MASTER_IRQ, 0);
3912 POSTING_READ(GEN8_MASTER_IRQ); 3639 POSTING_READ(GEN8_MASTER_IRQ);
3913 3640
3914#define GEN8_IRQ_FINI_NDX(type, which) \ 3641 gen8_gt_irq_reset(dev_priv);
3915do { \
3916 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3917 I915_WRITE(GEN8_##type##_IER(which), 0); \
3918 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3919 POSTING_READ(GEN8_##type##_IIR(which)); \
3920 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3921} while (0)
3922
3923#define GEN8_IRQ_FINI(type) \
3924do { \
3925 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3926 I915_WRITE(GEN8_##type##_IER, 0); \
3927 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3928 POSTING_READ(GEN8_##type##_IIR); \
3929 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3930} while (0)
3931
3932 GEN8_IRQ_FINI_NDX(GT, 0);
3933 GEN8_IRQ_FINI_NDX(GT, 1);
3934 GEN8_IRQ_FINI_NDX(GT, 2);
3935 GEN8_IRQ_FINI_NDX(GT, 3);
3936
3937 GEN8_IRQ_FINI(PCU);
3938
3939#undef GEN8_IRQ_FINI
3940#undef GEN8_IRQ_FINI_NDX
3941
3942 I915_WRITE(PORT_HOTPLUG_EN, 0);
3943 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3944 3642
3945 for_each_pipe(dev_priv, pipe) 3643 GEN5_IRQ_RESET(GEN8_PCU_);
3946 I915_WRITE(PIPESTAT(pipe), 0xffff);
3947 3644
3948 I915_WRITE(VLV_IMR, 0xffffffff); 3645 vlv_display_irq_uninstall(dev_priv);
3949 I915_WRITE(VLV_IER, 0x0);
3950 I915_WRITE(VLV_IIR, 0xffffffff);
3951 POSTING_READ(VLV_IIR);
3952} 3646}
3953 3647
3954static void ironlake_irq_uninstall(struct drm_device *dev) 3648static void ironlake_irq_uninstall(struct drm_device *dev)
@@ -3976,7 +3670,6 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
3976static int i8xx_irq_postinstall(struct drm_device *dev) 3670static int i8xx_irq_postinstall(struct drm_device *dev)
3977{ 3671{
3978 struct drm_i915_private *dev_priv = dev->dev_private; 3672 struct drm_i915_private *dev_priv = dev->dev_private;
3979 unsigned long irqflags;
3980 3673
3981 I915_WRITE16(EMR, 3674 I915_WRITE16(EMR,
3982 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3675 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -3999,10 +3692,10 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
3999 3692
4000 /* Interrupt setup is already guaranteed to be single-threaded, this is 3693 /* Interrupt setup is already guaranteed to be single-threaded, this is
4001 * just to make the assert_spin_locked check happy. */ 3694 * just to make the assert_spin_locked check happy. */
4002 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3695 spin_lock_irq(&dev_priv->irq_lock);
4003 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 3696 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4004 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 3697 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4005 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3698 spin_unlock_irq(&dev_priv->irq_lock);
4006 3699
4007 return 0; 3700 return 0;
4008} 3701}
@@ -4047,7 +3740,6 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4047 struct drm_i915_private *dev_priv = dev->dev_private; 3740 struct drm_i915_private *dev_priv = dev->dev_private;
4048 u16 iir, new_iir; 3741 u16 iir, new_iir;
4049 u32 pipe_stats[2]; 3742 u32 pipe_stats[2];
4050 unsigned long irqflags;
4051 int pipe; 3743 int pipe;
4052 u16 flip_mask = 3744 u16 flip_mask =
4053 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3745 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
@@ -4063,11 +3755,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4063 * It doesn't set the bit in iir again, but it still produces 3755 * It doesn't set the bit in iir again, but it still produces
4064 * interrupts (for non-MSI). 3756 * interrupts (for non-MSI).
4065 */ 3757 */
4066 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3758 spin_lock(&dev_priv->irq_lock);
4067 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3759 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4068 i915_handle_error(dev, false, 3760 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4069 "Command parser error, iir 0x%08x",
4070 iir);
4071 3761
4072 for_each_pipe(dev_priv, pipe) { 3762 for_each_pipe(dev_priv, pipe) {
4073 int reg = PIPESTAT(pipe); 3763 int reg = PIPESTAT(pipe);
@@ -4079,13 +3769,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4079 if (pipe_stats[pipe] & 0x8000ffff) 3769 if (pipe_stats[pipe] & 0x8000ffff)
4080 I915_WRITE(reg, pipe_stats[pipe]); 3770 I915_WRITE(reg, pipe_stats[pipe]);
4081 } 3771 }
4082 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3772 spin_unlock(&dev_priv->irq_lock);
4083 3773
4084 I915_WRITE16(IIR, iir & ~flip_mask); 3774 I915_WRITE16(IIR, iir & ~flip_mask);
4085 new_iir = I915_READ16(IIR); /* Flush posted writes */ 3775 new_iir = I915_READ16(IIR); /* Flush posted writes */
4086 3776
4087 i915_update_dri1_breadcrumb(dev);
4088
4089 if (iir & I915_USER_INTERRUPT) 3777 if (iir & I915_USER_INTERRUPT)
4090 notify_ring(dev, &dev_priv->ring[RCS]); 3778 notify_ring(dev, &dev_priv->ring[RCS]);
4091 3779
@@ -4101,9 +3789,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4101 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3789 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4102 i9xx_pipe_crc_irq_handler(dev, pipe); 3790 i9xx_pipe_crc_irq_handler(dev, pipe);
4103 3791
4104 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3792 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4105 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3793 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4106 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 3794 pipe);
4107 } 3795 }
4108 3796
4109 iir = new_iir; 3797 iir = new_iir;
@@ -4149,7 +3837,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
4149{ 3837{
4150 struct drm_i915_private *dev_priv = dev->dev_private; 3838 struct drm_i915_private *dev_priv = dev->dev_private;
4151 u32 enable_mask; 3839 u32 enable_mask;
4152 unsigned long irqflags;
4153 3840
4154 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3841 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4155 3842
@@ -4187,10 +3874,10 @@ static int i915_irq_postinstall(struct drm_device *dev)
4187 3874
4188 /* Interrupt setup is already guaranteed to be single-threaded, this is 3875 /* Interrupt setup is already guaranteed to be single-threaded, this is
4189 * just to make the assert_spin_locked check happy. */ 3876 * just to make the assert_spin_locked check happy. */
4190 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3877 spin_lock_irq(&dev_priv->irq_lock);
4191 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 3878 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4192 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 3879 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4193 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3880 spin_unlock_irq(&dev_priv->irq_lock);
4194 3881
4195 return 0; 3882 return 0;
4196} 3883}
@@ -4234,7 +3921,6 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4234 struct drm_device *dev = arg; 3921 struct drm_device *dev = arg;
4235 struct drm_i915_private *dev_priv = dev->dev_private; 3922 struct drm_i915_private *dev_priv = dev->dev_private;
4236 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 3923 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4237 unsigned long irqflags;
4238 u32 flip_mask = 3924 u32 flip_mask =
4239 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3925 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4240 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3926 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
@@ -4250,11 +3936,9 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4250 * It doesn't set the bit in iir again, but it still produces 3936 * It doesn't set the bit in iir again, but it still produces
4251 * interrupts (for non-MSI). 3937 * interrupts (for non-MSI).
4252 */ 3938 */
4253 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3939 spin_lock(&dev_priv->irq_lock);
4254 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3940 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4255 i915_handle_error(dev, false, 3941 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4256 "Command parser error, iir 0x%08x",
4257 iir);
4258 3942
4259 for_each_pipe(dev_priv, pipe) { 3943 for_each_pipe(dev_priv, pipe) {
4260 int reg = PIPESTAT(pipe); 3944 int reg = PIPESTAT(pipe);
@@ -4266,7 +3950,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4266 irq_received = true; 3950 irq_received = true;
4267 } 3951 }
4268 } 3952 }
4269 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3953 spin_unlock(&dev_priv->irq_lock);
4270 3954
4271 if (!irq_received) 3955 if (!irq_received)
4272 break; 3956 break;
@@ -4297,9 +3981,9 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4297 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3981 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4298 i9xx_pipe_crc_irq_handler(dev, pipe); 3982 i9xx_pipe_crc_irq_handler(dev, pipe);
4299 3983
4300 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3984 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4301 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3985 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4302 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 3986 pipe);
4303 } 3987 }
4304 3988
4305 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 3989 if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -4324,8 +4008,6 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4324 iir = new_iir; 4008 iir = new_iir;
4325 } while (iir & ~flip_mask); 4009 } while (iir & ~flip_mask);
4326 4010
4327 i915_update_dri1_breadcrumb(dev);
4328
4329 return ret; 4011 return ret;
4330} 4012}
4331 4013
@@ -4372,7 +4054,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
4372 struct drm_i915_private *dev_priv = dev->dev_private; 4054 struct drm_i915_private *dev_priv = dev->dev_private;
4373 u32 enable_mask; 4055 u32 enable_mask;
4374 u32 error_mask; 4056 u32 error_mask;
4375 unsigned long irqflags;
4376 4057
4377 /* Unmask the interrupts that we always want on. */ 4058 /* Unmask the interrupts that we always want on. */
4378 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | 4059 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
@@ -4393,11 +4074,11 @@ static int i965_irq_postinstall(struct drm_device *dev)
4393 4074
4394 /* Interrupt setup is already guaranteed to be single-threaded, this is 4075 /* Interrupt setup is already guaranteed to be single-threaded, this is
4395 * just to make the assert_spin_locked check happy. */ 4076 * just to make the assert_spin_locked check happy. */
4396 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 4077 spin_lock_irq(&dev_priv->irq_lock);
4397 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 4078 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4398 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 4079 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4399 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 4080 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4400 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4081 spin_unlock_irq(&dev_priv->irq_lock);
4401 4082
4402 /* 4083 /*
4403 * Enable some error detection, note the instruction error mask 4084 * Enable some error detection, note the instruction error mask
@@ -4462,7 +4143,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4462 struct drm_i915_private *dev_priv = dev->dev_private; 4143 struct drm_i915_private *dev_priv = dev->dev_private;
4463 u32 iir, new_iir; 4144 u32 iir, new_iir;
4464 u32 pipe_stats[I915_MAX_PIPES]; 4145 u32 pipe_stats[I915_MAX_PIPES];
4465 unsigned long irqflags;
4466 int ret = IRQ_NONE, pipe; 4146 int ret = IRQ_NONE, pipe;
4467 u32 flip_mask = 4147 u32 flip_mask =
4468 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 4148 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
@@ -4479,11 +4159,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4479 * It doesn't set the bit in iir again, but it still produces 4159 * It doesn't set the bit in iir again, but it still produces
4480 * interrupts (for non-MSI). 4160 * interrupts (for non-MSI).
4481 */ 4161 */
4482 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 4162 spin_lock(&dev_priv->irq_lock);
4483 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 4163 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4484 i915_handle_error(dev, false, 4164 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4485 "Command parser error, iir 0x%08x",
4486 iir);
4487 4165
4488 for_each_pipe(dev_priv, pipe) { 4166 for_each_pipe(dev_priv, pipe) {
4489 int reg = PIPESTAT(pipe); 4167 int reg = PIPESTAT(pipe);
@@ -4497,7 +4175,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4497 irq_received = true; 4175 irq_received = true;
4498 } 4176 }
4499 } 4177 }
4500 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4178 spin_unlock(&dev_priv->irq_lock);
4501 4179
4502 if (!irq_received) 4180 if (!irq_received)
4503 break; 4181 break;
@@ -4527,9 +4205,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4527 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 4205 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4528 i9xx_pipe_crc_irq_handler(dev, pipe); 4206 i9xx_pipe_crc_irq_handler(dev, pipe);
4529 4207
4530 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 4208 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4531 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 4209 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4532 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4533 } 4210 }
4534 4211
4535 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 4212 if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -4556,8 +4233,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4556 iir = new_iir; 4233 iir = new_iir;
4557 } 4234 }
4558 4235
4559 i915_update_dri1_breadcrumb(dev);
4560
4561 return ret; 4236 return ret;
4562} 4237}
4563 4238
@@ -4584,19 +4259,18 @@ static void i965_irq_uninstall(struct drm_device * dev)
4584 I915_WRITE(IIR, I915_READ(IIR)); 4259 I915_WRITE(IIR, I915_READ(IIR));
4585} 4260}
4586 4261
4587static void intel_hpd_irq_reenable(struct work_struct *work) 4262static void intel_hpd_irq_reenable_work(struct work_struct *work)
4588{ 4263{
4589 struct drm_i915_private *dev_priv = 4264 struct drm_i915_private *dev_priv =
4590 container_of(work, typeof(*dev_priv), 4265 container_of(work, typeof(*dev_priv),
4591 hotplug_reenable_work.work); 4266 hotplug_reenable_work.work);
4592 struct drm_device *dev = dev_priv->dev; 4267 struct drm_device *dev = dev_priv->dev;
4593 struct drm_mode_config *mode_config = &dev->mode_config; 4268 struct drm_mode_config *mode_config = &dev->mode_config;
4594 unsigned long irqflags;
4595 int i; 4269 int i;
4596 4270
4597 intel_runtime_pm_get(dev_priv); 4271 intel_runtime_pm_get(dev_priv);
4598 4272
4599 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 4273 spin_lock_irq(&dev_priv->irq_lock);
4600 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { 4274 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4601 struct drm_connector *connector; 4275 struct drm_connector *connector;
4602 4276
@@ -4620,14 +4294,21 @@ static void intel_hpd_irq_reenable(struct work_struct *work)
4620 } 4294 }
4621 if (dev_priv->display.hpd_irq_setup) 4295 if (dev_priv->display.hpd_irq_setup)
4622 dev_priv->display.hpd_irq_setup(dev); 4296 dev_priv->display.hpd_irq_setup(dev);
4623 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4297 spin_unlock_irq(&dev_priv->irq_lock);
4624 4298
4625 intel_runtime_pm_put(dev_priv); 4299 intel_runtime_pm_put(dev_priv);
4626} 4300}
4627 4301
4628void intel_irq_init(struct drm_device *dev) 4302/**
4303 * intel_irq_init - initializes irq support
4304 * @dev_priv: i915 device instance
4305 *
4306 * This function initializes all the irq support including work items, timers
4307 * and all the vtables. It does not setup the interrupt itself though.
4308 */
4309void intel_irq_init(struct drm_i915_private *dev_priv)
4629{ 4310{
4630 struct drm_i915_private *dev_priv = dev->dev_private; 4311 struct drm_device *dev = dev_priv->dev;
4631 4312
4632 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 4313 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4633 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); 4314 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
@@ -4636,7 +4317,7 @@ void intel_irq_init(struct drm_device *dev)
4636 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); 4317 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4637 4318
4638 /* Let's track the enabled rps events */ 4319 /* Let's track the enabled rps events */
4639 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) 4320 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4640 /* WaGsvRC0ResidencyMethod:vlv */ 4321 /* WaGsvRC0ResidencyMethod:vlv */
4641 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; 4322 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4642 else 4323 else
@@ -4646,17 +4327,14 @@ void intel_irq_init(struct drm_device *dev)
4646 i915_hangcheck_elapsed, 4327 i915_hangcheck_elapsed,
4647 (unsigned long) dev); 4328 (unsigned long) dev);
4648 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, 4329 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4649 intel_hpd_irq_reenable); 4330 intel_hpd_irq_reenable_work);
4650 4331
4651 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); 4332 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4652 4333
4653 /* Haven't installed the IRQ handler yet */ 4334 if (IS_GEN2(dev_priv)) {
4654 dev_priv->pm._irqs_disabled = true;
4655
4656 if (IS_GEN2(dev)) {
4657 dev->max_vblank_count = 0; 4335 dev->max_vblank_count = 0;
4658 dev->driver->get_vblank_counter = i8xx_get_vblank_counter; 4336 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4659 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 4337 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4660 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 4338 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4661 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 4339 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4662 } else { 4340 } else {
@@ -4669,7 +4347,7 @@ void intel_irq_init(struct drm_device *dev)
4669 * Gen2 doesn't have a hardware frame counter and so depends on 4347 * Gen2 doesn't have a hardware frame counter and so depends on
4670 * vblank interrupts to produce sane vblank seuquence numbers. 4348 * vblank interrupts to produce sane vblank seuquence numbers.
4671 */ 4349 */
4672 if (!IS_GEN2(dev)) 4350 if (!IS_GEN2(dev_priv))
4673 dev->vblank_disable_immediate = true; 4351 dev->vblank_disable_immediate = true;
4674 4352
4675 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 4353 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
@@ -4677,7 +4355,7 @@ void intel_irq_init(struct drm_device *dev)
4677 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 4355 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4678 } 4356 }
4679 4357
4680 if (IS_CHERRYVIEW(dev)) { 4358 if (IS_CHERRYVIEW(dev_priv)) {
4681 dev->driver->irq_handler = cherryview_irq_handler; 4359 dev->driver->irq_handler = cherryview_irq_handler;
4682 dev->driver->irq_preinstall = cherryview_irq_preinstall; 4360 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4683 dev->driver->irq_postinstall = cherryview_irq_postinstall; 4361 dev->driver->irq_postinstall = cherryview_irq_postinstall;
@@ -4685,7 +4363,7 @@ void intel_irq_init(struct drm_device *dev)
4685 dev->driver->enable_vblank = valleyview_enable_vblank; 4363 dev->driver->enable_vblank = valleyview_enable_vblank;
4686 dev->driver->disable_vblank = valleyview_disable_vblank; 4364 dev->driver->disable_vblank = valleyview_disable_vblank;
4687 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 4365 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4688 } else if (IS_VALLEYVIEW(dev)) { 4366 } else if (IS_VALLEYVIEW(dev_priv)) {
4689 dev->driver->irq_handler = valleyview_irq_handler; 4367 dev->driver->irq_handler = valleyview_irq_handler;
4690 dev->driver->irq_preinstall = valleyview_irq_preinstall; 4368 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4691 dev->driver->irq_postinstall = valleyview_irq_postinstall; 4369 dev->driver->irq_postinstall = valleyview_irq_postinstall;
@@ -4693,7 +4371,7 @@ void intel_irq_init(struct drm_device *dev)
4693 dev->driver->enable_vblank = valleyview_enable_vblank; 4371 dev->driver->enable_vblank = valleyview_enable_vblank;
4694 dev->driver->disable_vblank = valleyview_disable_vblank; 4372 dev->driver->disable_vblank = valleyview_disable_vblank;
4695 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 4373 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4696 } else if (IS_GEN8(dev)) { 4374 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4697 dev->driver->irq_handler = gen8_irq_handler; 4375 dev->driver->irq_handler = gen8_irq_handler;
4698 dev->driver->irq_preinstall = gen8_irq_reset; 4376 dev->driver->irq_preinstall = gen8_irq_reset;
4699 dev->driver->irq_postinstall = gen8_irq_postinstall; 4377 dev->driver->irq_postinstall = gen8_irq_postinstall;
@@ -4710,12 +4388,12 @@ void intel_irq_init(struct drm_device *dev)
4710 dev->driver->disable_vblank = ironlake_disable_vblank; 4388 dev->driver->disable_vblank = ironlake_disable_vblank;
4711 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; 4389 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4712 } else { 4390 } else {
4713 if (INTEL_INFO(dev)->gen == 2) { 4391 if (INTEL_INFO(dev_priv)->gen == 2) {
4714 dev->driver->irq_preinstall = i8xx_irq_preinstall; 4392 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4715 dev->driver->irq_postinstall = i8xx_irq_postinstall; 4393 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4716 dev->driver->irq_handler = i8xx_irq_handler; 4394 dev->driver->irq_handler = i8xx_irq_handler;
4717 dev->driver->irq_uninstall = i8xx_irq_uninstall; 4395 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4718 } else if (INTEL_INFO(dev)->gen == 3) { 4396 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4719 dev->driver->irq_preinstall = i915_irq_preinstall; 4397 dev->driver->irq_preinstall = i915_irq_preinstall;
4720 dev->driver->irq_postinstall = i915_irq_postinstall; 4398 dev->driver->irq_postinstall = i915_irq_postinstall;
4721 dev->driver->irq_uninstall = i915_irq_uninstall; 4399 dev->driver->irq_uninstall = i915_irq_uninstall;
@@ -4733,12 +4411,23 @@ void intel_irq_init(struct drm_device *dev)
4733 } 4411 }
4734} 4412}
4735 4413
4736void intel_hpd_init(struct drm_device *dev) 4414/**
4415 * intel_hpd_init - initializes and enables hpd support
4416 * @dev_priv: i915 device instance
4417 *
4418 * This function enables the hotplug support. It requires that interrupts have
4419 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4420 * poll request can run concurrently to other code, so locking rules must be
4421 * obeyed.
4422 *
4423 * This is a separate step from interrupt enabling to simplify the locking rules
4424 * in the driver load and resume code.
4425 */
4426void intel_hpd_init(struct drm_i915_private *dev_priv)
4737{ 4427{
4738 struct drm_i915_private *dev_priv = dev->dev_private; 4428 struct drm_device *dev = dev_priv->dev;
4739 struct drm_mode_config *mode_config = &dev->mode_config; 4429 struct drm_mode_config *mode_config = &dev->mode_config;
4740 struct drm_connector *connector; 4430 struct drm_connector *connector;
4741 unsigned long irqflags;
4742 int i; 4431 int i;
4743 4432
4744 for (i = 1; i < HPD_NUM_PINS; i++) { 4433 for (i = 1; i < HPD_NUM_PINS; i++) {
@@ -4756,27 +4445,72 @@ void intel_hpd_init(struct drm_device *dev)
4756 4445
4757 /* Interrupt setup is already guaranteed to be single-threaded, this is 4446 /* Interrupt setup is already guaranteed to be single-threaded, this is
4758 * just to make the assert_spin_locked checks happy. */ 4447 * just to make the assert_spin_locked checks happy. */
4759 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 4448 spin_lock_irq(&dev_priv->irq_lock);
4760 if (dev_priv->display.hpd_irq_setup) 4449 if (dev_priv->display.hpd_irq_setup)
4761 dev_priv->display.hpd_irq_setup(dev); 4450 dev_priv->display.hpd_irq_setup(dev);
4762 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4451 spin_unlock_irq(&dev_priv->irq_lock);
4763} 4452}
4764 4453
4765/* Disable interrupts so we can allow runtime PM. */ 4454/**
4766void intel_runtime_pm_disable_interrupts(struct drm_device *dev) 4455 * intel_irq_install - enables the hardware interrupt
4456 * @dev_priv: i915 device instance
4457 *
4458 * This function enables the hardware interrupt handling, but leaves the hotplug
4459 * handling still disabled. It is called after intel_irq_init().
4460 *
4461 * In the driver load and resume code we need working interrupts in a few places
4462 * but don't want to deal with the hassle of concurrent probe and hotplug
4463 * workers. Hence the split into this two-stage approach.
4464 */
4465int intel_irq_install(struct drm_i915_private *dev_priv)
4767{ 4466{
4768 struct drm_i915_private *dev_priv = dev->dev_private; 4467 /*
4468 * We enable some interrupt sources in our postinstall hooks, so mark
4469 * interrupts as enabled _before_ actually enabling them to avoid
4470 * special cases in our ordering checks.
4471 */
4472 dev_priv->pm.irqs_enabled = true;
4769 4473
4770 dev->driver->irq_uninstall(dev); 4474 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4771 dev_priv->pm._irqs_disabled = true;
4772} 4475}
4773 4476
4774/* Restore interrupts so we can recover from runtime PM. */ 4477/**
4775void intel_runtime_pm_restore_interrupts(struct drm_device *dev) 4478 * intel_irq_uninstall - finilizes all irq handling
4479 * @dev_priv: i915 device instance
4480 *
4481 * This stops interrupt and hotplug handling and unregisters and frees all
4482 * resources acquired in the init functions.
4483 */
4484void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4776{ 4485{
4777 struct drm_i915_private *dev_priv = dev->dev_private; 4486 drm_irq_uninstall(dev_priv->dev);
4487 intel_hpd_cancel_work(dev_priv);
4488 dev_priv->pm.irqs_enabled = false;
4489}
4778 4490
4779 dev_priv->pm._irqs_disabled = false; 4491/**
4780 dev->driver->irq_preinstall(dev); 4492 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4781 dev->driver->irq_postinstall(dev); 4493 * @dev_priv: i915 device instance
4494 *
4495 * This function is used to disable interrupts at runtime, both in the runtime
4496 * pm and the system suspend/resume code.
4497 */
4498void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4499{
4500 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4501 dev_priv->pm.irqs_enabled = false;
4502}
4503
4504/**
4505 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4506 * @dev_priv: i915 device instance
4507 *
4508 * This function is used to enable interrupts at runtime, both in the runtime
4509 * pm and the system suspend/resume code.
4510 */
4511void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4512{
4513 dev_priv->pm.irqs_enabled = true;
4514 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4515 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4782} 4516}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 21:22:28 -0500