1 files changed, 39 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 911bd40ef513..6be940effefd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2683,17 +2683,35 @@ static inline int fence_number(struct drm_i915_private *dev_priv,
         return fence - dev_priv->fence_regs;
 }
 
+static void i915_gem_write_fence__ipi(void *data)
+{
+        wbinvd();
+}
+
 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
                                          struct drm_i915_fence_reg *fence,
                                          bool enable)
 {
-        struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
-        int reg = fence_number(dev_priv, fence);
-
-        i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
+        struct drm_device *dev = obj->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int fence_reg = fence_number(dev_priv, fence);
+
+        /* In order to fully serialize access to the fenced region and
+         * the update to the fence register we need to take extreme
+         * measures on SNB+. In theory, the write to the fence register
+         * flushes all memory transactions before, and coupled with the
+         * mb() placed around the register write we serialise all memory
+         * operations with respect to the changes in the tiler. Yet, on
+         * SNB+ we need to take a step further and emit an explicit wbinvd()
+         * on each processor in order to manually flush all memory
+         * transactions before updating the fence register.
+         */
+        if (HAS_LLC(obj->base.dev))
+                on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
+        i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
 
         if (enable) {
-                obj->fence_reg = reg;
+                obj->fence_reg = fence_reg;
                 fence->obj = obj;
                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
         } else {
@@ -3992,6 +4010,12 @@ i915_gem_init_hw(struct drm_device *dev)
         if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
                 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
 
+        if (HAS_PCH_NOP(dev)) {
+                u32 temp = I915_READ(GEN7_MSG_CTL);
+                temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+                I915_WRITE(GEN7_MSG_CTL, temp);
+        }
+
         i915_gem_l3_remap(dev);
 
         i915_gem_init_swizzling(dev);
@@ -4005,7 +4029,13 @@ i915_gem_init_hw(struct drm_device *dev)
          * contexts before PPGTT.
          */
         i915_gem_context_init(dev);
-        i915_gem_init_ppgtt(dev);
+        if (dev_priv->mm.aliasing_ppgtt) {
+                ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
+                if (ret) {
+                        i915_gem_cleanup_aliasing_ppgtt(dev);
+                        DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
+                }
+        }
 
         return 0;
 }
@@ -4160,7 +4190,9 @@ i915_gem_load(struct drm_device *dev)
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 dev_priv->fence_reg_start = 3;
 
-        if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+        if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
+                dev_priv->num_fence_regs = 32;
+        else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
                 dev_priv->num_fence_regs = 16;
         else
                 dev_priv->num_fence_regs = 8;