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path: root/drivers/gpu/drm/i915/i915_gem.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c19
1 files changed, 16 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fd2b8bdffe3f..876b65cb7629 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1006,7 +1006,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1006 1006
1007 mutex_lock(&dev->struct_mutex); 1007 mutex_lock(&dev->struct_mutex);
1008#if WATCH_BUF 1008#if WATCH_BUF
1009 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n", 1009 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1010 obj, obj->size, read_domains, write_domain); 1010 obj, obj->size, read_domains, write_domain);
1011#endif 1011#endif
1012 if (read_domains & I915_GEM_DOMAIN_GTT) { 1012 if (read_domains & I915_GEM_DOMAIN_GTT) {
@@ -1050,7 +1050,7 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1050 } 1050 }
1051 1051
1052#if WATCH_BUF 1052#if WATCH_BUF
1053 DRM_INFO("%s: sw_finish %d (%p %d)\n", 1053 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1054 __func__, args->handle, obj, obj->size); 1054 __func__, args->handle, obj, obj->size);
1055#endif 1055#endif
1056 obj_priv = obj->driver_private; 1056 obj_priv = obj->driver_private;
@@ -2423,7 +2423,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2423 } 2423 }
2424 2424
2425#if WATCH_BUF 2425#if WATCH_BUF
2426 DRM_INFO("Binding object of size %d at 0x%08x\n", 2426 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2427 obj->size, obj_priv->gtt_offset); 2427 obj->size, obj_priv->gtt_offset);
2428#endif 2428#endif
2429 ret = i915_gem_object_get_pages(obj); 2429 ret = i915_gem_object_get_pages(obj);
@@ -4227,6 +4227,7 @@ i915_gem_lastclose(struct drm_device *dev)
4227void 4227void
4228i915_gem_load(struct drm_device *dev) 4228i915_gem_load(struct drm_device *dev)
4229{ 4229{
4230 int i;
4230 drm_i915_private_t *dev_priv = dev->dev_private; 4231 drm_i915_private_t *dev_priv = dev->dev_private;
4231 4232
4232 spin_lock_init(&dev_priv->mm.active_list_lock); 4233 spin_lock_init(&dev_priv->mm.active_list_lock);
@@ -4246,6 +4247,18 @@ i915_gem_load(struct drm_device *dev)
4246 else 4247 else
4247 dev_priv->num_fence_regs = 8; 4248 dev_priv->num_fence_regs = 8;
4248 4249
4250 /* Initialize fence registers to zero */
4251 if (IS_I965G(dev)) {
4252 for (i = 0; i < 16; i++)
4253 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4254 } else {
4255 for (i = 0; i < 8; i++)
4256 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4257 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4258 for (i = 0; i < 8; i++)
4259 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4260 }
4261
4249 i915_gem_detect_bit_6_swizzle(dev); 4262 i915_gem_detect_bit_6_swizzle(dev);
4250} 4263}
4251 4264