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path: root/drivers/gpu/drm/i915/i915_gem.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 38490cdf2d9f..cfbcf7ef567e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3494,9 +3494,9 @@ void i915_gem_init_swizzling(struct drm_device *dev)
3494 3494
3495 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); 3495 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3496 if (IS_GEN6(dev)) 3496 if (IS_GEN6(dev))
3497 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); 3497 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3498 else 3498 else
3499 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); 3499 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3500} 3500}
3501 3501
3502void i915_gem_init_ppgtt(struct drm_device *dev) 3502void i915_gem_init_ppgtt(struct drm_device *dev)
@@ -3545,7 +3545,7 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
3545 ecochk = I915_READ(GAM_ECOCHK); 3545 ecochk = I915_READ(GAM_ECOCHK);
3546 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | 3546 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3547 ECOCHK_PPGTT_CACHE64B); 3547 ECOCHK_PPGTT_CACHE64B);
3548 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); 3548 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3549 } else if (INTEL_INFO(dev)->gen >= 7) { 3549 } else if (INTEL_INFO(dev)->gen >= 7) {
3550 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); 3550 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3551 /* GFX_MODE is per-ring on gen7+ */ 3551 /* GFX_MODE is per-ring on gen7+ */
@@ -3556,7 +3556,7 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
3556 3556
3557 if (INTEL_INFO(dev)->gen >= 7) 3557 if (INTEL_INFO(dev)->gen >= 7)
3558 I915_WRITE(RING_MODE_GEN7(ring), 3558 I915_WRITE(RING_MODE_GEN7(ring),
3559 GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); 3559 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3560 3560
3561 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); 3561 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3562 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); 3562 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);