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path: root/drivers/gpu/drm/i915/i915_drv.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 87f7f88b1030..f69ba390a649 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -132,7 +132,7 @@ enum hpd_pin {
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc)) 133 if ((intel_encoder)->base.crtc == (__crtc))
134 134
135struct intel_pch_pll { 135struct intel_shared_dpll {
136 int refcount; /* count of number of CRTCs sharing this PLL */ 136 int refcount; /* count of number of CRTCs sharing this PLL */
137 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 137 int active; /* count of number of active CRTCs (i.e. DPMS on) */
138 bool on; /* is the PLL actually active? Disabled during modeset */ 138 bool on; /* is the PLL actually active? Disabled during modeset */
@@ -1026,7 +1026,6 @@ typedef struct drm_i915_private {
1026 u32 hpd_event_bits; 1026 u32 hpd_event_bits;
1027 struct timer_list hotplug_reenable_timer; 1027 struct timer_list hotplug_reenable_timer;
1028 1028
1029 int num_pch_pll;
1030 int num_plane; 1029 int num_plane;
1031 1030
1032 unsigned long cfb_size; 1031 unsigned long cfb_size;
@@ -1087,7 +1086,8 @@ typedef struct drm_i915_private {
1087 struct drm_crtc *pipe_to_crtc_mapping[3]; 1086 struct drm_crtc *pipe_to_crtc_mapping[3];
1088 wait_queue_head_t pending_flip_queue; 1087 wait_queue_head_t pending_flip_queue;
1089 1088
1090 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 1089 int num_shared_dpll;
1090 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1091 struct intel_ddi_plls ddi_plls; 1091 struct intel_ddi_plls ddi_plls;
1092 1092
1093 /* Reclocking support */ 1093 /* Reclocking support */