1 files changed, 24 insertions, 13 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06a37f4fd74b..554bef7a3b9c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -107,6 +107,7 @@ struct opregion_header;
 struct opregion_acpi;
 struct opregion_swsci;
 struct opregion_asle;
+struct drm_i915_private;
 
 struct intel_opregion {
         struct opregion_header *header;
@@ -126,6 +127,9 @@ struct drm_i915_master_private {
         struct _drm_i915_sarea *sarea_priv;
 };
 #define I915_FENCE_REG_NONE -1
+#define I915_MAX_NUM_FENCES 16
+/* 16 fences + sign bit for FENCE_REG_NONE */
+#define I915_MAX_NUM_FENCE_BITS 5
 
 struct drm_i915_fence_reg {
         struct list_head lru_list;
@@ -168,7 +172,7 @@ struct drm_i915_error_state {
         u32 instdone1;
         u32 seqno;
         u64 bbaddr;
-        u64 fence[16];
+        u64 fence[I915_MAX_NUM_FENCES];
         struct timeval time;
         struct drm_i915_error_object {
                 int page_count;
@@ -182,7 +186,7 @@ struct drm_i915_error_state {
                 u32 gtt_offset;
                 u32 read_domains;
                 u32 write_domain;
-                s32 fence_reg:5;
+                s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
                 s32 pinned:2;
                 u32 tiling:2;
                 u32 dirty:1;
@@ -218,6 +222,8 @@ struct drm_i915_display_funcs {
                           struct drm_i915_gem_object *obj);
         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                             int x, int y);
+        void (*force_wake_get)(struct drm_i915_private *dev_priv);
+        void (*force_wake_put)(struct drm_i915_private *dev_priv);
         /* clock updates for mode set */
         /* cursor updates */
         /* render clock increase/decrease */
@@ -375,7 +381,7 @@ typedef struct drm_i915_private {
         struct notifier_block lid_notifier;
 
         int crt_ddc_pin;
-        struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
+        struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
@@ -506,7 +512,7 @@ typedef struct drm_i915_private {
         u8 saveAR[21];
         u8 saveDACMASK;
         u8 saveCR[37];
-        uint64_t saveFENCE[16];
+        uint64_t saveFENCE[I915_MAX_NUM_FENCES];
         u32 saveCURACNTR;
         u32 saveCURAPOS;
         u32 saveCURABASE;
@@ -707,6 +713,7 @@ typedef struct drm_i915_private {
 
         u64 last_count1;
         unsigned long last_time1;
+        unsigned long chipset_power;
         u64 last_count2;
         struct timespec last_time2;
         unsigned long gfx_power;
@@ -777,10 +784,8 @@ struct drm_i915_gem_object {
          * Fence register bits (if any) for this object.  Will be set
          * as needed when mapped into the GTT.
          * Protected by dev->struct_mutex.
-         *
-         * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
          */
-        signed int fence_reg:5;
+        signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
 
         /**
          * Advice: are the backing pages purgeable?
@@ -997,12 +1002,12 @@ extern int i915_max_ioctl;
 extern unsigned int i915_fbpercrtc __always_unused;
 extern int i915_panel_ignore_lid __read_mostly;
 extern unsigned int i915_powersave __read_mostly;
-extern unsigned int i915_semaphores __read_mostly;
+extern int i915_semaphores __read_mostly;
 extern unsigned int i915_lvds_downclock __read_mostly;
-extern unsigned int i915_panel_use_ssc __read_mostly;
+extern int i915_panel_use_ssc __read_mostly;
 extern int i915_vbt_sdvo_panel_type __read_mostly;
-extern unsigned int i915_enable_rc6 __read_mostly;
-extern unsigned int i915_enable_fbc __read_mostly;
+extern int i915_enable_rc6 __read_mostly;
+extern int i915_enable_fbc __read_mostly;
 extern bool i915_enable_hangcheck __read_mostly;
 
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
@@ -1307,6 +1312,11 @@ extern void gen6_set_rps(struct drm_device *dev, u8 val);
 extern void intel_detect_pch(struct drm_device *dev);
 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
 
+extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
+extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
+extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
+extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
+
 /* overlay */
 #ifdef CONFIG_DEBUG_FS
 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
@@ -1351,8 +1361,9 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
 /* We give fast paths for the really cool registers */
 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
         (((dev_priv)->info->gen >= 6) && \
-        ((reg) < 0x40000) && \
-        ((reg) != FORCEWAKE))
+         ((reg) < 0x40000) &&            \
+         ((reg) != FORCEWAKE) &&         \
+         ((reg) != ECOBUS))
 
 #define __i915_read(x, y) \
         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);