1 files changed, 50 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c5df2234418d..a725f6591192 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -296,6 +296,13 @@ typedef struct drm_i915_private {
         u32 saveVBLANK_A;
         u32 saveVSYNC_A;
         u32 saveBCLRPAT_A;
+        u32 saveTRANSACONF;
+        u32 saveTRANS_HTOTAL_A;
+        u32 saveTRANS_HBLANK_A;
+        u32 saveTRANS_HSYNC_A;
+        u32 saveTRANS_VTOTAL_A;
+        u32 saveTRANS_VBLANK_A;
+        u32 saveTRANS_VSYNC_A;
         u32 savePIPEASTAT;
         u32 saveDSPASTRIDE;
         u32 saveDSPASIZE;
@@ -304,8 +311,11 @@ typedef struct drm_i915_private {
         u32 saveDSPASURF;
         u32 saveDSPATILEOFF;
         u32 savePFIT_PGM_RATIOS;
+        u32 saveBLC_HIST_CTL;
         u32 saveBLC_PWM_CTL;
         u32 saveBLC_PWM_CTL2;
+        u32 saveBLC_CPU_PWM_CTL;
+        u32 saveBLC_CPU_PWM_CTL2;
         u32 saveFPB0;
         u32 saveFPB1;
         u32 saveDPLL_B;
@@ -317,6 +327,13 @@ typedef struct drm_i915_private {
         u32 saveVBLANK_B;
         u32 saveVSYNC_B;
         u32 saveBCLRPAT_B;
+        u32 saveTRANSBCONF;
+        u32 saveTRANS_HTOTAL_B;
+        u32 saveTRANS_HBLANK_B;
+        u32 saveTRANS_HSYNC_B;
+        u32 saveTRANS_VTOTAL_B;
+        u32 saveTRANS_VBLANK_B;
+        u32 saveTRANS_VSYNC_B;
         u32 savePIPEBSTAT;
         u32 saveDSPBSTRIDE;
         u32 saveDSPBSIZE;
@@ -342,6 +359,7 @@ typedef struct drm_i915_private {
         u32 savePFIT_CONTROL;
         u32 save_palette_a[256];
         u32 save_palette_b[256];
+        u32 saveDPFC_CB_BASE;
         u32 saveFBC_CFB_BASE;
         u32 saveFBC_LL_BASE;
         u32 saveFBC_CONTROL;
@@ -349,6 +367,12 @@ typedef struct drm_i915_private {
         u32 saveIER;
         u32 saveIIR;
         u32 saveIMR;
+        u32 saveDEIER;
+        u32 saveDEIMR;
+        u32 saveGTIER;
+        u32 saveGTIMR;
+        u32 saveFDI_RXA_IMR;
+        u32 saveFDI_RXB_IMR;
         u32 saveCACHE_MODE_0;
         u32 saveD_STATE;
         u32 saveDSPCLK_GATE_D;
@@ -382,6 +406,26 @@ typedef struct drm_i915_private {
         u32 savePIPEB_DP_LINK_M;
         u32 savePIPEA_DP_LINK_N;
         u32 savePIPEB_DP_LINK_N;
+        u32 saveFDI_RXA_CTL;
+        u32 saveFDI_TXA_CTL;
+        u32 saveFDI_RXB_CTL;
+        u32 saveFDI_TXB_CTL;
+        u32 savePFA_CTL_1;
+        u32 savePFB_CTL_1;
+        u32 savePFA_WIN_SZ;
+        u32 savePFB_WIN_SZ;
+        u32 savePFA_WIN_POS;
+        u32 savePFB_WIN_POS;
+        u32 savePCH_DREF_CONTROL;
+        u32 saveDISP_ARB_CTL;
+        u32 savePIPEA_DATA_M1;
+        u32 savePIPEA_DATA_N1;
+        u32 savePIPEA_LINK_M1;
+        u32 savePIPEA_LINK_N1;
+        u32 savePIPEB_DATA_M1;
+        u32 savePIPEB_DATA_N1;
+        u32 savePIPEB_LINK_M1;
+        u32 savePIPEB_LINK_N1;
 
         struct {
                 struct drm_mm gtt_space;
@@ -492,6 +536,8 @@ typedef struct drm_i915_private {
                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
         } mm;
         struct sdvo_device_mapping sdvo_mappings[2];
+        /* indicate whether the LVDS_BORDER should be enabled or not */
+        unsigned int lvds_border_bits;
 
         /* Reclocking support */
         bool render_reclock_avail;
@@ -981,7 +1027,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
-#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)))
+#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
+                           (IS_I9XX(dev) || IS_GM45(dev)) && \
+                           !IS_IGD(dev) && \
+                           !IS_IGDNG(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)