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path: root/drivers/gpu/drm/i915/i915_drv.h
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-rw-r--r--drivers/gpu/drm/i915/i915_drv.h605
1 files changed, 343 insertions, 262 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 409826da3099..aac1bf332f75 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -89,7 +89,7 @@ struct drm_i915_gem_phys_object {
89 int id; 89 int id;
90 struct page **page_list; 90 struct page **page_list;
91 drm_dma_handle_t *handle; 91 drm_dma_handle_t *handle;
92 struct drm_gem_object *cur_obj; 92 struct drm_i915_gem_object *cur_obj;
93}; 93};
94 94
95struct mem_block { 95struct mem_block {
@@ -124,9 +124,9 @@ struct drm_i915_master_private {
124#define I915_FENCE_REG_NONE -1 124#define I915_FENCE_REG_NONE -1
125 125
126struct drm_i915_fence_reg { 126struct drm_i915_fence_reg {
127 struct drm_gem_object *obj;
128 struct list_head lru_list; 127 struct list_head lru_list;
129 bool gpu; 128 struct drm_i915_gem_object *obj;
129 uint32_t setup_seqno;
130}; 130};
131 131
132struct sdvo_device_mapping { 132struct sdvo_device_mapping {
@@ -139,6 +139,8 @@ struct sdvo_device_mapping {
139 u8 ddc_pin; 139 u8 ddc_pin;
140}; 140};
141 141
142struct intel_display_error_state;
143
142struct drm_i915_error_state { 144struct drm_i915_error_state {
143 u32 eir; 145 u32 eir;
144 u32 pgtbl_er; 146 u32 pgtbl_er;
@@ -148,11 +150,23 @@ struct drm_i915_error_state {
148 u32 ipehr; 150 u32 ipehr;
149 u32 instdone; 151 u32 instdone;
150 u32 acthd; 152 u32 acthd;
153 u32 error; /* gen6+ */
154 u32 bcs_acthd; /* gen6+ blt engine */
155 u32 bcs_ipehr;
156 u32 bcs_ipeir;
157 u32 bcs_instdone;
158 u32 bcs_seqno;
159 u32 vcs_acthd; /* gen6+ bsd engine */
160 u32 vcs_ipehr;
161 u32 vcs_ipeir;
162 u32 vcs_instdone;
163 u32 vcs_seqno;
151 u32 instpm; 164 u32 instpm;
152 u32 instps; 165 u32 instps;
153 u32 instdone1; 166 u32 instdone1;
154 u32 seqno; 167 u32 seqno;
155 u64 bbaddr; 168 u64 bbaddr;
169 u64 fence[16];
156 struct timeval time; 170 struct timeval time;
157 struct drm_i915_error_object { 171 struct drm_i915_error_object {
158 int page_count; 172 int page_count;
@@ -171,9 +185,11 @@ struct drm_i915_error_state {
171 u32 tiling:2; 185 u32 tiling:2;
172 u32 dirty:1; 186 u32 dirty:1;
173 u32 purgeable:1; 187 u32 purgeable:1;
174 } *active_bo; 188 u32 ring:4;
175 u32 active_bo_count; 189 } *active_bo, *pinned_bo;
190 u32 active_bo_count, pinned_bo_count;
176 struct intel_overlay_error_state *overlay; 191 struct intel_overlay_error_state *overlay;
192 struct intel_display_error_state *display;
177}; 193};
178 194
179struct drm_i915_display_funcs { 195struct drm_i915_display_funcs {
@@ -207,7 +223,6 @@ struct intel_device_info {
207 u8 is_broadwater : 1; 223 u8 is_broadwater : 1;
208 u8 is_crestline : 1; 224 u8 is_crestline : 1;
209 u8 has_fbc : 1; 225 u8 has_fbc : 1;
210 u8 has_rc6 : 1;
211 u8 has_pipe_cxsr : 1; 226 u8 has_pipe_cxsr : 1;
212 u8 has_hotplug : 1; 227 u8 has_hotplug : 1;
213 u8 cursor_needs_physical : 1; 228 u8 cursor_needs_physical : 1;
@@ -243,6 +258,7 @@ typedef struct drm_i915_private {
243 const struct intel_device_info *info; 258 const struct intel_device_info *info;
244 259
245 int has_gem; 260 int has_gem;
261 int relative_constants_mode;
246 262
247 void __iomem *regs; 263 void __iomem *regs;
248 264
@@ -253,20 +269,15 @@ typedef struct drm_i915_private {
253 } *gmbus; 269 } *gmbus;
254 270
255 struct pci_dev *bridge_dev; 271 struct pci_dev *bridge_dev;
256 struct intel_ring_buffer render_ring; 272 struct intel_ring_buffer ring[I915_NUM_RINGS];
257 struct intel_ring_buffer bsd_ring;
258 struct intel_ring_buffer blt_ring;
259 uint32_t next_seqno; 273 uint32_t next_seqno;
260 274
261 drm_dma_handle_t *status_page_dmah; 275 drm_dma_handle_t *status_page_dmah;
262 void *seqno_page;
263 dma_addr_t dma_status_page; 276 dma_addr_t dma_status_page;
264 uint32_t counter; 277 uint32_t counter;
265 unsigned int seqno_gfx_addr;
266 drm_local_map_t hws_map; 278 drm_local_map_t hws_map;
267 struct drm_gem_object *seqno_obj; 279 struct drm_i915_gem_object *pwrctx;
268 struct drm_gem_object *pwrctx; 280 struct drm_i915_gem_object *renderctx;
269 struct drm_gem_object *renderctx;
270 281
271 struct resource mch_res; 282 struct resource mch_res;
272 283
@@ -275,25 +286,17 @@ typedef struct drm_i915_private {
275 int front_offset; 286 int front_offset;
276 int current_page; 287 int current_page;
277 int page_flipping; 288 int page_flipping;
278#define I915_DEBUG_READ (1<<0)
279#define I915_DEBUG_WRITE (1<<1)
280 unsigned long debug_flags;
281 289
282 wait_queue_head_t irq_queue;
283 atomic_t irq_received; 290 atomic_t irq_received;
284 /** Protects user_irq_refcount and irq_mask_reg */
285 spinlock_t user_irq_lock;
286 u32 trace_irq_seqno; 291 u32 trace_irq_seqno;
292
293 /* protects the irq masks */
294 spinlock_t irq_lock;
287 /** Cached value of IMR to avoid reads in updating the bitfield */ 295 /** Cached value of IMR to avoid reads in updating the bitfield */
288 u32 irq_mask_reg;
289 u32 pipestat[2]; 296 u32 pipestat[2];
290 /** splitted irq regs for graphics and display engine on Ironlake, 297 u32 irq_mask;
291 irq_mask_reg is still used for display irq. */ 298 u32 gt_irq_mask;
292 u32 gt_irq_mask_reg; 299 u32 pch_irq_mask;
293 u32 gt_irq_enable_reg;
294 u32 de_irq_enable_reg;
295 u32 pch_irq_mask_reg;
296 u32 pch_irq_enable_reg;
297 300
298 u32 hotplug_supported_mask; 301 u32 hotplug_supported_mask;
299 struct work_struct hotplug_work; 302 struct work_struct hotplug_work;
@@ -306,7 +309,7 @@ typedef struct drm_i915_private {
306 int num_pipe; 309 int num_pipe;
307 310
308 /* For hangcheck timer */ 311 /* For hangcheck timer */
309#define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */ 312#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
310 struct timer_list hangcheck_timer; 313 struct timer_list hangcheck_timer;
311 int hangcheck_count; 314 int hangcheck_count;
312 uint32_t last_acthd; 315 uint32_t last_acthd;
@@ -530,23 +533,21 @@ typedef struct drm_i915_private {
530 533
531 struct { 534 struct {
532 /** Bridge to intel-gtt-ko */ 535 /** Bridge to intel-gtt-ko */
533 struct intel_gtt *gtt; 536 const struct intel_gtt *gtt;
534 /** Memory allocator for GTT stolen memory */ 537 /** Memory allocator for GTT stolen memory */
535 struct drm_mm vram; 538 struct drm_mm stolen;
536 /** Memory allocator for GTT */ 539 /** Memory allocator for GTT */
537 struct drm_mm gtt_space; 540 struct drm_mm gtt_space;
541 /** List of all objects in gtt_space. Used to restore gtt
542 * mappings on resume */
543 struct list_head gtt_list;
544 /** End of mappable part of GTT */
545 unsigned long gtt_mappable_end;
538 546
539 struct io_mapping *gtt_mapping; 547 struct io_mapping *gtt_mapping;
540 int gtt_mtrr; 548 int gtt_mtrr;
541 549
542 /** 550 struct shrinker inactive_shrinker;
543 * Membership on list of all loaded devices, used to evict
544 * inactive buffers under memory pressure.
545 *
546 * Modifications should only be done whilst holding the
547 * shrink_list_lock spinlock.
548 */
549 struct list_head shrink_list;
550 551
551 /** 552 /**
552 * List of objects currently involved in rendering. 553 * List of objects currently involved in rendering.
@@ -609,16 +610,6 @@ typedef struct drm_i915_private {
609 struct delayed_work retire_work; 610 struct delayed_work retire_work;
610 611
611 /** 612 /**
612 * Waiting sequence number, if any
613 */
614 uint32_t waiting_gem_seqno;
615
616 /**
617 * Last seq seen at irq time
618 */
619 uint32_t irq_gem_seqno;
620
621 /**
622 * Flag if the X Server, and thus DRM, is not currently in 613 * Flag if the X Server, and thus DRM, is not currently in
623 * control of the device. 614 * control of the device.
624 * 615 *
@@ -645,16 +636,11 @@ typedef struct drm_i915_private {
645 /* storage for physical objects */ 636 /* storage for physical objects */
646 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 637 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
647 638
648 uint32_t flush_rings;
649
650 /* accounting, useful for userland debugging */ 639 /* accounting, useful for userland debugging */
651 size_t object_memory;
652 size_t pin_memory;
653 size_t gtt_memory;
654 size_t gtt_total; 640 size_t gtt_total;
641 size_t mappable_gtt_total;
642 size_t object_memory;
655 u32 object_count; 643 u32 object_count;
656 u32 pin_count;
657 u32 gtt_count;
658 } mm; 644 } mm;
659 struct sdvo_device_mapping sdvo_mappings[2]; 645 struct sdvo_device_mapping sdvo_mappings[2];
660 /* indicate whether the LVDS_BORDER should be enabled or not */ 646 /* indicate whether the LVDS_BORDER should be enabled or not */
@@ -688,14 +674,14 @@ typedef struct drm_i915_private {
688 u8 fmax; 674 u8 fmax;
689 u8 fstart; 675 u8 fstart;
690 676
691 u64 last_count1; 677 u64 last_count1;
692 unsigned long last_time1; 678 unsigned long last_time1;
693 u64 last_count2; 679 u64 last_count2;
694 struct timespec last_time2; 680 struct timespec last_time2;
695 unsigned long gfx_power; 681 unsigned long gfx_power;
696 int c_m; 682 int c_m;
697 int r_t; 683 int r_t;
698 u8 corr; 684 u8 corr;
699 spinlock_t *mchdev_lock; 685 spinlock_t *mchdev_lock;
700 686
701 enum no_fbc_reason no_fbc_reason; 687 enum no_fbc_reason no_fbc_reason;
@@ -709,20 +695,20 @@ typedef struct drm_i915_private {
709 struct intel_fbdev *fbdev; 695 struct intel_fbdev *fbdev;
710} drm_i915_private_t; 696} drm_i915_private_t;
711 697
712/** driver private structure attached to each drm_gem_object */
713struct drm_i915_gem_object { 698struct drm_i915_gem_object {
714 struct drm_gem_object base; 699 struct drm_gem_object base;
715 700
716 /** Current space allocated to this object in the GTT, if any. */ 701 /** Current space allocated to this object in the GTT, if any. */
717 struct drm_mm_node *gtt_space; 702 struct drm_mm_node *gtt_space;
703 struct list_head gtt_list;
718 704
719 /** This object's place on the active/flushing/inactive lists */ 705 /** This object's place on the active/flushing/inactive lists */
720 struct list_head ring_list; 706 struct list_head ring_list;
721 struct list_head mm_list; 707 struct list_head mm_list;
722 /** This object's place on GPU write list */ 708 /** This object's place on GPU write list */
723 struct list_head gpu_write_list; 709 struct list_head gpu_write_list;
724 /** This object's place on eviction list */ 710 /** This object's place in the batchbuffer or on the eviction list */
725 struct list_head evict_list; 711 struct list_head exec_list;
726 712
727 /** 713 /**
728 * This is set if the object is on the active or flushing lists 714 * This is set if the object is on the active or flushing lists
@@ -738,6 +724,12 @@ struct drm_i915_gem_object {
738 unsigned int dirty : 1; 724 unsigned int dirty : 1;
739 725
740 /** 726 /**
727 * This is set if the object has been written to since the last
728 * GPU flush.
729 */
730 unsigned int pending_gpu_write : 1;
731
732 /**
741 * Fence register bits (if any) for this object. Will be set 733 * Fence register bits (if any) for this object. Will be set
742 * as needed when mapped into the GTT. 734 * as needed when mapped into the GTT.
743 * Protected by dev->struct_mutex. 735 * Protected by dev->struct_mutex.
@@ -747,29 +739,15 @@ struct drm_i915_gem_object {
747 signed int fence_reg : 5; 739 signed int fence_reg : 5;
748 740
749 /** 741 /**
750 * Used for checking the object doesn't appear more than once
751 * in an execbuffer object list.
752 */
753 unsigned int in_execbuffer : 1;
754
755 /**
756 * Advice: are the backing pages purgeable? 742 * Advice: are the backing pages purgeable?
757 */ 743 */
758 unsigned int madv : 2; 744 unsigned int madv : 2;
759 745
760 /** 746 /**
761 * Refcount for the pages array. With the current locking scheme, there
762 * are at most two concurrent users: Binding a bo to the gtt and
763 * pwrite/pread using physical addresses. So two bits for a maximum
764 * of two users are enough.
765 */
766 unsigned int pages_refcount : 2;
767#define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
768
769 /**
770 * Current tiling mode for the object. 747 * Current tiling mode for the object.
771 */ 748 */
772 unsigned int tiling_mode : 2; 749 unsigned int tiling_mode : 2;
750 unsigned int tiling_changed : 1;
773 751
774 /** How many users have pinned this object in GTT space. The following 752 /** How many users have pinned this object in GTT space. The following
775 * users can each hold at most one reference: pwrite/pread, pin_ioctl 753 * users can each hold at most one reference: pwrite/pread, pin_ioctl
@@ -783,28 +761,54 @@ struct drm_i915_gem_object {
783 unsigned int pin_count : 4; 761 unsigned int pin_count : 4;
784#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 762#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
785 763
786 /** AGP memory structure for our GTT binding. */ 764 /**
787 DRM_AGP_MEM *agp_mem; 765 * Is the object at the current location in the gtt mappable and
766 * fenceable? Used to avoid costly recalculations.
767 */
768 unsigned int map_and_fenceable : 1;
769
770 /**
771 * Whether the current gtt mapping needs to be mappable (and isn't just
772 * mappable by accident). Track pin and fault separate for a more
773 * accurate mappable working set.
774 */
775 unsigned int fault_mappable : 1;
776 unsigned int pin_mappable : 1;
777
778 /*
779 * Is the GPU currently using a fence to access this buffer,
780 */
781 unsigned int pending_fenced_gpu_access:1;
782 unsigned int fenced_gpu_access:1;
788 783
789 struct page **pages; 784 struct page **pages;
790 785
791 /** 786 /**
792 * Current offset of the object in GTT space. 787 * DMAR support
793 *
794 * This is the same as gtt_space->start
795 */ 788 */
796 uint32_t gtt_offset; 789 struct scatterlist *sg_list;
790 int num_sg;
797 791
798 /* Which ring is refering to is this object */ 792 /**
799 struct intel_ring_buffer *ring; 793 * Used for performing relocations during execbuffer insertion.
794 */
795 struct hlist_node exec_node;
796 unsigned long exec_handle;
800 797
801 /** 798 /**
802 * Fake offset for use by mmap(2) 799 * Current offset of the object in GTT space.
800 *
801 * This is the same as gtt_space->start
803 */ 802 */
804 uint64_t mmap_offset; 803 uint32_t gtt_offset;
805 804
806 /** Breadcrumb of last rendering to the buffer. */ 805 /** Breadcrumb of last rendering to the buffer. */
807 uint32_t last_rendering_seqno; 806 uint32_t last_rendering_seqno;
807 struct intel_ring_buffer *ring;
808
809 /** Breadcrumb of last fenced GPU access to the buffer. */
810 uint32_t last_fenced_seqno;
811 struct intel_ring_buffer *last_fenced_ring;
808 812
809 /** Current tiling stride for the object, if it's tiled. */ 813 /** Current tiling stride for the object, if it's tiled. */
810 uint32_t stride; 814 uint32_t stride;
@@ -880,6 +884,68 @@ enum intel_chip_family {
880 CHIP_I965 = 0x08, 884 CHIP_I965 = 0x08,
881}; 885};
882 886
887#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
888
889#define IS_I830(dev) ((dev)->pci_device == 0x3577)
890#define IS_845G(dev) ((dev)->pci_device == 0x2562)
891#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
892#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
893#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
894#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
895#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
896#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
897#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
898#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
899#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
900#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
901#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
902#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
903#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
904#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
905#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
906#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
907#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
908
909#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
910#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
911#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
912#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
913#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
914
915#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
916#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
917#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
918
919#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
920#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
921
922/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
923 * rows, which changed the alignment requirements and fence programming.
924 */
925#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
926 IS_I915GM(dev)))
927#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
928#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
929#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
930#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
931#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
932#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
933/* dsparb controlled by hw only */
934#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
935
936#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
937#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
938#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
939
940#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
941#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
942
943#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
944#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
945#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
946
947#include "i915_trace.h"
948
883extern struct drm_ioctl_desc i915_ioctls[]; 949extern struct drm_ioctl_desc i915_ioctls[];
884extern int i915_max_ioctl; 950extern int i915_max_ioctl;
885extern unsigned int i915_fbpercrtc; 951extern unsigned int i915_fbpercrtc;
@@ -907,8 +973,8 @@ extern int i915_driver_device_is_agp(struct drm_device * dev);
907extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 973extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
908 unsigned long arg); 974 unsigned long arg);
909extern int i915_emit_box(struct drm_device *dev, 975extern int i915_emit_box(struct drm_device *dev,
910 struct drm_clip_rect *boxes, 976 struct drm_clip_rect *box,
911 int i, int DR1, int DR4); 977 int DR1, int DR4);
912extern int i915_reset(struct drm_device *dev, u8 flags); 978extern int i915_reset(struct drm_device *dev, u8 flags);
913extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 979extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
914extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 980extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
@@ -918,6 +984,7 @@ extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
918 984
919/* i915_irq.c */ 985/* i915_irq.c */
920void i915_hangcheck_elapsed(unsigned long data); 986void i915_hangcheck_elapsed(unsigned long data);
987void i915_handle_error(struct drm_device *dev, bool wedged);
921extern int i915_irq_emit(struct drm_device *dev, void *data, 988extern int i915_irq_emit(struct drm_device *dev, void *data,
922 struct drm_file *file_priv); 989 struct drm_file *file_priv);
923extern int i915_irq_wait(struct drm_device *dev, void *data, 990extern int i915_irq_wait(struct drm_device *dev, void *data,
@@ -953,6 +1020,13 @@ void
953i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1020i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
954 1021
955void intel_enable_asle (struct drm_device *dev); 1022void intel_enable_asle (struct drm_device *dev);
1023int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1024 int *max_error,
1025 struct timeval *vblank_time,
1026 unsigned flags);
1027
1028int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1029 int *vpos, int *hpos);
956 1030
957#ifdef CONFIG_DEBUG_FS 1031#ifdef CONFIG_DEBUG_FS
958extern void i915_destroy_error_state(struct drm_device *dev); 1032extern void i915_destroy_error_state(struct drm_device *dev);
@@ -1017,15 +1091,28 @@ int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1017 struct drm_file *file_priv); 1091 struct drm_file *file_priv);
1018void i915_gem_load(struct drm_device *dev); 1092void i915_gem_load(struct drm_device *dev);
1019int i915_gem_init_object(struct drm_gem_object *obj); 1093int i915_gem_init_object(struct drm_gem_object *obj);
1020struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, 1094void i915_gem_flush_ring(struct drm_device *dev,
1021 size_t size); 1095 struct intel_ring_buffer *ring,
1096 uint32_t invalidate_domains,
1097 uint32_t flush_domains);
1098struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1099 size_t size);
1022void i915_gem_free_object(struct drm_gem_object *obj); 1100void i915_gem_free_object(struct drm_gem_object *obj);
1023int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 1101int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1024void i915_gem_object_unpin(struct drm_gem_object *obj); 1102 uint32_t alignment,
1025int i915_gem_object_unbind(struct drm_gem_object *obj); 1103 bool map_and_fenceable);
1026void i915_gem_release_mmap(struct drm_gem_object *obj); 1104void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1105int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1106void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1027void i915_gem_lastclose(struct drm_device *dev); 1107void i915_gem_lastclose(struct drm_device *dev);
1028 1108
1109int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1110int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1111 bool interruptible);
1112void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1113 struct intel_ring_buffer *ring,
1114 u32 seqno);
1115
1029/** 1116/**
1030 * Returns true if seq1 is later than seq2. 1117 * Returns true if seq1 is later than seq2.
1031 */ 1118 */
@@ -1035,73 +1122,88 @@ i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1035 return (int32_t)(seq1 - seq2) >= 0; 1122 return (int32_t)(seq1 - seq2) >= 0;
1036} 1123}
1037 1124
1038int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, 1125static inline u32
1039 bool interruptible); 1126i915_gem_next_request_seqno(struct drm_device *dev,
1040int i915_gem_object_put_fence_reg(struct drm_gem_object *obj, 1127 struct intel_ring_buffer *ring)
1041 bool interruptible); 1128{
1129 drm_i915_private_t *dev_priv = dev->dev_private;
1130 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1131}
1132
1133int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1134 struct intel_ring_buffer *pipelined,
1135 bool interruptible);
1136int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1137
1042void i915_gem_retire_requests(struct drm_device *dev); 1138void i915_gem_retire_requests(struct drm_device *dev);
1043void i915_gem_reset(struct drm_device *dev); 1139void i915_gem_reset(struct drm_device *dev);
1044void i915_gem_clflush_object(struct drm_gem_object *obj); 1140void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1045int i915_gem_object_set_domain(struct drm_gem_object *obj, 1141int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1046 uint32_t read_domains, 1142 uint32_t read_domains,
1047 uint32_t write_domain); 1143 uint32_t write_domain);
1048int i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, 1144int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
1049 bool interruptible); 1145 bool interruptible);
1050int i915_gem_init_ringbuffer(struct drm_device *dev); 1146int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1051void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1147void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1052int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1148void i915_gem_do_init(struct drm_device *dev,
1053 unsigned long end); 1149 unsigned long start,
1054int i915_gpu_idle(struct drm_device *dev); 1150 unsigned long mappable_end,
1055int i915_gem_idle(struct drm_device *dev); 1151 unsigned long end);
1056uint32_t i915_add_request(struct drm_device *dev, 1152int __must_check i915_gpu_idle(struct drm_device *dev);
1057 struct drm_file *file_priv, 1153int __must_check i915_gem_idle(struct drm_device *dev);
1058 struct drm_i915_gem_request *request, 1154int __must_check i915_add_request(struct drm_device *dev,
1059 struct intel_ring_buffer *ring); 1155 struct drm_file *file_priv,
1060int i915_do_wait_request(struct drm_device *dev, 1156 struct drm_i915_gem_request *request,
1061 uint32_t seqno, 1157 struct intel_ring_buffer *ring);
1062 bool interruptible, 1158int __must_check i915_do_wait_request(struct drm_device *dev,
1063 struct intel_ring_buffer *ring); 1159 uint32_t seqno,
1160 bool interruptible,
1161 struct intel_ring_buffer *ring);
1064int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1162int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1065int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 1163int __must_check
1066 int write); 1164i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1067int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, 1165 bool write);
1068 bool pipelined); 1166int __must_check
1167i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1168 struct intel_ring_buffer *pipelined);
1069int i915_gem_attach_phys_object(struct drm_device *dev, 1169int i915_gem_attach_phys_object(struct drm_device *dev,
1070 struct drm_gem_object *obj, 1170 struct drm_i915_gem_object *obj,
1071 int id, 1171 int id,
1072 int align); 1172 int align);
1073void i915_gem_detach_phys_object(struct drm_device *dev, 1173void i915_gem_detach_phys_object(struct drm_device *dev,
1074 struct drm_gem_object *obj); 1174 struct drm_i915_gem_object *obj);
1075void i915_gem_free_all_phys_object(struct drm_device *dev); 1175void i915_gem_free_all_phys_object(struct drm_device *dev);
1076void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); 1176void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1077 1177
1078void i915_gem_shrinker_init(void); 1178/* i915_gem_gtt.c */
1079void i915_gem_shrinker_exit(void); 1179void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1180int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1181void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1080 1182
1081/* i915_gem_evict.c */ 1183/* i915_gem_evict.c */
1082int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment); 1184int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1083int i915_gem_evict_everything(struct drm_device *dev); 1185 unsigned alignment, bool mappable);
1084int i915_gem_evict_inactive(struct drm_device *dev); 1186int __must_check i915_gem_evict_everything(struct drm_device *dev,
1187 bool purgeable_only);
1188int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1189 bool purgeable_only);
1085 1190
1086/* i915_gem_tiling.c */ 1191/* i915_gem_tiling.c */
1087void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1192void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1088void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 1193void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1089void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); 1194void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1090bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
1091 int tiling_mode);
1092bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
1093 int tiling_mode);
1094 1195
1095/* i915_gem_debug.c */ 1196/* i915_gem_debug.c */
1096void i915_gem_dump_object(struct drm_gem_object *obj, int len, 1197void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1097 const char *where, uint32_t mark); 1198 const char *where, uint32_t mark);
1098#if WATCH_LISTS 1199#if WATCH_LISTS
1099int i915_verify_lists(struct drm_device *dev); 1200int i915_verify_lists(struct drm_device *dev);
1100#else 1201#else
1101#define i915_verify_lists(dev) 0 1202#define i915_verify_lists(dev) 0
1102#endif 1203#endif
1103void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 1204void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1104void i915_gem_dump_object(struct drm_gem_object *obj, int len, 1205 int handle);
1206void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1105 const char *where, uint32_t mark); 1207 const char *where, uint32_t mark);
1106 1208
1107/* i915_debugfs.c */ 1209/* i915_debugfs.c */
@@ -1163,6 +1265,7 @@ extern void intel_disable_fbc(struct drm_device *dev);
1163extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 1265extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1164extern bool intel_fbc_enabled(struct drm_device *dev); 1266extern bool intel_fbc_enabled(struct drm_device *dev);
1165extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1267extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1268extern void gen6_set_rps(struct drm_device *dev, u8 val);
1166extern void intel_detect_pch (struct drm_device *dev); 1269extern void intel_detect_pch (struct drm_device *dev);
1167extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); 1270extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1168 1271
@@ -1170,79 +1273,120 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1170#ifdef CONFIG_DEBUG_FS 1273#ifdef CONFIG_DEBUG_FS
1171extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1274extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1172extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1275extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1276
1277extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1278extern void intel_display_print_error_state(struct seq_file *m,
1279 struct drm_device *dev,
1280 struct intel_display_error_state *error);
1173#endif 1281#endif
1174 1282
1283#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1284
1285#define BEGIN_LP_RING(n) \
1286 intel_ring_begin(LP_RING(dev_priv), (n))
1287
1288#define OUT_RING(x) \
1289 intel_ring_emit(LP_RING(dev_priv), x)
1290
1291#define ADVANCE_LP_RING() \
1292 intel_ring_advance(LP_RING(dev_priv))
1293
1175/** 1294/**
1176 * Lock test for when it's just for synchronization of ring access. 1295 * Lock test for when it's just for synchronization of ring access.
1177 * 1296 *
1178 * In that case, we don't need to do it when GEM is initialized as nobody else 1297 * In that case, we don't need to do it when GEM is initialized as nobody else
1179 * has access to the ring. 1298 * has access to the ring.
1180 */ 1299 */
1181#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 1300#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1182 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ 1301 if (LP_RING(dev->dev_private)->obj == NULL) \
1183 == NULL) \ 1302 LOCK_TEST_WITH_RETURN(dev, file); \
1184 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1185} while (0) 1303} while (0)
1186 1304
1187static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg) 1305
1306#define __i915_read(x, y) \
1307static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1308 u##x val = read##y(dev_priv->regs + reg); \
1309 trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1310 return val; \
1311}
1312__i915_read(8, b)
1313__i915_read(16, w)
1314__i915_read(32, l)
1315__i915_read(64, q)
1316#undef __i915_read
1317
1318#define __i915_write(x, y) \
1319static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1320 trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1321 write##y(val, dev_priv->regs + reg); \
1322}
1323__i915_write(8, b)
1324__i915_write(16, w)
1325__i915_write(32, l)
1326__i915_write(64, q)
1327#undef __i915_write
1328
1329#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1330#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1331
1332#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1333#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1334#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1335#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1336
1337#define I915_READ(reg) i915_read32(dev_priv, (reg))
1338#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1339#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1340#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1341
1342#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1343#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1344
1345#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1346#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1347
1348
1349/* On SNB platform, before reading ring registers forcewake bit
1350 * must be set to prevent GT core from power down and stale values being
1351 * returned.
1352 */
1353void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
1354void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
1355static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
1188{ 1356{
1189 u32 val; 1357 u32 val;
1190 1358
1191 val = readl(dev_priv->regs + reg); 1359 if (dev_priv->info->gen >= 6) {
1192 if (dev_priv->debug_flags & I915_DEBUG_READ) 1360 __gen6_force_wake_get(dev_priv);
1193 printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg); 1361 val = I915_READ(reg);
1362 __gen6_force_wake_put(dev_priv);
1363 } else
1364 val = I915_READ(reg);
1365
1194 return val; 1366 return val;
1195} 1367}
1196 1368
1197static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, 1369static inline void
1198 u32 val) 1370i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1199{ 1371{
1200 writel(val, dev_priv->regs + reg); 1372 /* Trace down the write operation before the real write */
1201 if (dev_priv->debug_flags & I915_DEBUG_WRITE) 1373 trace_i915_reg_rw('W', reg, val, len);
1202 printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg); 1374 switch (len) {
1375 case 8:
1376 writeq(val, dev_priv->regs + reg);
1377 break;
1378 case 4:
1379 writel(val, dev_priv->regs + reg);
1380 break;
1381 case 2:
1382 writew(val, dev_priv->regs + reg);
1383 break;
1384 case 1:
1385 writeb(val, dev_priv->regs + reg);
1386 break;
1387 }
1203} 1388}
1204 1389
1205#define I915_READ(reg) i915_read(dev_priv, (reg))
1206#define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
1207#define I915_READ16(reg) readw(dev_priv->regs + (reg))
1208#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1209#define I915_READ8(reg) readb(dev_priv->regs + (reg))
1210#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1211#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1212#define I915_READ64(reg) readq(dev_priv->regs + (reg))
1213#define POSTING_READ(reg) (void)I915_READ(reg)
1214#define POSTING_READ16(reg) (void)I915_READ16(reg)
1215
1216#define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
1217 I915_DEBUG_WRITE)
1218#define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
1219 I915_DEBUG_WRITE))
1220
1221#define I915_VERBOSE 0
1222
1223#define BEGIN_LP_RING(n) do { \
1224 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1225 if (I915_VERBOSE) \
1226 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1227 intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \
1228} while (0)
1229
1230
1231#define OUT_RING(x) do { \
1232 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1233 if (I915_VERBOSE) \
1234 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1235 intel_ring_emit(dev, &dev_priv__->render_ring, x); \
1236} while (0)
1237
1238#define ADVANCE_LP_RING() do { \
1239 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1240 if (I915_VERBOSE) \
1241 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1242 dev_priv__->render_ring.tail); \
1243 intel_ring_advance(dev, &dev_priv__->render_ring); \
1244} while(0)
1245
1246/** 1390/**
1247 * Reads a dword out of the status page, which is written to from the command 1391 * Reads a dword out of the status page, which is written to from the command
1248 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1392 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
@@ -1259,72 +1403,9 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
1259 * The area from dword 0x20 to 0x3ff is available for driver usage. 1403 * The area from dword 0x20 to 0x3ff is available for driver usage.
1260 */ 1404 */
1261#define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ 1405#define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1262 (dev_priv->render_ring.status_page.page_addr))[reg]) 1406 (LP_RING(dev_priv)->status_page.page_addr))[reg])
1263#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1407#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1264#define I915_GEM_HWS_INDEX 0x20 1408#define I915_GEM_HWS_INDEX 0x20
1265#define I915_BREADCRUMB_INDEX 0x21 1409#define I915_BREADCRUMB_INDEX 0x21
1266 1410
1267#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1268
1269#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1270#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1271#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1272#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1273#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1274#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1275#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1276#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1277#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1278#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1279#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1280#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1281#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1282#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1283#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1284#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1285#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1286#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1287#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1288
1289#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1290#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1291#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1292#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1293#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1294
1295#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1296#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1297#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1298
1299#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1300#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1301
1302/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1303 * rows, which changed the alignment requirements and fence programming.
1304 */
1305#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1306 IS_I915GM(dev)))
1307#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1308#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1309#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1310#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1311#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1312#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1313/* dsparb controlled by hw only */
1314#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1315
1316#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1317#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1318#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1319#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1320
1321#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1322#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1323
1324#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1325#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1326#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1327
1328#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1329
1330#endif 1411#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 07:00:19 -0500