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path: root/drivers/gpu/drm/i915/i915_drv.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c462
1 files changed, 2 insertions, 460 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d95eca2bc454..eff66ed3e58e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -38,211 +38,9 @@ static struct pci_device_id pciidlist[] = {
38 i915_PCI_IDS 38 i915_PCI_IDS
39}; 39};
40 40
41enum pipe {
42 PIPE_A = 0,
43 PIPE_B,
44};
45
46static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
47{
48 struct drm_i915_private *dev_priv = dev->dev_private;
49
50 if (pipe == PIPE_A)
51 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
52 else
53 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
54}
55
56static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
57{
58 struct drm_i915_private *dev_priv = dev->dev_private;
59 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
60 u32 *array;
61 int i;
62
63 if (!i915_pipe_enabled(dev, pipe))
64 return;
65
66 if (pipe == PIPE_A)
67 array = dev_priv->save_palette_a;
68 else
69 array = dev_priv->save_palette_b;
70
71 for(i = 0; i < 256; i++)
72 array[i] = I915_READ(reg + (i << 2));
73}
74
75static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
76{
77 struct drm_i915_private *dev_priv = dev->dev_private;
78 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
79 u32 *array;
80 int i;
81
82 if (!i915_pipe_enabled(dev, pipe))
83 return;
84
85 if (pipe == PIPE_A)
86 array = dev_priv->save_palette_a;
87 else
88 array = dev_priv->save_palette_b;
89
90 for(i = 0; i < 256; i++)
91 I915_WRITE(reg + (i << 2), array[i]);
92}
93
94static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
95{
96 outb(reg, index_port);
97 return inb(data_port);
98}
99
100static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
101{
102 inb(st01);
103 outb(palette_enable | reg, VGA_AR_INDEX);
104 return inb(VGA_AR_DATA_READ);
105}
106
107static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
108{
109 inb(st01);
110 outb(palette_enable | reg, VGA_AR_INDEX);
111 outb(val, VGA_AR_DATA_WRITE);
112}
113
114static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
115{
116 outb(reg, index_port);
117 outb(val, data_port);
118}
119
120static void i915_save_vga(struct drm_device *dev)
121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 int i;
124 u16 cr_index, cr_data, st01;
125
126 /* VGA color palette registers */
127 dev_priv->saveDACMASK = inb(VGA_DACMASK);
128 /* DACCRX automatically increments during read */
129 outb(0, VGA_DACRX);
130 /* Read 3 bytes of color data from each index */
131 for (i = 0; i < 256 * 3; i++)
132 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
133
134 /* MSR bits */
135 dev_priv->saveMSR = inb(VGA_MSR_READ);
136 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
137 cr_index = VGA_CR_INDEX_CGA;
138 cr_data = VGA_CR_DATA_CGA;
139 st01 = VGA_ST01_CGA;
140 } else {
141 cr_index = VGA_CR_INDEX_MDA;
142 cr_data = VGA_CR_DATA_MDA;
143 st01 = VGA_ST01_MDA;
144 }
145
146 /* CRT controller regs */
147 i915_write_indexed(cr_index, cr_data, 0x11,
148 i915_read_indexed(cr_index, cr_data, 0x11) &
149 (~0x80));
150 for (i = 0; i <= 0x24; i++)
151 dev_priv->saveCR[i] =
152 i915_read_indexed(cr_index, cr_data, i);
153 /* Make sure we don't turn off CR group 0 writes */
154 dev_priv->saveCR[0x11] &= ~0x80;
155
156 /* Attribute controller registers */
157 inb(st01);
158 dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
159 for (i = 0; i <= 0x14; i++)
160 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
161 inb(st01);
162 outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
163 inb(st01);
164
165 /* Graphics controller registers */
166 for (i = 0; i < 9; i++)
167 dev_priv->saveGR[i] =
168 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
169
170 dev_priv->saveGR[0x10] =
171 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
172 dev_priv->saveGR[0x11] =
173 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
174 dev_priv->saveGR[0x18] =
175 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
176
177 /* Sequencer registers */
178 for (i = 0; i < 8; i++)
179 dev_priv->saveSR[i] =
180 i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
181}
182
183static void i915_restore_vga(struct drm_device *dev)
184{
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 int i;
187 u16 cr_index, cr_data, st01;
188
189 /* MSR bits */
190 outb(dev_priv->saveMSR, VGA_MSR_WRITE);
191 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
192 cr_index = VGA_CR_INDEX_CGA;
193 cr_data = VGA_CR_DATA_CGA;
194 st01 = VGA_ST01_CGA;
195 } else {
196 cr_index = VGA_CR_INDEX_MDA;
197 cr_data = VGA_CR_DATA_MDA;
198 st01 = VGA_ST01_MDA;
199 }
200
201 /* Sequencer registers, don't write SR07 */
202 for (i = 0; i < 7; i++)
203 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
204 dev_priv->saveSR[i]);
205
206 /* CRT controller regs */
207 /* Enable CR group 0 writes */
208 i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
209 for (i = 0; i <= 0x24; i++)
210 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
211
212 /* Graphics controller regs */
213 for (i = 0; i < 9; i++)
214 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
215 dev_priv->saveGR[i]);
216
217 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
218 dev_priv->saveGR[0x10]);
219 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
220 dev_priv->saveGR[0x11]);
221 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
222 dev_priv->saveGR[0x18]);
223
224 /* Attribute controller registers */
225 inb(st01);
226 for (i = 0; i <= 0x14; i++)
227 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
228 inb(st01); /* switch back to index mode */
229 outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
230 inb(st01);
231
232 /* VGA color palette registers */
233 outb(dev_priv->saveDACMASK, VGA_DACMASK);
234 /* DACCRX automatically increments during read */
235 outb(0, VGA_DACWX);
236 /* Read 3 bytes of color data from each index */
237 for (i = 0; i < 256 * 3; i++)
238 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
239
240}
241
242static int i915_suspend(struct drm_device *dev, pm_message_t state) 41static int i915_suspend(struct drm_device *dev, pm_message_t state)
243{ 42{
244 struct drm_i915_private *dev_priv = dev->dev_private; 43 struct drm_i915_private *dev_priv = dev->dev_private;
245 int i;
246 44
247 if (!dev || !dev_priv) { 45 if (!dev || !dev_priv) {
248 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv); 46 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
@@ -254,122 +52,8 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
254 return 0; 52 return 0;
255 53
256 pci_save_state(dev->pdev); 54 pci_save_state(dev->pdev);
257 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
258
259 /* Display arbitration control */
260 dev_priv->saveDSPARB = I915_READ(DSPARB);
261
262 /* Pipe & plane A info */
263 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
264 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
265 dev_priv->saveFPA0 = I915_READ(FPA0);
266 dev_priv->saveFPA1 = I915_READ(FPA1);
267 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
268 if (IS_I965G(dev))
269 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
270 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
271 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
272 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
273 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
274 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
275 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
276 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
277
278 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
279 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
280 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
281 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
282 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
283 if (IS_I965G(dev)) {
284 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
285 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
286 }
287 i915_save_palette(dev, PIPE_A);
288 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
289
290 /* Pipe & plane B info */
291 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
292 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
293 dev_priv->saveFPB0 = I915_READ(FPB0);
294 dev_priv->saveFPB1 = I915_READ(FPB1);
295 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
296 if (IS_I965G(dev))
297 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
298 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
299 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
300 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
301 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
302 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
303 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
304 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
305
306 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
307 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
308 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
309 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
310 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
311 if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
312 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
313 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
314 }
315 i915_save_palette(dev, PIPE_B);
316 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
317
318 /* CRT state */
319 dev_priv->saveADPA = I915_READ(ADPA);
320 55
321 /* LVDS state */ 56 i915_save_state(dev);
322 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
323 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
324 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
325 if (IS_I965G(dev))
326 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
327 if (IS_MOBILE(dev) && !IS_I830(dev))
328 dev_priv->saveLVDS = I915_READ(LVDS);
329 if (!IS_I830(dev) && !IS_845G(dev))
330 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
331 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
332 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
333 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
334
335 /* FIXME: save TV & SDVO state */
336
337 /* FBC state */
338 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
339 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
340 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
341 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
342
343 /* Interrupt state */
344 dev_priv->saveIIR = I915_READ(IIR);
345 dev_priv->saveIER = I915_READ(IER);
346 dev_priv->saveIMR = I915_READ(IMR);
347
348 /* VGA state */
349 dev_priv->saveVGA0 = I915_READ(VGA0);
350 dev_priv->saveVGA1 = I915_READ(VGA1);
351 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
352 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
353
354 /* Clock gating state */
355 dev_priv->saveD_STATE = I915_READ(D_STATE);
356 dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
357
358 /* Cache mode state */
359 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
360
361 /* Memory Arbitration state */
362 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
363
364 /* Scratch space */
365 for (i = 0; i < 16; i++) {
366 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
367 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
368 }
369 for (i = 0; i < 3; i++)
370 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
371
372 i915_save_vga(dev);
373 57
374 intel_opregion_free(dev); 58 intel_opregion_free(dev);
375 59
@@ -384,155 +68,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
384 68
385static int i915_resume(struct drm_device *dev) 69static int i915_resume(struct drm_device *dev)
386{ 70{
387 struct drm_i915_private *dev_priv = dev->dev_private;
388 int i;
389
390 pci_set_power_state(dev->pdev, PCI_D0); 71 pci_set_power_state(dev->pdev, PCI_D0);
391 pci_restore_state(dev->pdev); 72 pci_restore_state(dev->pdev);
392 if (pci_enable_device(dev->pdev)) 73 if (pci_enable_device(dev->pdev))
393 return -1; 74 return -1;
394 pci_set_master(dev->pdev); 75 pci_set_master(dev->pdev);
395 76
396 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 77 i915_restore_state(dev);
397
398 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
399
400 /* Pipe & plane A info */
401 /* Prime the clock */
402 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
403 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
404 ~DPLL_VCO_ENABLE);
405 udelay(150);
406 }
407 I915_WRITE(FPA0, dev_priv->saveFPA0);
408 I915_WRITE(FPA1, dev_priv->saveFPA1);
409 /* Actually enable it */
410 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
411 udelay(150);
412 if (IS_I965G(dev))
413 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
414 udelay(150);
415
416 /* Restore mode */
417 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
418 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
419 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
420 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
421 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
422 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
423 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
424
425 /* Restore plane info */
426 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
427 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
428 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
429 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
430 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
431 if (IS_I965G(dev)) {
432 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
433 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
434 }
435
436 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
437
438 i915_restore_palette(dev, PIPE_A);
439 /* Enable the plane */
440 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
441 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
442
443 /* Pipe & plane B info */
444 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
445 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
446 ~DPLL_VCO_ENABLE);
447 udelay(150);
448 }
449 I915_WRITE(FPB0, dev_priv->saveFPB0);
450 I915_WRITE(FPB1, dev_priv->saveFPB1);
451 /* Actually enable it */
452 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
453 udelay(150);
454 if (IS_I965G(dev))
455 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
456 udelay(150);
457
458 /* Restore mode */
459 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
460 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
461 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
462 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
463 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
464 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
465 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
466
467 /* Restore plane info */
468 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
469 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
470 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
471 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
472 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
473 if (IS_I965G(dev)) {
474 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
475 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
476 }
477
478 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
479
480 i915_restore_palette(dev, PIPE_B);
481 /* Enable the plane */
482 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
483 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
484
485 /* CRT state */
486 I915_WRITE(ADPA, dev_priv->saveADPA);
487
488 /* LVDS state */
489 if (IS_I965G(dev))
490 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
491 if (IS_MOBILE(dev) && !IS_I830(dev))
492 I915_WRITE(LVDS, dev_priv->saveLVDS);
493 if (!IS_I830(dev) && !IS_845G(dev))
494 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
495
496 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
497 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
498 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
499 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
500 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
501 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
502
503 /* FIXME: restore TV & SDVO state */
504
505 /* FBC info */
506 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
507 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
508 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
509 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
510
511 /* VGA state */
512 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
513 I915_WRITE(VGA0, dev_priv->saveVGA0);
514 I915_WRITE(VGA1, dev_priv->saveVGA1);
515 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
516 udelay(150);
517
518 /* Clock gating state */
519 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
520 I915_WRITE(CG_2D_DIS, dev_priv->saveCG_2D_DIS);
521
522 /* Cache mode state */
523 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
524
525 /* Memory arbitration state */
526 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
527
528 for (i = 0; i < 16; i++) {
529 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
530 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
531 }
532 for (i = 0; i < 3; i++)
533 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
534
535 i915_restore_vga(dev);
536 78
537 intel_opregion_init(dev); 79 intel_opregion_init(dev);
538 80
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