diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_dma.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 28c812a0c634..4d56dfd25e04 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c | |||
@@ -40,11 +40,11 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller) | |||
40 | { | 40 | { |
41 | drm_i915_private_t *dev_priv = dev->dev_private; | 41 | drm_i915_private_t *dev_priv = dev->dev_private; |
42 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | 42 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
43 | u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; | 43 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
44 | int i; | 44 | int i; |
45 | 45 | ||
46 | for (i = 0; i < 10000; i++) { | 46 | for (i = 0; i < 10000; i++) { |
47 | ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; | 47 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
48 | ring->space = ring->head - (ring->tail + 8); | 48 | ring->space = ring->head - (ring->tail + 8); |
49 | if (ring->space < 0) | 49 | if (ring->space < 0) |
50 | ring->space += ring->Size; | 50 | ring->space += ring->Size; |
@@ -67,8 +67,8 @@ void i915_kernel_lost_context(struct drm_device * dev) | |||
67 | drm_i915_private_t *dev_priv = dev->dev_private; | 67 | drm_i915_private_t *dev_priv = dev->dev_private; |
68 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | 68 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
69 | 69 | ||
70 | ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; | 70 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
71 | ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR; | 71 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; |
72 | ring->space = ring->head - (ring->tail + 8); | 72 | ring->space = ring->head - (ring->tail + 8); |
73 | if (ring->space < 0) | 73 | if (ring->space < 0) |
74 | ring->space += ring->Size; | 74 | ring->space += ring->Size; |
@@ -98,13 +98,13 @@ static int i915_dma_cleanup(struct drm_device * dev) | |||
98 | drm_pci_free(dev, dev_priv->status_page_dmah); | 98 | drm_pci_free(dev, dev_priv->status_page_dmah); |
99 | dev_priv->status_page_dmah = NULL; | 99 | dev_priv->status_page_dmah = NULL; |
100 | /* Need to rewrite hardware status page */ | 100 | /* Need to rewrite hardware status page */ |
101 | I915_WRITE(0x02080, 0x1ffff000); | 101 | I915_WRITE(HWS_PGA, 0x1ffff000); |
102 | } | 102 | } |
103 | 103 | ||
104 | if (dev_priv->status_gfx_addr) { | 104 | if (dev_priv->status_gfx_addr) { |
105 | dev_priv->status_gfx_addr = 0; | 105 | dev_priv->status_gfx_addr = 0; |
106 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | 106 | drm_core_ioremapfree(&dev_priv->hws_map, dev); |
107 | I915_WRITE(0x2080, 0x1ffff000); | 107 | I915_WRITE(HWS_PGA, 0x1ffff000); |
108 | } | 108 | } |
109 | 109 | ||
110 | return 0; | 110 | return 0; |
@@ -170,7 +170,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) | |||
170 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | 170 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; |
171 | 171 | ||
172 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | 172 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
173 | I915_WRITE(0x02080, dev_priv->dma_status_page); | 173 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
174 | } | 174 | } |
175 | DRM_DEBUG("Enabled hardware status page\n"); | 175 | DRM_DEBUG("Enabled hardware status page\n"); |
176 | return 0; | 176 | return 0; |
@@ -201,9 +201,9 @@ static int i915_dma_resume(struct drm_device * dev) | |||
201 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | 201 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); |
202 | 202 | ||
203 | if (dev_priv->status_gfx_addr != 0) | 203 | if (dev_priv->status_gfx_addr != 0) |
204 | I915_WRITE(0x02080, dev_priv->status_gfx_addr); | 204 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
205 | else | 205 | else |
206 | I915_WRITE(0x02080, dev_priv->dma_status_page); | 206 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
207 | DRM_DEBUG("Enabled hardware status page\n"); | 207 | DRM_DEBUG("Enabled hardware status page\n"); |
208 | 208 | ||
209 | return 0; | 209 | return 0; |
@@ -402,8 +402,8 @@ static void i915_emit_breadcrumb(struct drm_device *dev) | |||
402 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; | 402 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; |
403 | 403 | ||
404 | BEGIN_LP_RING(4); | 404 | BEGIN_LP_RING(4); |
405 | OUT_RING(CMD_STORE_DWORD_IDX); | 405 | OUT_RING(MI_STORE_DWORD_INDEX); |
406 | OUT_RING(20); | 406 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); |
407 | OUT_RING(dev_priv->counter); | 407 | OUT_RING(dev_priv->counter); |
408 | OUT_RING(0); | 408 | OUT_RING(0); |
409 | ADVANCE_LP_RING(); | 409 | ADVANCE_LP_RING(); |
@@ -505,7 +505,7 @@ static int i915_dispatch_flip(struct drm_device * dev) | |||
505 | i915_kernel_lost_context(dev); | 505 | i915_kernel_lost_context(dev); |
506 | 506 | ||
507 | BEGIN_LP_RING(2); | 507 | BEGIN_LP_RING(2); |
508 | OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); | 508 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
509 | OUT_RING(0); | 509 | OUT_RING(0); |
510 | ADVANCE_LP_RING(); | 510 | ADVANCE_LP_RING(); |
511 | 511 | ||
@@ -530,8 +530,8 @@ static int i915_dispatch_flip(struct drm_device * dev) | |||
530 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; | 530 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
531 | 531 | ||
532 | BEGIN_LP_RING(4); | 532 | BEGIN_LP_RING(4); |
533 | OUT_RING(CMD_STORE_DWORD_IDX); | 533 | OUT_RING(MI_STORE_DWORD_INDEX); |
534 | OUT_RING(20); | 534 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); |
535 | OUT_RING(dev_priv->counter); | 535 | OUT_RING(dev_priv->counter); |
536 | OUT_RING(0); | 536 | OUT_RING(0); |
537 | ADVANCE_LP_RING(); | 537 | ADVANCE_LP_RING(); |
@@ -728,8 +728,8 @@ static int i915_set_status_page(struct drm_device *dev, void *data, | |||
728 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | 728 | dev_priv->hw_status_page = dev_priv->hws_map.handle; |
729 | 729 | ||
730 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | 730 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
731 | I915_WRITE(0x02080, dev_priv->status_gfx_addr); | 731 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
732 | DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n", | 732 | DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", |
733 | dev_priv->status_gfx_addr); | 733 | dev_priv->status_gfx_addr); |
734 | DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); | 734 | DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); |
735 | return 0; | 735 | return 0; |