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path: root/drivers/gpu/drm/i915/i915_dma.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c40
1 files changed, 28 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index e5b138be45fa..701bfeac7f57 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -807,6 +807,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
807 case I915_PARAM_NUM_FENCES_AVAIL: 807 case I915_PARAM_NUM_FENCES_AVAIL:
808 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; 808 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
809 break; 809 break;
810 case I915_PARAM_HAS_OVERLAY:
811 value = dev_priv->overlay ? 1 : 0;
812 break;
813 case I915_PARAM_HAS_PAGEFLIPPING:
814 value = 1;
815 break;
810 default: 816 default:
811 DRM_DEBUG_DRIVER("Unknown parameter %d\n", 817 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
812 param->param); 818 param->param);
@@ -962,7 +968,7 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
962 * Some of the preallocated space is taken by the GTT 968 * Some of the preallocated space is taken by the GTT
963 * and popup. GTT is 1K per MB of aperture size, and popup is 4K. 969 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
964 */ 970 */
965 if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev)) 971 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev))
966 overhead = 4096; 972 overhead = 4096;
967 else 973 else
968 overhead = (*aperture_size / 1024) + 4096; 974 overhead = (*aperture_size / 1024) + 4096;
@@ -1048,7 +1054,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1048 int gtt_offset, gtt_size; 1054 int gtt_offset, gtt_size;
1049 1055
1050 if (IS_I965G(dev)) { 1056 if (IS_I965G(dev)) {
1051 if (IS_G4X(dev) || IS_IGDNG(dev)) { 1057 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
1052 gtt_offset = 2*1024*1024; 1058 gtt_offset = 2*1024*1024;
1053 gtt_size = 2*1024*1024; 1059 gtt_size = 2*1024*1024;
1054 } else { 1060 } else {
@@ -1070,7 +1076,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1070 1076
1071 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024)); 1077 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1072 1078
1073 DRM_DEBUG("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); 1079 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1074 1080
1075 /* Mask out these reserved bits on this hardware. */ 1081 /* Mask out these reserved bits on this hardware. */
1076 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) || 1082 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
@@ -1096,7 +1102,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1096 phys =(entry & PTE_ADDRESS_MASK) | 1102 phys =(entry & PTE_ADDRESS_MASK) |
1097 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4)); 1103 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1098 1104
1099 DRM_DEBUG("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys); 1105 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1100 1106
1101 return phys; 1107 return phys;
1102} 1108}
@@ -1306,7 +1312,7 @@ static void i915_get_mem_freq(struct drm_device *dev)
1306 drm_i915_private_t *dev_priv = dev->dev_private; 1312 drm_i915_private_t *dev_priv = dev->dev_private;
1307 u32 tmp; 1313 u32 tmp;
1308 1314
1309 if (!IS_IGD(dev)) 1315 if (!IS_PINEVIEW(dev))
1310 return; 1316 return;
1311 1317
1312 tmp = I915_READ(CLKCFG); 1318 tmp = I915_READ(CLKCFG);
@@ -1413,7 +1419,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1413 if (ret) 1419 if (ret)
1414 goto out_iomapfree; 1420 goto out_iomapfree;
1415 1421
1416 dev_priv->wq = create_workqueue("i915"); 1422 dev_priv->wq = create_singlethread_workqueue("i915");
1417 if (dev_priv->wq == NULL) { 1423 if (dev_priv->wq == NULL) {
1418 DRM_ERROR("Failed to create our workqueue.\n"); 1424 DRM_ERROR("Failed to create our workqueue.\n");
1419 ret = -ENOMEM; 1425 ret = -ENOMEM;
@@ -1434,7 +1440,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1434 1440
1435 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1441 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1436 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 1442 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1437 if (IS_G4X(dev) || IS_IGDNG(dev)) { 1443 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
1438 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 1444 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1439 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 1445 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1440 } 1446 }
@@ -1489,9 +1495,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1489 } 1495 }
1490 1496
1491 /* Must be done after probing outputs */ 1497 /* Must be done after probing outputs */
1492 /* FIXME: verify on IGDNG */ 1498 intel_opregion_init(dev, 0);
1493 if (!IS_IGDNG(dev))
1494 intel_opregion_init(dev, 0);
1495 1499
1496 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, 1500 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1497 (unsigned long) dev); 1501 (unsigned long) dev);
@@ -1525,6 +1529,15 @@ int i915_driver_unload(struct drm_device *dev)
1525 } 1529 }
1526 1530
1527 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1531 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1532 /*
1533 * free the memory space allocated for the child device
1534 * config parsed from VBT
1535 */
1536 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1537 kfree(dev_priv->child_dev);
1538 dev_priv->child_dev = NULL;
1539 dev_priv->child_dev_num = 0;
1540 }
1528 drm_irq_uninstall(dev); 1541 drm_irq_uninstall(dev);
1529 vga_client_register(dev->pdev, NULL, NULL, NULL); 1542 vga_client_register(dev->pdev, NULL, NULL, NULL);
1530 } 1543 }
@@ -1535,8 +1548,7 @@ int i915_driver_unload(struct drm_device *dev)
1535 if (dev_priv->regs != NULL) 1548 if (dev_priv->regs != NULL)
1536 iounmap(dev_priv->regs); 1549 iounmap(dev_priv->regs);
1537 1550
1538 if (!IS_IGDNG(dev)) 1551 intel_opregion_free(dev, 0);
1539 intel_opregion_free(dev, 0);
1540 1552
1541 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1553 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1542 intel_modeset_cleanup(dev); 1554 intel_modeset_cleanup(dev);
@@ -1548,6 +1560,8 @@ int i915_driver_unload(struct drm_device *dev)
1548 mutex_unlock(&dev->struct_mutex); 1560 mutex_unlock(&dev->struct_mutex);
1549 drm_mm_takedown(&dev_priv->vram); 1561 drm_mm_takedown(&dev_priv->vram);
1550 i915_gem_lastclose(dev); 1562 i915_gem_lastclose(dev);
1563
1564 intel_cleanup_overlay(dev);
1551 } 1565 }
1552 1566
1553 pci_dev_put(dev_priv->bridge_dev); 1567 pci_dev_put(dev_priv->bridge_dev);
@@ -1656,6 +1670,8 @@ struct drm_ioctl_desc i915_ioctls[] = {
1656 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), 1670 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1657 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), 1671 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1658 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0), 1672 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
1673 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1674 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1659}; 1675};
1660 1676
1661int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 1677int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);