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path: root/drivers/gpu/drm/i915/i915_debugfs.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index be88532b35cf..e913d325d5b8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -901,7 +901,7 @@ i915_next_seqno_set(void *data, u64 val)
901 901
902DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, 902DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
903 i915_next_seqno_get, i915_next_seqno_set, 903 i915_next_seqno_get, i915_next_seqno_set,
904 "next_seqno : 0x%llx\n"); 904 "0x%llx\n");
905 905
906static int i915_rstdby_delays(struct seq_file *m, void *unused) 906static int i915_rstdby_delays(struct seq_file *m, void *unused)
907{ 907{
@@ -1006,6 +1006,9 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
1006 max_freq = rp_state_cap & 0xff; 1006 max_freq = rp_state_cap & 0xff;
1007 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 1007 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1008 max_freq * GT_FREQUENCY_MULTIPLIER); 1008 max_freq * GT_FREQUENCY_MULTIPLIER);
1009
1010 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1011 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1009 } else { 1012 } else {
1010 seq_printf(m, "no P-state info available\n"); 1013 seq_printf(m, "no P-state info available\n");
1011 } 1014 }
@@ -1354,7 +1357,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
1354 if (ret) 1357 if (ret)
1355 return ret; 1358 return ret;
1356 1359
1357 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); 1360 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1358 1361
1359 for (gpu_freq = dev_priv->rps.min_delay; 1362 for (gpu_freq = dev_priv->rps.min_delay;
1360 gpu_freq <= dev_priv->rps.max_delay; 1363 gpu_freq <= dev_priv->rps.max_delay;
@@ -1363,7 +1366,10 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
1363 sandybridge_pcode_read(dev_priv, 1366 sandybridge_pcode_read(dev_priv,
1364 GEN6_PCODE_READ_MIN_FREQ_TABLE, 1367 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1365 &ia_freq); 1368 &ia_freq);
1366 seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100); 1369 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1370 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1371 ((ia_freq >> 0) & 0xff) * 100,
1372 ((ia_freq >> 8) & 0xff) * 100);
1367 } 1373 }
1368 1374
1369 mutex_unlock(&dev_priv->rps.hw_lock); 1375 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -1687,7 +1693,7 @@ i915_wedged_set(void *data, u64 val)
1687 1693
1688DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 1694DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1689 i915_wedged_get, i915_wedged_set, 1695 i915_wedged_get, i915_wedged_set,
1690 "wedged : %llu\n"); 1696 "%llu\n");
1691 1697
1692static int 1698static int
1693i915_ring_stop_get(void *data, u64 *val) 1699i915_ring_stop_get(void *data, u64 *val)
@@ -1841,7 +1847,7 @@ i915_max_freq_set(void *data, u64 val)
1841 1847
1842DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, 1848DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
1843 i915_max_freq_get, i915_max_freq_set, 1849 i915_max_freq_get, i915_max_freq_set,
1844 "max freq: %llu\n"); 1850 "%llu\n");
1845 1851
1846static int 1852static int
1847i915_min_freq_get(void *data, u64 *val) 1853i915_min_freq_get(void *data, u64 *val)
@@ -1892,7 +1898,7 @@ i915_min_freq_set(void *data, u64 val)
1892 1898
1893DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, 1899DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
1894 i915_min_freq_get, i915_min_freq_set, 1900 i915_min_freq_get, i915_min_freq_set,
1895 "min freq: %llu\n"); 1901 "%llu\n");
1896 1902
1897static int 1903static int
1898i915_cache_sharing_get(void *data, u64 *val) 1904i915_cache_sharing_get(void *data, u64 *val)