diff options
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_hdmi.c')
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_hdmi.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 743059fed39b..b565d1e63b3b 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c | |||
@@ -1557,8 +1557,7 @@ static void hdmi_v14_mode_set(struct hdmi_context *hdata, | |||
1557 | (m->vsync_start - m->vdisplay) / 2); | 1557 | (m->vsync_start - m->vdisplay) / 2); |
1558 | hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2); | 1558 | hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2); |
1559 | hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2); | 1559 | hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2); |
1560 | hdmi_set_reg(core->v_blank_f0, 2, (m->vtotal + | 1560 | hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2); |
1561 | ((m->vsync_end - m->vsync_start) * 4) + 5) / 2); | ||
1562 | hdmi_set_reg(core->v_blank_f1, 2, m->vtotal); | 1561 | hdmi_set_reg(core->v_blank_f1, 2, m->vtotal); |
1563 | hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7); | 1562 | hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7); |
1564 | hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2); | 1563 | hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2); |
@@ -1568,7 +1567,10 @@ static void hdmi_v14_mode_set(struct hdmi_context *hdata, | |||
1568 | (m->htotal / 2) + (m->hsync_start - m->hdisplay)); | 1567 | (m->htotal / 2) + (m->hsync_start - m->hdisplay)); |
1569 | hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2); | 1568 | hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2); |
1570 | hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2); | 1569 | hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2); |
1571 | hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/ | 1570 | hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2); |
1571 | hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1); | ||
1572 | hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1); | ||
1573 | hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1); | ||
1572 | hdmi_set_reg(tg->vact_st3, 2, 0x0); | 1574 | hdmi_set_reg(tg->vact_st3, 2, 0x0); |
1573 | hdmi_set_reg(tg->vact_st4, 2, 0x0); | 1575 | hdmi_set_reg(tg->vact_st4, 2, 0x0); |
1574 | } else { | 1576 | } else { |
@@ -1590,6 +1592,9 @@ static void hdmi_v14_mode_set(struct hdmi_context *hdata, | |||
1590 | hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */ | 1592 | hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */ |
1591 | hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */ | 1593 | hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */ |
1592 | hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */ | 1594 | hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */ |
1595 | hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */ | ||
1596 | hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */ | ||
1597 | hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ | ||
1593 | } | 1598 | } |
1594 | 1599 | ||
1595 | /* Following values & calculations are same irrespective of mode type */ | 1600 | /* Following values & calculations are same irrespective of mode type */ |
@@ -1621,12 +1626,9 @@ static void hdmi_v14_mode_set(struct hdmi_context *hdata, | |||
1621 | hdmi_set_reg(tg->hact_sz, 2, m->hdisplay); | 1626 | hdmi_set_reg(tg->hact_sz, 2, m->hdisplay); |
1622 | hdmi_set_reg(tg->v_fsz, 2, m->vtotal); | 1627 | hdmi_set_reg(tg->v_fsz, 2, m->vtotal); |
1623 | hdmi_set_reg(tg->vsync, 2, 0x1); | 1628 | hdmi_set_reg(tg->vsync, 2, 0x1); |
1624 | hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */ | ||
1625 | hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */ | 1629 | hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */ |
1626 | hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */ | 1630 | hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */ |
1627 | hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */ | ||
1628 | hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */ | 1631 | hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */ |
1629 | hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ | ||
1630 | hdmi_set_reg(tg->tg_3d, 1, 0x0); | 1632 | hdmi_set_reg(tg->tg_3d, 1, 0x0); |
1631 | } | 1633 | } |
1632 | 1634 | ||