27 files changed, 594 insertions, 246 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 0f82aa8fa158..573532f7553e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -70,7 +70,7 @@ config GPIO_GENERIC
 
 config GPIO_DA9052
         tristate "Dialog DA9052 GPIO"
-        depends on PMIC_DA9052
+        depends on PMIC_DA9052 && BROKEN
         help
           Say yes here to enable the GPIO driver for the DA9052 chip.
 
@@ -141,6 +141,12 @@ config GPIO_PL061
         help
           Say yes here to support the PrimeCell PL061 GPIO device
 
+config GPIO_PXA
+        bool "PXA GPIO support"
+        depends on ARCH_PXA || ARCH_MMP
+        help
+          Say yes here to support the PXA GPIO device
+
 config GPIO_XILINX
         bool "Xilinx GPIO support"
         depends on PPC_OF || MICROBLAZE
@@ -347,7 +353,7 @@ comment "PCI GPIO expanders:"
 
 config GPIO_CS5535
         tristate "AMD CS5535/CS5536 GPIO support"
-        depends on PCI && X86 && !CS5535_GPIO && MFD_CS5535
+        depends on PCI && X86 && MFD_CS5535
         help
           The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
           can be used for quite a number of things.  The CS5535/6 is found on
@@ -378,7 +384,7 @@ config GPIO_LANGWELL
           Say Y here to support Intel Langwell/Penwell GPIO.
 
 config GPIO_PCH
-        tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7223 IOH GPIO"
+        tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7223/ML7831) GPIO"
         depends on PCI && X86
         select GENERIC_IRQ_CHIP
         help
@@ -386,11 +392,12 @@ config GPIO_PCH
           which is an IOH(Input/Output Hub) for x86 embedded processor.
           This driver can access PCH GPIO device.
 
-          This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
-          Output Hub), ML7223.
+          This driver also can be used for LAPIS Semiconductor IOH(Input/
+          Output Hub), ML7223 and ML7831.
           ML7223 IOH is for MP(Media Phone) use.
-          ML7223 is companion chip for Intel Atom E6xx series.
-          ML7223 is completely compatible for Intel EG20T PCH.
+          ML7831 IOH is for general purpose use.
+          ML7223/ML7831 is companion chip for Intel Atom E6xx series.
+          ML7223/ML7831 is completely compatible for Intel EG20T PCH.
 
 config GPIO_ML_IOH
         tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support"
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7f20316fb156..62e641e79e8f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_ARCH_DAVINCI)	+= gpio-davinci.o
 obj-$(CONFIG_GPIO_EP93XX)       += gpio-ep93xx.o
 obj-$(CONFIG_GPIO_IT8761E)      += gpio-it8761e.o
 obj-$(CONFIG_GPIO_JANZ_TTL)     += gpio-janz-ttl.o
-obj-$(CONFIG_MACH_KS8695)       += gpio-ks8695.o
+obj-$(CONFIG_ARCH_KS8695)       += gpio-ks8695.o
 obj-$(CONFIG_GPIO_LANGWELL)     += gpio-langwell.o
 obj-$(CONFIG_ARCH_LPC32XX)      += gpio-lpc32xx.o
 obj-$(CONFIG_GPIO_MAX730X)      += gpio-max730x.o
@@ -40,7 +40,7 @@ obj-$(CONFIG_GPIO_PCA953X)	+= gpio-pca953x.o
 obj-$(CONFIG_GPIO_PCF857X)      += gpio-pcf857x.o
 obj-$(CONFIG_GPIO_PCH)          += gpio-pch.o
 obj-$(CONFIG_GPIO_PL061)        += gpio-pl061.o
-obj-$(CONFIG_PLAT_PXA)          += gpio-pxa.o
+obj-$(CONFIG_GPIO_PXA)          += gpio-pxa.o
 obj-$(CONFIG_GPIO_RDC321X)      += gpio-rdc321x.o
 obj-$(CONFIG_PLAT_SAMSUNG)      += gpio-samsung.o
 obj-$(CONFIG_ARCH_SA1100)       += gpio-sa1100.o
diff --git a/drivers/gpio/gpio-adp5520.c b/drivers/gpio/gpio-adp5520.c
index 9f2781537001..2f263cc32561 100644
--- a/drivers/gpio/gpio-adp5520.c
+++ b/drivers/gpio/gpio-adp5520.c
@@ -193,17 +193,7 @@ static struct platform_driver adp5520_gpio_driver = {
         .remove         = __devexit_p(adp5520_gpio_remove),
 };
 
-static int __init adp5520_gpio_init(void)
-{
-        return platform_driver_register(&adp5520_gpio_driver);
-}
-module_init(adp5520_gpio_init);
-
-static void __exit adp5520_gpio_exit(void)
-{
-        platform_driver_unregister(&adp5520_gpio_driver);
-}
-module_exit(adp5520_gpio_exit);
+module_platform_driver(adp5520_gpio_driver);
 
 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 MODULE_DESCRIPTION("GPIO ADP5520 Driver");
diff --git a/drivers/gpio/gpio-adp5588.c b/drivers/gpio/gpio-adp5588.c
index 3525ad918771..9ad1703d1408 100644
--- a/drivers/gpio/gpio-adp5588.c
+++ b/drivers/gpio/gpio-adp5588.c
@@ -418,9 +418,8 @@ static int __devinit adp5588_gpio_probe(struct i2c_client *client,
         if (ret)
                 goto err_irq;
 
-        dev_info(&client->dev, "gpios %d..%d (IRQ Base %d) on a %s Rev. %d\n",
-                        gc->base, gc->base + gc->ngpio - 1,
-                        pdata->irq_base, client->name, revid);
+        dev_info(&client->dev, "IRQ Base: %d Rev.: %d\n",
+                        pdata->irq_base, revid);
 
         if (pdata->setup) {
                 ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context);
diff --git a/drivers/gpio/gpio-bt8xx.c b/drivers/gpio/gpio-bt8xx.c
index ec57936aef62..5ca4098ba092 100644
--- a/drivers/gpio/gpio-bt8xx.c
+++ b/drivers/gpio/gpio-bt8xx.c
@@ -223,9 +223,6 @@ static int bt8xxgpio_probe(struct pci_dev *dev,
                 goto err_release_mem;
         }
 
-        printk(KERN_INFO "bt8xxgpio: Abusing BT8xx card for GPIOs %d to %d\n",
-               bg->gpio.base, bg->gpio.base + BT8XXGPIO_NR_GPIOS - 1);
-
         return 0;
 
 err_release_mem:
diff --git a/drivers/gpio/gpio-cs5535.c b/drivers/gpio/gpio-cs5535.c
index 6e16cba56ad2..19eda1bbe343 100644
--- a/drivers/gpio/gpio-cs5535.c
+++ b/drivers/gpio/gpio-cs5535.c
@@ -347,7 +347,6 @@ static int __devinit cs5535_gpio_probe(struct platform_device *pdev)
         if (err)
                 goto release_region;
 
-        dev_info(&pdev->dev, "GPIO support successfully loaded.\n");
         return 0;
 
 release_region:
@@ -382,18 +381,7 @@ static struct platform_driver cs5535_gpio_driver = {
         .remove = __devexit_p(cs5535_gpio_remove),
 };
 
-static int __init cs5535_gpio_init(void)
-{
-        return platform_driver_register(&cs5535_gpio_driver);
-}
-
-static void __exit cs5535_gpio_exit(void)
-{
-        platform_driver_unregister(&cs5535_gpio_driver);
-}
-
-module_init(cs5535_gpio_init);
-module_exit(cs5535_gpio_exit);
+module_platform_driver(cs5535_gpio_driver);
 
 MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
 MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
diff --git a/drivers/gpio/gpio-da9052.c b/drivers/gpio/gpio-da9052.c
index 038f5eb8b13d..56dd047d5844 100644
--- a/drivers/gpio/gpio-da9052.c
+++ b/drivers/gpio/gpio-da9052.c
@@ -22,7 +22,6 @@
 #include <linux/mfd/da9052/da9052.h>
 #include <linux/mfd/da9052/reg.h>
 #include <linux/mfd/da9052/pdata.h>
-#include <linux/mfd/da9052/gpio.h>
 
 #define DA9052_INPUT                            1
 #define DA9052_OUTPUT_OPENDRAIN         2
@@ -43,6 +42,9 @@
 #define DA9052_GPIO_MASK_UPPER_NIBBLE           0xF0
 #define DA9052_GPIO_MASK_LOWER_NIBBLE           0x0F
 #define DA9052_GPIO_NIBBLE_SHIFT                4
+#define DA9052_IRQ_GPI0                 16
+#define DA9052_GPIO_ODD_SHIFT                   7
+#define DA9052_GPIO_EVEN_SHIFT                  3
 
 struct da9052_gpio {
         struct da9052 *da9052;
@@ -104,33 +106,26 @@ static int da9052_gpio_get(struct gpio_chip *gc, unsigned offset)
 static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 {
         struct da9052_gpio *gpio = to_da9052_gpio(gc);
-        unsigned char register_value = 0;
         int ret;
 
         if (da9052_gpio_port_odd(offset)) {
-                if (value) {
-                        register_value = DA9052_GPIO_ODD_PORT_MODE;
                         ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
                                                 DA9052_GPIO_0_1_REG,
                                                 DA9052_GPIO_ODD_PORT_MODE,
-                                                register_value);
+                                                value << DA9052_GPIO_ODD_SHIFT);
                         if (ret != 0)
                                 dev_err(gpio->da9052->dev,
                                         "Failed to updated gpio odd reg,%d",
                                         ret);
-                }
         } else {
-                if (value) {
-                        register_value = DA9052_GPIO_EVEN_PORT_MODE;
                         ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
                                                 DA9052_GPIO_0_1_REG,
                                                 DA9052_GPIO_EVEN_PORT_MODE,
-                                                register_value);
+                                                value << DA9052_GPIO_EVEN_SHIFT);
                         if (ret != 0)
                                 dev_err(gpio->da9052->dev,
                                         "Failed to updated gpio even reg,%d",
                                         ret);
-                }
         }
 }
 
@@ -201,9 +196,9 @@ static struct gpio_chip reference_gp __devinitdata = {
         .direction_input = da9052_gpio_direction_input,
         .direction_output = da9052_gpio_direction_output,
         .to_irq = da9052_gpio_to_irq,
-        .can_sleep = 1;
-        .ngpio = 16;
-        .base = -1;
+        .can_sleep = 1,
+        .ngpio = 16,
+        .base = -1,
 };
 
 static int __devinit da9052_gpio_probe(struct platform_device *pdev)
@@ -259,17 +254,7 @@ static struct platform_driver da9052_gpio_driver = {
         },
 };
 
-static int __init da9052_gpio_init(void)
-{
-        return platform_driver_register(&da9052_gpio_driver);
-}
-module_init(da9052_gpio_init);
-
-static void __exit da9052_gpio_exit(void)
-{
-        return platform_driver_unregister(&da9052_gpio_driver);
-}
-module_exit(da9052_gpio_exit);
+module_platform_driver(da9052_gpio_driver);
 
 MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
 MODULE_DESCRIPTION("DA9052 GPIO Device Driver");
diff --git a/drivers/gpio/gpio-generic.c b/drivers/gpio/gpio-generic.c
index 4e24436b0f82..e38dd0c31973 100644
--- a/drivers/gpio/gpio-generic.c
+++ b/drivers/gpio/gpio-generic.c
@@ -524,17 +524,7 @@ static struct platform_driver bgpio_driver = {
         .remove = __devexit_p(bgpio_pdev_remove),
 };
 
-static int __init bgpio_platform_init(void)
-{
-        return platform_driver_register(&bgpio_driver);
-}
-module_init(bgpio_platform_init);
-
-static void __exit bgpio_platform_exit(void)
-{
-        platform_driver_unregister(&bgpio_driver);
-}
-module_exit(bgpio_platform_exit);
+module_platform_driver(bgpio_driver);
 
 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
 
diff --git a/drivers/gpio/gpio-janz-ttl.c b/drivers/gpio/gpio-janz-ttl.c
index 813ac077e5d7..f2f000dd70b3 100644
--- a/drivers/gpio/gpio-janz-ttl.c
+++ b/drivers/gpio/gpio-janz-ttl.c
@@ -201,8 +201,6 @@ static int __devinit ttl_probe(struct platform_device *pdev)
                 goto out_iounmap_regs;
         }
 
-        dev_info(&pdev->dev, "module %d: registered GPIO device\n",
-                             pdata->modno);
         return 0;
 
 out_iounmap_regs:
@@ -239,20 +237,9 @@ static struct platform_driver ttl_driver = {
         .remove         = __devexit_p(ttl_remove),
 };
 
-static int __init ttl_init(void)
-{
-        return platform_driver_register(&ttl_driver);
-}
-
-static void __exit ttl_exit(void)
-{
-        platform_driver_unregister(&ttl_driver);
-}
+module_platform_driver(ttl_driver);
 
 MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
 MODULE_DESCRIPTION("Janz MODULbus VMOD-TTL Driver");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:janz-ttl");
-
-module_init(ttl_init);
-module_exit(ttl_exit);
diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c
index ea8e73869250..461958fc2264 100644
--- a/drivers/gpio/gpio-ml-ioh.c
+++ b/drivers/gpio/gpio-ml-ioh.c
@@ -332,6 +332,34 @@ static void ioh_irq_mask(struct irq_data *d)
                   &chip->reg->regs[chip->ch].imask);
 }
 
+static void ioh_irq_disable(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct ioh_gpio *chip = gc->private;
+        unsigned long flags;
+        u32 ien;
+
+        spin_lock_irqsave(&chip->spinlock, flags);
+        ien = ioread32(&chip->reg->regs[chip->ch].ien);
+        ien &= ~(1 << (d->irq - chip->irq_base));
+        iowrite32(ien, &chip->reg->regs[chip->ch].ien);
+        spin_unlock_irqrestore(&chip->spinlock, flags);
+}
+
+static void ioh_irq_enable(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct ioh_gpio *chip = gc->private;
+        unsigned long flags;
+        u32 ien;
+
+        spin_lock_irqsave(&chip->spinlock, flags);
+        ien = ioread32(&chip->reg->regs[chip->ch].ien);
+        ien |= 1 << (d->irq - chip->irq_base);
+        iowrite32(ien, &chip->reg->regs[chip->ch].ien);
+        spin_unlock_irqrestore(&chip->spinlock, flags);
+}
+
 static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
 {
         struct ioh_gpio *chip = dev_id;
@@ -339,7 +367,7 @@ static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
         int i, j;
         int ret = IRQ_NONE;
 
-        for (i = 0; i < 8; i++) {
+        for (i = 0; i < 8; i++, chip++) {
                 reg_val = ioread32(&chip->reg->regs[i].istatus);
                 for (j = 0; j < num_ports[i]; j++) {
                         if (reg_val & BIT(j)) {
@@ -370,6 +398,8 @@ static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
         ct->chip.irq_mask = ioh_irq_mask;
         ct->chip.irq_unmask = ioh_irq_unmask;
         ct->chip.irq_set_type = ioh_irq_type;
+        ct->chip.irq_disable = ioh_irq_disable;
+        ct->chip.irq_enable = ioh_irq_enable;
 
         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index ec3fcf0a7e12..5cd04b65c556 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -132,6 +132,15 @@ static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val
         return 0;
 }
 
+static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        /* GPIO 28..31 are input only on MPC5121 */
+        if (gpio >= 28)
+                return -EINVAL;
+
+        return mpc8xxx_gpio_dir_out(gc, gpio, val);
+}
+
 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 {
         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
@@ -340,11 +349,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
         mm_gc->save_regs = mpc8xxx_gpio_save_regs;
         gc->ngpio = MPC8XXX_GPIO_PINS;
         gc->direction_input = mpc8xxx_gpio_dir_in;
-        gc->direction_output = mpc8xxx_gpio_dir_out;
-        if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
-                gc->get = mpc8572_gpio_get;
-        else
-                gc->get = mpc8xxx_gpio_get;
+        gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
+                mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
+        gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
+                mpc8572_gpio_get : mpc8xxx_gpio_get;
         gc->set = mpc8xxx_gpio_set;
         gc->to_irq = mpc8xxx_gpio_to_irq;
 
diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/gpio/gpio-nomadik.c
index 1ebedfb6d46d..839624f9fe6a 100644
--- a/drivers/gpio/gpio-nomadik.c
+++ b/drivers/gpio/gpio-nomadik.c
@@ -1150,8 +1150,8 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
 
         nmk_gpio_init_irq(nmk_chip);
 
-        dev_info(&dev->dev, "Bits %i-%i at address %p\n",
-                 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
+        dev_info(&dev->dev, "at address %p\n",
+                 nmk_chip->addr);
         return 0;
 
 out_free:
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 147df8ae79db..d3f3e8f54561 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -546,7 +546,7 @@ static void pca953x_irq_teardown(struct pca953x_chip *chip)
  * Translate OpenFirmware node properties into platform_data
  * WARNING: This is DEPRECATED and will be removed eventually!
  */
-void
+static void
 pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
 {
         struct device_node *node;
@@ -574,7 +574,7 @@ pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
                 *invert = *val;
 }
 #else
-void
+static void
 pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
 {
         *gpio_base = -1;
diff --git a/drivers/gpio/gpio-pcf857x.c b/drivers/gpio/gpio-pcf857x.c
index 3e1f1ecd07be..2d1de9e7e9bd 100644
--- a/drivers/gpio/gpio-pcf857x.c
+++ b/drivers/gpio/gpio-pcf857x.c
@@ -290,10 +290,7 @@ static int pcf857x_probe(struct i2c_client *client,
          * methods can't be called from sleeping contexts.
          */
 
-        dev_info(&client->dev, "gpios %d..%d on a %s%s\n",
-                        gpio->chip.base,
-                        gpio->chip.base + gpio->chip.ngpio - 1,
-                        client->name,
+        dev_info(&client->dev, "%s\n",
                         client->irq ? " (irq ignored)" : "");
 
         /* Let platform code set up the GPIOs and their users.
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
index a6008e123d04..f0603297f829 100644
--- a/drivers/gpio/gpio-pch.c
+++ b/drivers/gpio/gpio-pch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -49,8 +49,8 @@ struct pch_regs {
 
 enum pch_type_t {
         INTEL_EG20T_PCH,
-        OKISEMI_ML7223m_IOH, /* OKISEMI ML7223 IOH PCIe Bus-m */
-        OKISEMI_ML7223n_IOH  /* OKISEMI ML7223 IOH PCIe Bus-n */
+        OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
+        OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
 };
 
 /* Specifies number of GPIO PINS */
@@ -524,6 +524,7 @@ static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
         { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
         { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
+        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
         { 0, }
 };
 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 093c90bd3c1d..8f79c03049f3 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -238,10 +238,6 @@ static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
         int ret, irq, i;
         static DECLARE_BITMAP(init_irq, NR_IRQS);
 
-        pdata = dev->dev.platform_data;
-        if (pdata == NULL)
-                return -ENODEV;
-
         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
         if (chip == NULL)
                 return -ENOMEM;
@@ -350,6 +346,8 @@ static struct amba_id pl061_ids[] = {
         { 0, 0 },
 };
 
+MODULE_DEVICE_TABLE(amba, pl061_ids);
+
 static struct amba_driver pl061_gpio_driver = {
         .drv = {
                 .name   = "pl061_gpio",
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index ee137712f9db..b2d3ee1d183a 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -11,14 +11,46 @@
  *  it under the terms of the GNU General Public License version 2 as
  *  published by the Free Software Foundation.
  */
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
-#include <mach/gpio-pxa.h>
+/*
+ * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
+ * one set of registers. The register offsets are organized below:
+ *
+ *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
+ * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
+ * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
+ * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
+ *
+ * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
+ * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
+ * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
+ *
+ * NOTE:
+ *   BANK 3 is only available on PXA27x and later processors.
+ *   BANK 4 and 5 are only available on PXA935
+ */
+
+#define GPLR_OFFSET     0x00
+#define GPDR_OFFSET     0x0C
+#define GPSR_OFFSET     0x18
+#define GPCR_OFFSET     0x24
+#define GRER_OFFSET     0x30
+#define GFER_OFFSET     0x3C
+#define GEDR_OFFSET     0x48
+#define GAFR_OFFSET     0x54
+#define ED_MASK_OFFSET  0x9C    /* GPIO edge detection for AP side */
+
+#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 
 int pxa_last_gpio;
 
@@ -39,8 +71,20 @@ struct pxa_gpio_chip {
 #endif
 };
 
+enum {
+        PXA25X_GPIO = 0,
+        PXA26X_GPIO,
+        PXA27X_GPIO,
+        PXA3XX_GPIO,
+        PXA93X_GPIO,
+        MMP_GPIO = 0x10,
+        MMP2_GPIO,
+};
+
 static DEFINE_SPINLOCK(gpio_lock);
 static struct pxa_gpio_chip *pxa_gpio_chips;
+static int gpio_type;
+static void __iomem *gpio_reg_base;
 
 #define for_each_gpio_chip(i, c)                        \
         for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
@@ -55,6 +99,122 @@ static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
         return &pxa_gpio_chips[gpio_to_bank(gpio)];
 }
 
+static inline int gpio_is_pxa_type(int type)
+{
+        return (type & MMP_GPIO) == 0;
+}
+
+static inline int gpio_is_mmp_type(int type)
+{
+        return (type & MMP_GPIO) != 0;
+}
+
+/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
+ * as well as their Alternate Function value being '1' for GPIO in GAFRx.
+ */
+static inline int __gpio_is_inverted(int gpio)
+{
+        if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
+                return 1;
+        return 0;
+}
+
+/*
+ * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
+ * function of a GPIO, and GPDRx cannot be altered once configured. It
+ * is attributed as "occupied" here (I know this terminology isn't
+ * accurate, you are welcome to propose a better one :-)
+ */
+static inline int __gpio_is_occupied(unsigned gpio)
+{
+        struct pxa_gpio_chip *pxachip;
+        void __iomem *base;
+        unsigned long gafr = 0, gpdr = 0;
+        int ret, af = 0, dir = 0;
+
+        pxachip = gpio_to_pxachip(gpio);
+        base = gpio_chip_base(&pxachip->chip);
+        gpdr = readl_relaxed(base + GPDR_OFFSET);
+
+        switch (gpio_type) {
+        case PXA25X_GPIO:
+        case PXA26X_GPIO:
+        case PXA27X_GPIO:
+                gafr = readl_relaxed(base + GAFR_OFFSET);
+                af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
+                dir = gpdr & GPIO_bit(gpio);
+
+                if (__gpio_is_inverted(gpio))
+                        ret = (af != 1) || (dir == 0);
+                else
+                        ret = (af != 0) || (dir != 0);
+                break;
+        default:
+                ret = gpdr & GPIO_bit(gpio);
+                break;
+        }
+        return ret;
+}
+
+#ifdef CONFIG_ARCH_PXA
+static inline int __pxa_gpio_to_irq(int gpio)
+{
+        if (gpio_is_pxa_type(gpio_type))
+                return PXA_GPIO_TO_IRQ(gpio);
+        return -1;
+}
+
+static inline int __pxa_irq_to_gpio(int irq)
+{
+        if (gpio_is_pxa_type(gpio_type))
+                return irq - PXA_GPIO_TO_IRQ(0);
+        return -1;
+}
+#else
+static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
+static inline int __pxa_irq_to_gpio(int irq) { return -1; }
+#endif
+
+#ifdef CONFIG_ARCH_MMP
+static inline int __mmp_gpio_to_irq(int gpio)
+{
+        if (gpio_is_mmp_type(gpio_type))
+                return MMP_GPIO_TO_IRQ(gpio);
+        return -1;
+}
+
+static inline int __mmp_irq_to_gpio(int irq)
+{
+        if (gpio_is_mmp_type(gpio_type))
+                return irq - MMP_GPIO_TO_IRQ(0);
+        return -1;
+}
+#else
+static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
+static inline int __mmp_irq_to_gpio(int irq) { return -1; }
+#endif
+
+static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        int gpio, ret;
+
+        gpio = chip->base + offset;
+        ret = __pxa_gpio_to_irq(gpio);
+        if (ret >= 0)
+                return ret;
+        return __mmp_gpio_to_irq(gpio);
+}
+
+int pxa_irq_to_gpio(int irq)
+{
+        int ret;
+
+        ret = __pxa_irq_to_gpio(irq);
+        if (ret >= 0)
+                return ret;
+        return __mmp_irq_to_gpio(irq);
+}
+
 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         void __iomem *base = gpio_chip_base(chip);
@@ -63,12 +223,12 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        value = __raw_readl(base + GPDR_OFFSET);
+        value = readl_relaxed(base + GPDR_OFFSET);
         if (__gpio_is_inverted(chip->base + offset))
                 value |= mask;
         else
                 value &= ~mask;
-        __raw_writel(value, base + GPDR_OFFSET);
+        writel_relaxed(value, base + GPDR_OFFSET);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
         return 0;
@@ -81,16 +241,16 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip,
         uint32_t tmp, mask = 1 << offset;
         unsigned long flags;
 
-        __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
+        writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        tmp = __raw_readl(base + GPDR_OFFSET);
+        tmp = readl_relaxed(base + GPDR_OFFSET);
         if (__gpio_is_inverted(chip->base + offset))
                 tmp &= ~mask;
         else
                 tmp |= mask;
-        __raw_writel(tmp, base + GPDR_OFFSET);
+        writel_relaxed(tmp, base + GPDR_OFFSET);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
         return 0;
@@ -98,16 +258,16 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip,
 
 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
+        return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
 }
 
 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-        __raw_writel(1 << offset, gpio_chip_base(chip) +
+        writel_relaxed(1 << offset, gpio_chip_base(chip) +
                                 (value ? GPSR_OFFSET : GPCR_OFFSET));
 }
 
-static int __init pxa_init_gpio_chip(int gpio_end)
+static int __devinit pxa_init_gpio_chip(int gpio_end)
 {
         int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
         struct pxa_gpio_chip *chips;
@@ -122,7 +282,7 @@ static int __init pxa_init_gpio_chip(int gpio_end)
                 struct gpio_chip *c = &chips[i].chip;
 
                 sprintf(chips[i].label, "gpio-%d", i);
-                chips[i].regbase = GPIO_BANK(i);
+                chips[i].regbase = gpio_reg_base + BANK_OFF(i);
 
                 c->base  = gpio;
                 c->label = chips[i].label;
@@ -131,6 +291,7 @@ static int __init pxa_init_gpio_chip(int gpio_end)
                 c->direction_output = pxa_gpio_direction_output;
                 c->get = pxa_gpio_get;
                 c->set = pxa_gpio_set;
+                c->to_irq = pxa_gpio_to_irq;
 
                 /* number of GPIOs on last bank may be less than 32 */
                 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
@@ -147,18 +308,18 @@ static inline void update_edge_detect(struct pxa_gpio_chip *c)
 {
         uint32_t grer, gfer;
 
-        grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
-        gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
+        grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
+        gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
         grer |= c->irq_edge_rise & c->irq_mask;
         gfer |= c->irq_edge_fall & c->irq_mask;
-        __raw_writel(grer, c->regbase + GRER_OFFSET);
-        __raw_writel(gfer, c->regbase + GFER_OFFSET);
+        writel_relaxed(grer, c->regbase + GRER_OFFSET);
+        writel_relaxed(gfer, c->regbase + GFER_OFFSET);
 }
 
 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
 {
         struct pxa_gpio_chip *c;
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         unsigned long gpdr, mask = GPIO_bit(gpio);
 
         c = gpio_to_pxachip(gpio);
@@ -176,12 +337,12 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
         }
 
-        gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
+        gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
 
         if (__gpio_is_inverted(gpio))
-                __raw_writel(gpdr | mask,  c->regbase + GPDR_OFFSET);
+                writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
         else
-                __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
+                writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
 
         if (type & IRQ_TYPE_EDGE_RISING)
                 c->irq_edge_rise |= mask;
@@ -212,9 +373,9 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                 for_each_gpio_chip(gpio, c) {
                         gpio_base = c->chip.base;
 
-                        gedr = __raw_readl(c->regbase + GEDR_OFFSET);
+                        gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
                         gedr = gedr & c->irq_mask;
-                        __raw_writel(gedr, c->regbase + GEDR_OFFSET);
+                        writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
 
                         n = find_first_bit(&gedr, BITS_PER_LONG);
                         while (n < BITS_PER_LONG) {
@@ -229,29 +390,29 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 
 static void pxa_ack_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
 
-        __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
+        writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
 }
 
 static void pxa_mask_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
         uint32_t grer, gfer;
 
         c->irq_mask &= ~GPIO_bit(gpio);
 
-        grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
-        gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
-        __raw_writel(grer, c->regbase + GRER_OFFSET);
-        __raw_writel(gfer, c->regbase + GFER_OFFSET);
+        grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
+        gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
+        writel_relaxed(grer, c->regbase + GRER_OFFSET);
+        writel_relaxed(gfer, c->regbase + GFER_OFFSET);
 }
 
 static void pxa_unmask_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
 
         c->irq_mask |= GPIO_bit(gpio);
@@ -266,34 +427,143 @@ static struct irq_chip pxa_muxed_gpio_chip = {
         .irq_set_type   = pxa_gpio_irq_type,
 };
 
-void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
+static int pxa_gpio_nums(void)
 {
-        struct pxa_gpio_chip *c;
-        int gpio, irq;
+        int count = 0;
+
+#ifdef CONFIG_ARCH_PXA
+        if (cpu_is_pxa25x()) {
+#ifdef CONFIG_CPU_PXA26x
+                count = 89;
+                gpio_type = PXA26X_GPIO;
+#elif defined(CONFIG_PXA25x)
+                count = 84;
+                gpio_type = PXA26X_GPIO;
+#endif /* CONFIG_CPU_PXA26x */
+        } else if (cpu_is_pxa27x()) {
+                count = 120;
+                gpio_type = PXA27X_GPIO;
+        } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
+                count = 191;
+                gpio_type = PXA93X_GPIO;
+        } else if (cpu_is_pxa3xx()) {
+                count = 127;
+                gpio_type = PXA3XX_GPIO;
+        }
+#endif /* CONFIG_ARCH_PXA */
+
+#ifdef CONFIG_ARCH_MMP
+        if (cpu_is_pxa168() || cpu_is_pxa910()) {
+                count = 127;
+                gpio_type = MMP_GPIO;
+        } else if (cpu_is_mmp2()) {
+                count = 191;
+                gpio_type = MMP2_GPIO;
+        }
+#endif /* CONFIG_ARCH_MMP */
+        return count;
+}
 
-        pxa_last_gpio = end;
+static int __devinit pxa_gpio_probe(struct platform_device *pdev)
+{
+        struct pxa_gpio_chip *c;
+        struct resource *res;
+        struct clk *clk;
+        int gpio, irq, ret;
+        int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
+
+        pxa_last_gpio = pxa_gpio_nums();
+        if (!pxa_last_gpio)
+                return -EINVAL;
+
+        irq0 = platform_get_irq_byname(pdev, "gpio0");
+        irq1 = platform_get_irq_byname(pdev, "gpio1");
+        irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
+        if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
+                || (irq_mux <= 0))
+                return -EINVAL;
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -EINVAL;
+        gpio_reg_base = ioremap(res->start, resource_size(res));
+        if (!gpio_reg_base)
+                return -EINVAL;
+
+        if (irq0 > 0)
+                gpio_offset = 2;
+
+        clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(clk)) {
+                dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
+                        PTR_ERR(clk));
+                iounmap(gpio_reg_base);
+                return PTR_ERR(clk);
+        }
+        ret = clk_prepare(clk);
+        if (ret) {
+                clk_put(clk);
+                iounmap(gpio_reg_base);
+                return ret;
+        }
+        ret = clk_enable(clk);
+        if (ret) {
+                clk_unprepare(clk);
+                clk_put(clk);
+                iounmap(gpio_reg_base);
+                return ret;
+        }
 
         /* Initialize GPIO chips */
-        pxa_init_gpio_chip(end);
+        pxa_init_gpio_chip(pxa_last_gpio);
 
         /* clear all GPIO edge detects */
         for_each_gpio_chip(gpio, c) {
-                __raw_writel(0, c->regbase + GFER_OFFSET);
-                __raw_writel(0, c->regbase + GRER_OFFSET);
-                __raw_writel(~0,c->regbase + GEDR_OFFSET);
+                writel_relaxed(0, c->regbase + GFER_OFFSET);
+                writel_relaxed(0, c->regbase + GRER_OFFSET);
+                writel_relaxed(~0,c->regbase + GEDR_OFFSET);
+                /* unmask GPIO edge detect for AP side */
+                if (gpio_is_mmp_type(gpio_type))
+                        writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
         }
 
-        for (irq  = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
+#ifdef CONFIG_ARCH_PXA
+        irq = gpio_to_irq(0);
+        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                 handle_edge_irq);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
+
+        irq = gpio_to_irq(1);
+        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                 handle_edge_irq);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
+#endif
+
+        for (irq  = gpio_to_irq(gpio_offset);
+                irq <= gpio_to_irq(pxa_last_gpio); irq++) {
                 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
                                          handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        /* Install handler for GPIO>=2 edge detect interrupts */
-        irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
-        pxa_muxed_gpio_chip.irq_set_wake = fn;
+        irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
+        return 0;
 }
 
+static struct platform_driver pxa_gpio_driver = {
+        .probe          = pxa_gpio_probe,
+        .driver         = {
+                .name   = "pxa-gpio",
+        },
+};
+
+static int __init pxa_gpio_init(void)
+{
+        return platform_driver_register(&pxa_gpio_driver);
+}
+postcore_initcall(pxa_gpio_init);
+
 #ifdef CONFIG_PM
 static int pxa_gpio_suspend(void)
 {
@@ -301,13 +571,13 @@ static int pxa_gpio_suspend(void)
         int gpio;
 
         for_each_gpio_chip(gpio, c) {
-                c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
-                c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
-                c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
-                c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
+                c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
+                c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
+                c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
+                c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
 
                 /* Clear GPIO transition detect bits */
-                __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
+                writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
         }
         return 0;
 }
@@ -319,12 +589,12 @@ static void pxa_gpio_resume(void)
 
         for_each_gpio_chip(gpio, c) {
                 /* restore level with set/clear */
-                __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
-                __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
+                writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
+                writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
 
-                __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
-                __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
-                __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
+                writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
+                writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
+                writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
         }
 }
 #else
@@ -336,3 +606,10 @@ struct syscore_ops pxa_gpio_syscore_ops = {
         .suspend        = pxa_gpio_suspend,
         .resume         = pxa_gpio_resume,
 };
+
+static int __init pxa_gpio_sysinit(void)
+{
+        register_syscore_ops(&pxa_gpio_syscore_ops);
+        return 0;
+}
+postcore_initcall(pxa_gpio_sysinit);
diff --git a/drivers/gpio/gpio-rdc321x.c b/drivers/gpio/gpio-rdc321x.c
index 2762698e0204..e97016af6443 100644
--- a/drivers/gpio/gpio-rdc321x.c
+++ b/drivers/gpio/gpio-rdc321x.c
@@ -227,18 +227,7 @@ static struct platform_driver rdc321x_gpio_driver = {
         .remove         = __devexit_p(rdc321x_gpio_remove),
 };
 
-static int __init rdc321x_gpio_init(void)
-{
-        return platform_driver_register(&rdc321x_gpio_driver);
-}
-
-static void __exit rdc321x_gpio_exit(void)
-{
-        platform_driver_unregister(&rdc321x_gpio_driver);
-}
-
-module_init(rdc321x_gpio_init);
-module_exit(rdc321x_gpio_exit);
+module_platform_driver(rdc321x_gpio_driver);
 
 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 MODULE_DESCRIPTION("RDC321x GPIO driver");
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 866251852719..a7661773c052 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -22,8 +22,11 @@
 #include <linux/spinlock.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/ioport.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/of_address.h>
 
 #include <asm/irq.h>
 
@@ -230,7 +233,7 @@ static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
  *
- * The reverse of samsung_gpio_setcfg_2bit(). Will return a value whicg
+ * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
  * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
  * S3C_GPIO_SPECIAL() macro.
  */
@@ -467,33 +470,42 @@ static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
 #endif
 
 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
-        {
+        [0] = {
                 .cfg_eint       = 0x0,
-        }, {
+        },
+        [1] = {
                 .cfg_eint       = 0x3,
-        }, {
+        },
+        [2] = {
                 .cfg_eint       = 0x7,
-        }, {
+        },
+        [3] = {
                 .cfg_eint       = 0xF,
-        }, {
+        },
+        [4] = {
                 .cfg_eint       = 0x0,
                 .set_config     = samsung_gpio_setcfg_2bit,
                 .get_config     = samsung_gpio_getcfg_2bit,
-        }, {
+        },
+        [5] = {
                 .cfg_eint       = 0x2,
                 .set_config     = samsung_gpio_setcfg_2bit,
                 .get_config     = samsung_gpio_getcfg_2bit,
-        }, {
+        },
+        [6] = {
                 .cfg_eint       = 0x3,
                 .set_config     = samsung_gpio_setcfg_2bit,
                 .get_config     = samsung_gpio_getcfg_2bit,
-        }, {
+        },
+        [7] = {
                 .set_config     = samsung_gpio_setcfg_2bit,
                 .get_config     = samsung_gpio_getcfg_2bit,
-        }, {
+        },
+        [8] = {
                 .set_pull       = exynos4_gpio_setpull,
                 .get_pull       = exynos4_gpio_getpull,
-        }, {
+        },
+        [9] = {
                 .cfg_eint       = 0x3,
                 .set_pull       = exynos4_gpio_setpull,
                 .get_pull       = exynos4_gpio_getpull,
@@ -2374,6 +2386,63 @@ static struct samsung_gpio_chip exynos4_gpios_3[] = {
 #endif
 };
 
+#if defined(CONFIG_ARCH_EXYNOS4) && defined(CONFIG_OF)
+static int exynos4_gpio_xlate(struct gpio_chip *gc, struct device_node *np,
+                              const void *gpio_spec, u32 *flags)
+{
+        const __be32 *gpio = gpio_spec;
+        const u32 n = be32_to_cpup(gpio);
+        unsigned int pin = gc->base + be32_to_cpu(gpio[0]);
+
+        if (WARN_ON(gc->of_gpio_n_cells < 4))
+                return -EINVAL;
+
+        if (n > gc->ngpio)
+                return -EINVAL;
+
+        if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(be32_to_cpu(gpio[1]))))
+                pr_warn("gpio_xlate: failed to set pin function\n");
+        if (s3c_gpio_setpull(pin, be32_to_cpu(gpio[2])))
+                pr_warn("gpio_xlate: failed to set pin pull up/down\n");
+        if (s5p_gpio_set_drvstr(pin, be32_to_cpu(gpio[3])))
+                pr_warn("gpio_xlate: failed to set pin drive strength\n");
+
+        return n;
+}
+
+static const struct of_device_id exynos4_gpio_dt_match[] __initdata = {
+        { .compatible = "samsung,exynos4-gpio", },
+        {}
+};
+
+static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+                                                 u64 base, u64 offset)
+{
+        struct gpio_chip *gc =  &chip->chip;
+        u64 address;
+
+        if (!of_have_populated_dt())
+                return;
+
+        address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
+        gc->of_node = of_find_matching_node_by_address(NULL,
+                        exynos4_gpio_dt_match, address);
+        if (!gc->of_node) {
+                pr_info("gpio: device tree node not found for gpio controller"
+                        " with base address %08llx\n", address);
+                return;
+        }
+        gc->of_gpio_n_cells = 4;
+        gc->of_xlate = exynos4_gpio_xlate;
+}
+#elif defined(CONFIG_ARCH_EXYNOS4)
+static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+                                                 u64 base, u64 offset)
+{
+        return;
+}
+#endif /* defined(CONFIG_ARCH_EXYNOS4) && defined(CONFIG_OF) */
+
 /* TODO: cleanup soc_is_* */
 static __init int samsung_gpiolib_init(void)
 {
@@ -2455,6 +2524,10 @@ static __init int samsung_gpiolib_init(void)
                                 chip->config = &exynos4_gpio_cfg;
                                 chip->group = group++;
                         }
+#ifdef CONFIG_CPU_EXYNOS4210
+                        exynos4_gpiolib_attach_ofnode(chip,
+                                        EXYNOS4_PA_GPIO1, i * 0x20);
+#endif
                 }
                 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, nr_chips, S5P_VA_GPIO1);
 
@@ -2467,6 +2540,10 @@ static __init int samsung_gpiolib_init(void)
                                 chip->config = &exynos4_gpio_cfg;
                                 chip->group = group++;
                         }
+#ifdef CONFIG_CPU_EXYNOS4210
+                        exynos4_gpiolib_attach_ofnode(chip,
+                                        EXYNOS4_PA_GPIO2, i * 0x20);
+#endif
                 }
                 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, nr_chips, S5P_VA_GPIO2);
 
@@ -2479,6 +2556,10 @@ static __init int samsung_gpiolib_init(void)
                                 chip->config = &exynos4_gpio_cfg;
                                 chip->group = group++;
                         }
+#ifdef CONFIG_CPU_EXYNOS4210
+                        exynos4_gpiolib_attach_ofnode(chip,
+                                        EXYNOS4_PA_GPIO3, i * 0x20);
+#endif
                 }
                 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, nr_chips, S5P_VA_GPIO3);
 
diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index 163515845494..8cadf4d683a8 100644
--- a/drivers/gpio/gpio-sch.c
+++ b/drivers/gpio/gpio-sch.c
@@ -297,18 +297,7 @@ static struct platform_driver sch_gpio_driver = {
         .remove         = __devexit_p(sch_gpio_remove),
 };
 
-static int __init sch_gpio_init(void)
-{
-        return platform_driver_register(&sch_gpio_driver);
-}
-
-static void __exit sch_gpio_exit(void)
-{
-        platform_driver_unregister(&sch_gpio_driver);
-}
-
-module_init(sch_gpio_init);
-module_exit(sch_gpio_exit);
+module_platform_driver(sch_gpio_driver);
 
 MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
 MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
diff --git a/drivers/gpio/gpio-timberdale.c b/drivers/gpio/gpio-timberdale.c
index c593bd46bfb6..031c6adf5b65 100644
--- a/drivers/gpio/gpio-timberdale.c
+++ b/drivers/gpio/gpio-timberdale.c
@@ -359,18 +359,7 @@ static struct platform_driver timbgpio_platform_driver = {
 
 /*--------------------------------------------------------------------------*/
 
-static int __init timbgpio_init(void)
-{
-        return platform_driver_register(&timbgpio_platform_driver);
-}
-
-static void __exit timbgpio_exit(void)
-{
-        platform_driver_unregister(&timbgpio_platform_driver);
-}
-
-module_init(timbgpio_init);
-module_exit(timbgpio_exit);
+module_platform_driver(timbgpio_platform_driver);
 
 MODULE_DESCRIPTION("Timberdale GPIO driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-ucb1400.c b/drivers/gpio/gpio-ucb1400.c
index 50e6bd1392ce..26405efe0f9f 100644
--- a/drivers/gpio/gpio-ucb1400.c
+++ b/drivers/gpio/gpio-ucb1400.c
@@ -103,23 +103,12 @@ static struct platform_driver ucb1400_gpio_driver = {
         },
 };
 
-static int __init ucb1400_gpio_init(void)
-{
-        return platform_driver_register(&ucb1400_gpio_driver);
-}
-
-static void __exit ucb1400_gpio_exit(void)
-{
-        platform_driver_unregister(&ucb1400_gpio_driver);
-}
-
 void __init ucb1400_gpio_set_data(struct ucb1400_gpio_data *data)
 {
         ucbdata = data;
 }
 
-module_init(ucb1400_gpio_init);
-module_exit(ucb1400_gpio_exit);
+module_platform_driver(ucb1400_gpio_driver);
 
 MODULE_DESCRIPTION("Philips UCB1400 GPIO driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-vr41xx.c b/drivers/gpio/gpio-vr41xx.c
index 98723cb9ac68..82d5c20ad3cb 100644
--- a/drivers/gpio/gpio-vr41xx.c
+++ b/drivers/gpio/gpio-vr41xx.c
@@ -571,15 +571,4 @@ static struct platform_driver giu_device_driver = {
         },
 };
 
-static int __init vr41xx_giu_init(void)
-{
-        return platform_driver_register(&giu_device_driver);
-}
-
-static void __exit vr41xx_giu_exit(void)
-{
-        platform_driver_unregister(&giu_device_driver);
-}
-
-module_init(vr41xx_giu_init);
-module_exit(vr41xx_giu_exit);
+module_platform_driver(giu_device_driver);
diff --git a/drivers/gpio/gpio-vx855.c b/drivers/gpio/gpio-vx855.c
index ef5aabd8b8b7..76ebfe5ff702 100644
--- a/drivers/gpio/gpio-vx855.c
+++ b/drivers/gpio/gpio-vx855.c
@@ -315,17 +315,7 @@ static struct platform_driver vx855gpio_driver = {
         .remove         = __devexit_p(vx855gpio_remove),
 };
 
-static int vx855gpio_init(void)
-{
-        return platform_driver_register(&vx855gpio_driver);
-}
-module_init(vx855gpio_init);
-
-static void vx855gpio_exit(void)
-{
-        platform_driver_unregister(&vx855gpio_driver);
-}
-module_exit(vx855gpio_exit);
+module_platform_driver(vx855gpio_driver);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Harald Welte <HaraldWelte@viatech.com>");
diff --git a/drivers/gpio/gpio-wm8994.c b/drivers/gpio/gpio-wm8994.c
index 96198f3fab73..92ea5350dfe9 100644
--- a/drivers/gpio/gpio-wm8994.c
+++ b/drivers/gpio/gpio-wm8994.c
@@ -117,6 +117,60 @@ static int wm8994_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 
 
 #ifdef CONFIG_DEBUG_FS
+static const char *wm8994_gpio_fn(u16 fn)
+{
+        switch (fn) {
+        case WM8994_GP_FN_PIN_SPECIFIC:
+                return "pin-specific";
+        case WM8994_GP_FN_GPIO:
+                return "GPIO";
+        case WM8994_GP_FN_SDOUT:
+                return "SDOUT";
+        case WM8994_GP_FN_IRQ:
+                return "IRQ";
+        case WM8994_GP_FN_TEMPERATURE:
+                return "Temperature";
+        case WM8994_GP_FN_MICBIAS1_DET:
+                return "MICBIAS1 detect";
+        case WM8994_GP_FN_MICBIAS1_SHORT:
+                return "MICBIAS1 short";
+        case WM8994_GP_FN_MICBIAS2_DET:
+                return "MICBIAS2 detect";
+        case WM8994_GP_FN_MICBIAS2_SHORT:
+                return "MICBIAS2 short";
+        case WM8994_GP_FN_FLL1_LOCK:
+                return "FLL1 lock";
+        case WM8994_GP_FN_FLL2_LOCK:
+                return "FLL2 lock";
+        case WM8994_GP_FN_SRC1_LOCK:
+                return "SRC1 lock";
+        case WM8994_GP_FN_SRC2_LOCK:
+                return "SRC2 lock";
+        case WM8994_GP_FN_DRC1_ACT:
+                return "DRC1 activity";
+        case WM8994_GP_FN_DRC2_ACT:
+                return "DRC2 activity";
+        case WM8994_GP_FN_DRC3_ACT:
+                return "DRC3 activity";
+        case WM8994_GP_FN_WSEQ_STATUS:
+                return "Write sequencer";
+        case WM8994_GP_FN_FIFO_ERROR:
+                return "FIFO error";
+        case WM8994_GP_FN_OPCLK:
+                return "OPCLK";
+        case WM8994_GP_FN_THW:
+                return "Thermal warning";
+        case WM8994_GP_FN_DCS_DONE:
+                return "DC servo";
+        case WM8994_GP_FN_FLL1_OUT:
+                return "FLL1 output";
+        case WM8994_GP_FN_FLL2_OUT:
+                return "FLL1 output";
+        default:
+                return "Unknown";
+        }
+}
+
 static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 {
         struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
@@ -148,8 +202,29 @@ static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
                         continue;
                 }
 
-                /* No decode yet; note that GPIO2 is special */
-                seq_printf(s, "(%x)\n", reg);
+                if (reg & WM8994_GPN_DIR)
+                        seq_printf(s, "in ");
+                else
+                        seq_printf(s, "out ");
+
+                if (reg & WM8994_GPN_PU)
+                        seq_printf(s, "pull up ");
+
+                if (reg & WM8994_GPN_PD)
+                        seq_printf(s, "pull down ");
+
+                if (reg & WM8994_GPN_POL)
+                        seq_printf(s, "inverted ");
+                else
+                        seq_printf(s, "noninverted ");
+
+                if (reg & WM8994_GPN_OP_CFG)
+                        seq_printf(s, "open drain ");
+                else
+                        seq_printf(s, "CMOS ");
+
+                seq_printf(s, "%s (%x)\n",
+                           wm8994_gpio_fn(reg & WM8994_GPN_FN_MASK), reg);
         }
 }
 #else
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 0ce6ac9898b1..79b0fe8a7253 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -206,7 +206,6 @@ static int __devinit xgpio_of_probe(struct device_node *np)
                        np->full_name, status);
                 return status;
         }
-        pr_info("XGpio: %s: registered\n", np->full_name);
         return 0;
 }
 
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index a971e3d043ba..17fdf4b6af93 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -114,7 +114,7 @@ static int gpio_ensure_requested(struct gpio_desc *desc, unsigned offset)
 }
 
 /* caller holds gpio_lock *OR* gpio is marked as requested */
-static inline struct gpio_chip *gpio_to_chip(unsigned gpio)
+struct gpio_chip *gpio_to_chip(unsigned gpio)
 {
         return gpio_desc[gpio].chip;
 }
@@ -1089,6 +1089,10 @@ unlock:
         if (status)
                 goto fail;
 
+        pr_info("gpiochip_add: registered GPIOs %d to %d on device: %s\n",
+                chip->base, chip->base + chip->ngpio - 1,
+                chip->label ? : "generic");
+
         return 0;
 fail:
         /* failures here can mean systems won't boot... */