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-rw-r--r--drivers/gpio/Kconfig42
-rw-r--r--drivers/gpio/Makefile4
-rw-r--r--drivers/gpio/gpio-adnp.c15
-rw-r--r--drivers/gpio/gpio-adp5588.c16
-rw-r--r--drivers/gpio/gpio-bcm-kona.c109
-rw-r--r--drivers/gpio/gpio-clps711x.c1
-rw-r--r--drivers/gpio/gpio-davinci.c75
-rw-r--r--drivers/gpio/gpio-dwapb.c438
-rw-r--r--drivers/gpio/gpio-em.c14
-rw-r--r--drivers/gpio/gpio-generic.c20
-rw-r--r--drivers/gpio/gpio-ich.c100
-rw-r--r--drivers/gpio/gpio-intel-mid.c22
-rw-r--r--drivers/gpio/gpio-iop.c2
-rw-r--r--drivers/gpio/gpio-lynxpoint.c16
-rw-r--r--drivers/gpio/gpio-max732x.c9
-rw-r--r--drivers/gpio/gpio-mcp23s08.c48
-rw-r--r--drivers/gpio/gpio-moxart.c40
-rw-r--r--drivers/gpio/gpio-mvebu.c7
-rw-r--r--drivers/gpio/gpio-mxs.c3
-rw-r--r--drivers/gpio/gpio-omap.c20
-rw-r--r--drivers/gpio/gpio-pca953x.c10
-rw-r--r--drivers/gpio/gpio-pch.c8
-rw-r--r--drivers/gpio/gpio-pl061.c108
-rw-r--r--drivers/gpio/gpio-rc5t583.c2
-rw-r--r--drivers/gpio/gpio-rcar.c32
-rw-r--r--drivers/gpio/gpio-samsung.c1
-rw-r--r--drivers/gpio/gpio-spear-spics.c4
-rw-r--r--drivers/gpio/gpio-stmpe.c18
-rw-r--r--drivers/gpio/gpio-syscon.c191
-rw-r--r--drivers/gpio/gpio-tnetv107x.c206
-rw-r--r--drivers/gpio/gpio-twl4030.c6
-rw-r--r--drivers/gpio/gpio-tz1090.c28
-rw-r--r--drivers/gpio/gpio-vr41xx.c20
-rw-r--r--drivers/gpio/gpio-zevio.c220
-rw-r--r--drivers/gpio/gpiolib-acpi.c482
-rw-r--r--drivers/gpio/gpiolib-of.c3
-rw-r--r--drivers/gpio/gpiolib.c417
-rw-r--r--drivers/gpio/gpiolib.h3
38 files changed, 2065 insertions, 695 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 903f24d28ba0..a86c49a605c6 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -55,6 +55,9 @@ config GPIO_ACPI
55 def_bool y 55 def_bool y
56 depends on ACPI 56 depends on ACPI
57 57
58config GPIOLIB_IRQCHIP
59 bool
60
58config DEBUG_GPIO 61config DEBUG_GPIO
59 bool "Debug GPIO calls" 62 bool "Debug GPIO calls"
60 depends on DEBUG_KERNEL 63 depends on DEBUG_KERNEL
@@ -128,6 +131,15 @@ config GPIO_GENERIC_PLATFORM
128 help 131 help
129 Say yes here to support basic platform_device memory-mapped GPIO controllers. 132 Say yes here to support basic platform_device memory-mapped GPIO controllers.
130 133
134config GPIO_DWAPB
135 tristate "Synopsys DesignWare APB GPIO driver"
136 select GPIO_GENERIC
137 select GENERIC_IRQ_CHIP
138 depends on OF_GPIO
139 help
140 Say Y or M here to build support for the Synopsys DesignWare APB
141 GPIO block.
142
131config GPIO_IT8761E 143config GPIO_IT8761E
132 tristate "IT8761E GPIO support" 144 tristate "IT8761E GPIO support"
133 depends on X86 # unconditional access to IO space. 145 depends on X86 # unconditional access to IO space.
@@ -145,6 +157,12 @@ config GPIO_EP93XX
145 depends on ARCH_EP93XX 157 depends on ARCH_EP93XX
146 select GPIO_GENERIC 158 select GPIO_GENERIC
147 159
160config GPIO_ZEVIO
161 bool "LSI ZEVIO SoC memory mapped GPIOs"
162 depends on ARM && OF_GPIO
163 help
164 Say yes here to support the GPIO controller in LSI ZEVIO SoCs.
165
148config GPIO_MM_LANTIQ 166config GPIO_MM_LANTIQ
149 bool "Lantiq Memory mapped GPIOs" 167 bool "Lantiq Memory mapped GPIOs"
150 depends on LANTIQ && SOC_XWAY 168 depends on LANTIQ && SOC_XWAY
@@ -192,7 +210,7 @@ config GPIO_MSM_V1
192 210
193config GPIO_MSM_V2 211config GPIO_MSM_V2
194 tristate "Qualcomm MSM GPIO v2" 212 tristate "Qualcomm MSM GPIO v2"
195 depends on GPIOLIB && OF && ARCH_MSM 213 depends on GPIOLIB && OF && ARCH_QCOM
196 help 214 help
197 Say yes here to support the GPIO interface on ARM v7 based 215 Say yes here to support the GPIO interface on ARM v7 based
198 Qualcomm MSM chips. Most of the pins on the MSM can be 216 Qualcomm MSM chips. Most of the pins on the MSM can be
@@ -228,7 +246,8 @@ config GPIO_OCTEON
228config GPIO_PL061 246config GPIO_PL061
229 bool "PrimeCell PL061 GPIO support" 247 bool "PrimeCell PL061 GPIO support"
230 depends on ARM_AMBA 248 depends on ARM_AMBA
231 select GENERIC_IRQ_CHIP 249 select IRQ_DOMAIN
250 select GPIOLIB_IRQCHIP
232 help 251 help
233 Say yes here to support the PrimeCell PL061 GPIO device 252 Say yes here to support the PrimeCell PL061 GPIO device
234 253
@@ -275,8 +294,15 @@ config GPIO_STA2X11
275 Say yes here to support the STA2x11/ConneXt GPIO device. 294 Say yes here to support the STA2x11/ConneXt GPIO device.
276 The GPIO module has 128 GPIO pins with alternate functions. 295 The GPIO module has 128 GPIO pins with alternate functions.
277 296
297config GPIO_SYSCON
298 tristate "GPIO based on SYSCON"
299 depends on MFD_SYSCON && OF
300 help
301 Say yes here to support GPIO functionality though SYSCON driver.
302
278config GPIO_TS5500 303config GPIO_TS5500
279 tristate "TS-5500 DIO blocks and compatibles" 304 tristate "TS-5500 DIO blocks and compatibles"
305 depends on TS5500 || COMPILE_TEST
280 help 306 help
281 This driver supports Digital I/O exposed by pin blocks found on some 307 This driver supports Digital I/O exposed by pin blocks found on some
282 Technologic Systems platforms. It includes, but is not limited to, 3 308 Technologic Systems platforms. It includes, but is not limited to, 3
@@ -462,7 +488,7 @@ config GPIO_MC9S08DZ60
462 Select this to enable the MC9S08DZ60 GPIO driver 488 Select this to enable the MC9S08DZ60 GPIO driver
463 489
464config GPIO_PCA953X 490config GPIO_PCA953X
465 tristate "PCA953x, PCA955x, PCA957x, TCA64xx, and MAX7310 I/O ports" 491 tristate "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
466 depends on I2C 492 depends on I2C
467 help 493 help
468 Say yes here to provide access to several register-oriented 494 Say yes here to provide access to several register-oriented
@@ -472,11 +498,15 @@ config GPIO_PCA953X
472 4 bits: pca9536, pca9537 498 4 bits: pca9536, pca9537
473 499
474 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, 500 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
475 pca9556, pca9557, pca9574, tca6408 501 pca9556, pca9557, pca9574, tca6408, xra1202
476 502
477 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, 503 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
478 tca6416 504 tca6416
479 505
506 24 bits: tca6424
507
508 40 bits: pca9505, pca9698
509
480config GPIO_PCA953X_IRQ 510config GPIO_PCA953X_IRQ
481 bool "Interrupt controller support for PCA953x" 511 bool "Interrupt controller support for PCA953x"
482 depends on GPIO_PCA953X=y 512 depends on GPIO_PCA953X=y
@@ -630,7 +660,7 @@ comment "PCI GPIO expanders:"
630 660
631config GPIO_CS5535 661config GPIO_CS5535
632 tristate "AMD CS5535/CS5536 GPIO support" 662 tristate "AMD CS5535/CS5536 GPIO support"
633 depends on PCI && X86 && MFD_CS5535 663 depends on MFD_CS5535
634 help 664 help
635 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that 665 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
636 can be used for quite a number of things. The CS5535/6 is found on 666 can be used for quite a number of things. The CS5535/6 is found on
@@ -642,7 +672,7 @@ config GPIO_BT8XX
642 tristate "BT8XX GPIO abuser" 672 tristate "BT8XX GPIO abuser"
643 depends on PCI && VIDEO_BT848=n 673 depends on PCI && VIDEO_BT848=n
644 help 674 help
645 The BT8xx frame grabber chip has 24 GPIO pins than can be abused 675 The BT8xx frame grabber chip has 24 GPIO pins that can be abused
646 as a cheap PCI GPIO card. 676 as a cheap PCI GPIO card.
647 677
648 This chip can be found on Miro, Hauppauge and STB TV-cards. 678 This chip can be found on Miro, Hauppauge and STB TV-cards.
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 5d50179ece16..6309aff1d806 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
23obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o 23obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
24obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o 24obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o
25obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o 25obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
26obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o
26obj-$(CONFIG_GPIO_EM) += gpio-em.o 27obj-$(CONFIG_GPIO_EM) += gpio-em.o
27obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o 28obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
28obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o 29obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
@@ -76,11 +77,11 @@ obj-$(CONFIG_GPIO_STA2X11) += gpio-sta2x11.o
76obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o 77obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
77obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o 78obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o
78obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o 79obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
80obj-$(CONFIG_GPIO_SYSCON) += gpio-syscon.o
79obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o 81obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o
80obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o 82obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
81obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o 83obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o
82obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o 84obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o
83obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o
84obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o 85obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o
85obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o 86obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o
86obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o 87obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o
@@ -99,3 +100,4 @@ obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
99obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o 100obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
100obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o 101obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
101obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o 102obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
103obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
diff --git a/drivers/gpio/gpio-adnp.c b/drivers/gpio/gpio-adnp.c
index 6fc6206b38bd..b2239d678d01 100644
--- a/drivers/gpio/gpio-adnp.c
+++ b/drivers/gpio/gpio-adnp.c
@@ -408,24 +408,23 @@ static void adnp_irq_bus_unlock(struct irq_data *data)
408 mutex_unlock(&adnp->irq_lock); 408 mutex_unlock(&adnp->irq_lock);
409} 409}
410 410
411static unsigned int adnp_irq_startup(struct irq_data *data) 411static int adnp_irq_reqres(struct irq_data *data)
412{ 412{
413 struct adnp *adnp = irq_data_get_irq_chip_data(data); 413 struct adnp *adnp = irq_data_get_irq_chip_data(data);
414 414
415 if (gpio_lock_as_irq(&adnp->gpio, data->hwirq)) 415 if (gpio_lock_as_irq(&adnp->gpio, data->hwirq)) {
416 dev_err(adnp->gpio.dev, 416 dev_err(adnp->gpio.dev,
417 "unable to lock HW IRQ %lu for IRQ\n", 417 "unable to lock HW IRQ %lu for IRQ\n",
418 data->hwirq); 418 data->hwirq);
419 /* Satisfy the .enable semantics by unmasking the line */ 419 return -EINVAL;
420 adnp_irq_unmask(data); 420 }
421 return 0; 421 return 0;
422} 422}
423 423
424static void adnp_irq_shutdown(struct irq_data *data) 424static void adnp_irq_relres(struct irq_data *data)
425{ 425{
426 struct adnp *adnp = irq_data_get_irq_chip_data(data); 426 struct adnp *adnp = irq_data_get_irq_chip_data(data);
427 427
428 adnp_irq_mask(data);
429 gpio_unlock_as_irq(&adnp->gpio, data->hwirq); 428 gpio_unlock_as_irq(&adnp->gpio, data->hwirq);
430} 429}
431 430
@@ -436,8 +435,8 @@ static struct irq_chip adnp_irq_chip = {
436 .irq_set_type = adnp_irq_set_type, 435 .irq_set_type = adnp_irq_set_type,
437 .irq_bus_lock = adnp_irq_bus_lock, 436 .irq_bus_lock = adnp_irq_bus_lock,
438 .irq_bus_sync_unlock = adnp_irq_bus_unlock, 437 .irq_bus_sync_unlock = adnp_irq_bus_unlock,
439 .irq_startup = adnp_irq_startup, 438 .irq_request_resources = adnp_irq_reqres,
440 .irq_shutdown = adnp_irq_shutdown, 439 .irq_release_resources = adnp_irq_relres,
441}; 440};
442 441
443static int adnp_irq_map(struct irq_domain *domain, unsigned int irq, 442static int adnp_irq_map(struct irq_domain *domain, unsigned int irq,
diff --git a/drivers/gpio/gpio-adp5588.c b/drivers/gpio/gpio-adp5588.c
index 3f190e68f973..d974020b78bb 100644
--- a/drivers/gpio/gpio-adp5588.c
+++ b/drivers/gpio/gpio-adp5588.c
@@ -67,9 +67,20 @@ static int adp5588_gpio_get_value(struct gpio_chip *chip, unsigned off)
67{ 67{
68 struct adp5588_gpio *dev = 68 struct adp5588_gpio *dev =
69 container_of(chip, struct adp5588_gpio, gpio_chip); 69 container_of(chip, struct adp5588_gpio, gpio_chip);
70 unsigned bank = ADP5588_BANK(off);
71 unsigned bit = ADP5588_BIT(off);
72 int val;
70 73
71 return !!(adp5588_gpio_read(dev->client, 74 mutex_lock(&dev->lock);
72 GPIO_DAT_STAT1 + ADP5588_BANK(off)) & ADP5588_BIT(off)); 75
76 if (dev->dir[bank] & bit)
77 val = dev->dat_out[bank];
78 else
79 val = adp5588_gpio_read(dev->client, GPIO_DAT_STAT1 + bank);
80
81 mutex_unlock(&dev->lock);
82
83 return !!(val & bit);
73} 84}
74 85
75static void adp5588_gpio_set_value(struct gpio_chip *chip, 86static void adp5588_gpio_set_value(struct gpio_chip *chip,
@@ -386,6 +397,7 @@ static int adp5588_gpio_probe(struct i2c_client *client,
386 gc->ngpio = ADP5588_MAXGPIO; 397 gc->ngpio = ADP5588_MAXGPIO;
387 gc->label = client->name; 398 gc->label = client->name;
388 gc->owner = THIS_MODULE; 399 gc->owner = THIS_MODULE;
400 gc->names = pdata->names;
389 401
390 mutex_init(&dev->lock); 402 mutex_init(&dev->lock);
391 403
diff --git a/drivers/gpio/gpio-bcm-kona.c b/drivers/gpio/gpio-bcm-kona.c
index f32357e2d78d..3f6b33ce9bd4 100644
--- a/drivers/gpio/gpio-bcm-kona.c
+++ b/drivers/gpio/gpio-bcm-kona.c
@@ -28,6 +28,10 @@
28#define GPIO_BANK(gpio) ((gpio) >> 5) 28#define GPIO_BANK(gpio) ((gpio) >> 5)
29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) 29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
30 30
31/* There is a GPIO control register for each GPIO */
32#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
33
34/* The remaining registers are per GPIO bank */
31#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) 35#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
32#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) 36#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
33#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) 37#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
@@ -35,7 +39,6 @@
35#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) 39#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
36#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) 40#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
37#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) 41#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
38#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
39#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) 42#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
40 43
41#define GPIO_GPPWR_OFFSET 0x00000520 44#define GPIO_GPPWR_OFFSET 0x00000520
@@ -80,22 +83,43 @@ static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
80 return container_of(chip, struct bcm_kona_gpio, gpio_chip); 83 return container_of(chip, struct bcm_kona_gpio, gpio_chip);
81} 84}
82 85
83static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base, 86static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
84 int bank_id, int lockcode) 87 int bank_id, u32 lockcode)
85{ 88{
86 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); 89 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
87 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); 90 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
88} 91}
89 92
90static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id) 93static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
94 unsigned gpio)
91{ 95{
92 bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE); 96 u32 val;
97 unsigned long flags;
98 int bank_id = GPIO_BANK(gpio);
99
100 spin_lock_irqsave(&kona_gpio->lock, flags);
101
102 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
103 val |= BIT(gpio);
104 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
105
106 spin_unlock_irqrestore(&kona_gpio->lock, flags);
93} 107}
94 108
95static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base, 109static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
96 int bank_id) 110 unsigned gpio)
97{ 111{
98 bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE); 112 u32 val;
113 unsigned long flags;
114 int bank_id = GPIO_BANK(gpio);
115
116 spin_lock_irqsave(&kona_gpio->lock, flags);
117
118 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
119 val &= ~BIT(gpio);
120 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
121
122 spin_unlock_irqrestore(&kona_gpio->lock, flags);
99} 123}
100 124
101static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 125static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
@@ -110,7 +134,6 @@ static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
110 kona_gpio = to_kona_gpio(chip); 134 kona_gpio = to_kona_gpio(chip);
111 reg_base = kona_gpio->reg_base; 135 reg_base = kona_gpio->reg_base;
112 spin_lock_irqsave(&kona_gpio->lock, flags); 136 spin_lock_irqsave(&kona_gpio->lock, flags);
113 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
114 137
115 /* determine the GPIO pin direction */ 138 /* determine the GPIO pin direction */
116 val = readl(reg_base + GPIO_CONTROL(gpio)); 139 val = readl(reg_base + GPIO_CONTROL(gpio));
@@ -127,7 +150,6 @@ static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
127 writel(val, reg_base + reg_offset); 150 writel(val, reg_base + reg_offset);
128 151
129out: 152out:
130 bcm_kona_gpio_lock_bank(reg_base, bank_id);
131 spin_unlock_irqrestore(&kona_gpio->lock, flags); 153 spin_unlock_irqrestore(&kona_gpio->lock, flags);
132} 154}
133 155
@@ -143,7 +165,6 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
143 kona_gpio = to_kona_gpio(chip); 165 kona_gpio = to_kona_gpio(chip);
144 reg_base = kona_gpio->reg_base; 166 reg_base = kona_gpio->reg_base;
145 spin_lock_irqsave(&kona_gpio->lock, flags); 167 spin_lock_irqsave(&kona_gpio->lock, flags);
146 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
147 168
148 /* determine the GPIO pin direction */ 169 /* determine the GPIO pin direction */
149 val = readl(reg_base + GPIO_CONTROL(gpio)); 170 val = readl(reg_base + GPIO_CONTROL(gpio));
@@ -154,32 +175,43 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
154 GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); 175 GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
155 val = readl(reg_base + reg_offset); 176 val = readl(reg_base + reg_offset);
156 177
157 bcm_kona_gpio_lock_bank(reg_base, bank_id);
158 spin_unlock_irqrestore(&kona_gpio->lock, flags); 178 spin_unlock_irqrestore(&kona_gpio->lock, flags);
159 179
160 /* return the specified bit status */ 180 /* return the specified bit status */
161 return !!(val & BIT(bit)); 181 return !!(val & BIT(bit));
162} 182}
163 183
184static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
185{
186 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
187
188 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
189 return 0;
190}
191
192static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
193{
194 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
195
196 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
197}
198
164static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 199static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
165{ 200{
166 struct bcm_kona_gpio *kona_gpio; 201 struct bcm_kona_gpio *kona_gpio;
167 void __iomem *reg_base; 202 void __iomem *reg_base;
168 u32 val; 203 u32 val;
169 unsigned long flags; 204 unsigned long flags;
170 int bank_id = GPIO_BANK(gpio);
171 205
172 kona_gpio = to_kona_gpio(chip); 206 kona_gpio = to_kona_gpio(chip);
173 reg_base = kona_gpio->reg_base; 207 reg_base = kona_gpio->reg_base;
174 spin_lock_irqsave(&kona_gpio->lock, flags); 208 spin_lock_irqsave(&kona_gpio->lock, flags);
175 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
176 209
177 val = readl(reg_base + GPIO_CONTROL(gpio)); 210 val = readl(reg_base + GPIO_CONTROL(gpio));
178 val &= ~GPIO_GPCTR0_IOTR_MASK; 211 val &= ~GPIO_GPCTR0_IOTR_MASK;
179 val |= GPIO_GPCTR0_IOTR_CMD_INPUT; 212 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
180 writel(val, reg_base + GPIO_CONTROL(gpio)); 213 writel(val, reg_base + GPIO_CONTROL(gpio));
181 214
182 bcm_kona_gpio_lock_bank(reg_base, bank_id);
183 spin_unlock_irqrestore(&kona_gpio->lock, flags); 215 spin_unlock_irqrestore(&kona_gpio->lock, flags);
184 216
185 return 0; 217 return 0;
@@ -198,7 +230,6 @@ static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
198 kona_gpio = to_kona_gpio(chip); 230 kona_gpio = to_kona_gpio(chip);
199 reg_base = kona_gpio->reg_base; 231 reg_base = kona_gpio->reg_base;
200 spin_lock_irqsave(&kona_gpio->lock, flags); 232 spin_lock_irqsave(&kona_gpio->lock, flags);
201 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
202 233
203 val = readl(reg_base + GPIO_CONTROL(gpio)); 234 val = readl(reg_base + GPIO_CONTROL(gpio));
204 val &= ~GPIO_GPCTR0_IOTR_MASK; 235 val &= ~GPIO_GPCTR0_IOTR_MASK;
@@ -210,7 +241,6 @@ static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
210 val |= BIT(bit); 241 val |= BIT(bit);
211 writel(val, reg_base + reg_offset); 242 writel(val, reg_base + reg_offset);
212 243
213 bcm_kona_gpio_lock_bank(reg_base, bank_id);
214 spin_unlock_irqrestore(&kona_gpio->lock, flags); 244 spin_unlock_irqrestore(&kona_gpio->lock, flags);
215 245
216 return 0; 246 return 0;
@@ -233,7 +263,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
233 void __iomem *reg_base; 263 void __iomem *reg_base;
234 u32 val, res; 264 u32 val, res;
235 unsigned long flags; 265 unsigned long flags;
236 int bank_id = GPIO_BANK(gpio);
237 266
238 kona_gpio = to_kona_gpio(chip); 267 kona_gpio = to_kona_gpio(chip);
239 reg_base = kona_gpio->reg_base; 268 reg_base = kona_gpio->reg_base;
@@ -257,7 +286,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
257 286
258 /* spin lock for read-modify-write of the GPIO register */ 287 /* spin lock for read-modify-write of the GPIO register */
259 spin_lock_irqsave(&kona_gpio->lock, flags); 288 spin_lock_irqsave(&kona_gpio->lock, flags);
260 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
261 289
262 val = readl(reg_base + GPIO_CONTROL(gpio)); 290 val = readl(reg_base + GPIO_CONTROL(gpio));
263 val &= ~GPIO_GPCTR0_DBR_MASK; 291 val &= ~GPIO_GPCTR0_DBR_MASK;
@@ -272,7 +300,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
272 300
273 writel(val, reg_base + GPIO_CONTROL(gpio)); 301 writel(val, reg_base + GPIO_CONTROL(gpio));
274 302
275 bcm_kona_gpio_lock_bank(reg_base, bank_id);
276 spin_unlock_irqrestore(&kona_gpio->lock, flags); 303 spin_unlock_irqrestore(&kona_gpio->lock, flags);
277 304
278 return 0; 305 return 0;
@@ -281,6 +308,8 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
281static struct gpio_chip template_chip = { 308static struct gpio_chip template_chip = {
282 .label = "bcm-kona-gpio", 309 .label = "bcm-kona-gpio",
283 .owner = THIS_MODULE, 310 .owner = THIS_MODULE,
311 .request = bcm_kona_gpio_request,
312 .free = bcm_kona_gpio_free,
284 .direction_input = bcm_kona_gpio_direction_input, 313 .direction_input = bcm_kona_gpio_direction_input,
285 .get = bcm_kona_gpio_get, 314 .get = bcm_kona_gpio_get,
286 .direction_output = bcm_kona_gpio_direction_output, 315 .direction_output = bcm_kona_gpio_direction_output,
@@ -294,7 +323,7 @@ static void bcm_kona_gpio_irq_ack(struct irq_data *d)
294{ 323{
295 struct bcm_kona_gpio *kona_gpio; 324 struct bcm_kona_gpio *kona_gpio;
296 void __iomem *reg_base; 325 void __iomem *reg_base;
297 int gpio = d->hwirq; 326 unsigned gpio = d->hwirq;
298 int bank_id = GPIO_BANK(gpio); 327 int bank_id = GPIO_BANK(gpio);
299 int bit = GPIO_BIT(gpio); 328 int bit = GPIO_BIT(gpio);
300 u32 val; 329 u32 val;
@@ -303,13 +332,11 @@ static void bcm_kona_gpio_irq_ack(struct irq_data *d)
303 kona_gpio = irq_data_get_irq_chip_data(d); 332 kona_gpio = irq_data_get_irq_chip_data(d);
304 reg_base = kona_gpio->reg_base; 333 reg_base = kona_gpio->reg_base;
305 spin_lock_irqsave(&kona_gpio->lock, flags); 334 spin_lock_irqsave(&kona_gpio->lock, flags);
306 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
307 335
308 val = readl(reg_base + GPIO_INT_STATUS(bank_id)); 336 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
309 val |= BIT(bit); 337 val |= BIT(bit);
310 writel(val, reg_base + GPIO_INT_STATUS(bank_id)); 338 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
311 339
312 bcm_kona_gpio_lock_bank(reg_base, bank_id);
313 spin_unlock_irqrestore(&kona_gpio->lock, flags); 340 spin_unlock_irqrestore(&kona_gpio->lock, flags);
314} 341}
315 342
@@ -317,7 +344,7 @@ static void bcm_kona_gpio_irq_mask(struct irq_data *d)
317{ 344{
318 struct bcm_kona_gpio *kona_gpio; 345 struct bcm_kona_gpio *kona_gpio;
319 void __iomem *reg_base; 346 void __iomem *reg_base;
320 int gpio = d->hwirq; 347 unsigned gpio = d->hwirq;
321 int bank_id = GPIO_BANK(gpio); 348 int bank_id = GPIO_BANK(gpio);
322 int bit = GPIO_BIT(gpio); 349 int bit = GPIO_BIT(gpio);
323 u32 val; 350 u32 val;
@@ -326,13 +353,11 @@ static void bcm_kona_gpio_irq_mask(struct irq_data *d)
326 kona_gpio = irq_data_get_irq_chip_data(d); 353 kona_gpio = irq_data_get_irq_chip_data(d);
327 reg_base = kona_gpio->reg_base; 354 reg_base = kona_gpio->reg_base;
328 spin_lock_irqsave(&kona_gpio->lock, flags); 355 spin_lock_irqsave(&kona_gpio->lock, flags);
329 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
330 356
331 val = readl(reg_base + GPIO_INT_MASK(bank_id)); 357 val = readl(reg_base + GPIO_INT_MASK(bank_id));
332 val |= BIT(bit); 358 val |= BIT(bit);
333 writel(val, reg_base + GPIO_INT_MASK(bank_id)); 359 writel(val, reg_base + GPIO_INT_MASK(bank_id));
334 360
335 bcm_kona_gpio_lock_bank(reg_base, bank_id);
336 spin_unlock_irqrestore(&kona_gpio->lock, flags); 361 spin_unlock_irqrestore(&kona_gpio->lock, flags);
337} 362}
338 363
@@ -340,7 +365,7 @@ static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
340{ 365{
341 struct bcm_kona_gpio *kona_gpio; 366 struct bcm_kona_gpio *kona_gpio;
342 void __iomem *reg_base; 367 void __iomem *reg_base;
343 int gpio = d->hwirq; 368 unsigned gpio = d->hwirq;
344 int bank_id = GPIO_BANK(gpio); 369 int bank_id = GPIO_BANK(gpio);
345 int bit = GPIO_BIT(gpio); 370 int bit = GPIO_BIT(gpio);
346 u32 val; 371 u32 val;
@@ -349,13 +374,11 @@ static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
349 kona_gpio = irq_data_get_irq_chip_data(d); 374 kona_gpio = irq_data_get_irq_chip_data(d);
350 reg_base = kona_gpio->reg_base; 375 reg_base = kona_gpio->reg_base;
351 spin_lock_irqsave(&kona_gpio->lock, flags); 376 spin_lock_irqsave(&kona_gpio->lock, flags);
352 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
353 377
354 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id)); 378 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
355 val |= BIT(bit); 379 val |= BIT(bit);
356 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); 380 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
357 381
358 bcm_kona_gpio_lock_bank(reg_base, bank_id);
359 spin_unlock_irqrestore(&kona_gpio->lock, flags); 382 spin_unlock_irqrestore(&kona_gpio->lock, flags);
360} 383}
361 384
@@ -363,11 +386,10 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
363{ 386{
364 struct bcm_kona_gpio *kona_gpio; 387 struct bcm_kona_gpio *kona_gpio;
365 void __iomem *reg_base; 388 void __iomem *reg_base;
366 int gpio = d->hwirq; 389 unsigned gpio = d->hwirq;
367 u32 lvl_type; 390 u32 lvl_type;
368 u32 val; 391 u32 val;
369 unsigned long flags; 392 unsigned long flags;
370 int bank_id = GPIO_BANK(gpio);
371 393
372 kona_gpio = irq_data_get_irq_chip_data(d); 394 kona_gpio = irq_data_get_irq_chip_data(d);
373 reg_base = kona_gpio->reg_base; 395 reg_base = kona_gpio->reg_base;
@@ -394,14 +416,12 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
394 } 416 }
395 417
396 spin_lock_irqsave(&kona_gpio->lock, flags); 418 spin_lock_irqsave(&kona_gpio->lock, flags);
397 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
398 419
399 val = readl(reg_base + GPIO_CONTROL(gpio)); 420 val = readl(reg_base + GPIO_CONTROL(gpio));
400 val &= ~GPIO_GPCTR0_ITR_MASK; 421 val &= ~GPIO_GPCTR0_ITR_MASK;
401 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT; 422 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
402 writel(val, reg_base + GPIO_CONTROL(gpio)); 423 writel(val, reg_base + GPIO_CONTROL(gpio));
403 424
404 bcm_kona_gpio_lock_bank(reg_base, bank_id);
405 spin_unlock_irqrestore(&kona_gpio->lock, flags); 425 spin_unlock_irqrestore(&kona_gpio->lock, flags);
406 426
407 return 0; 427 return 0;
@@ -424,7 +444,6 @@ static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
424 */ 444 */
425 reg_base = bank->kona_gpio->reg_base; 445 reg_base = bank->kona_gpio->reg_base;
426 bank_id = bank->id; 446 bank_id = bank->id;
427 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
428 447
429 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) & 448 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
430 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) { 449 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
@@ -444,28 +463,26 @@ static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
444 } 463 }
445 } 464 }
446 465
447 bcm_kona_gpio_lock_bank(reg_base, bank_id);
448
449 chained_irq_exit(chip, desc); 466 chained_irq_exit(chip, desc);
450} 467}
451 468
452static unsigned int bcm_kona_gpio_irq_startup(struct irq_data *d) 469static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
453{ 470{
454 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d); 471 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
455 472
456 if (gpio_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) 473 if (gpio_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
457 dev_err(kona_gpio->gpio_chip.dev, 474 dev_err(kona_gpio->gpio_chip.dev,
458 "unable to lock HW IRQ %lu for IRQ\n", 475 "unable to lock HW IRQ %lu for IRQ\n",
459 d->hwirq); 476 d->hwirq);
460 bcm_kona_gpio_irq_unmask(d); 477 return -EINVAL;
478 }
461 return 0; 479 return 0;
462} 480}
463 481
464static void bcm_kona_gpio_irq_shutdown(struct irq_data *d) 482static void bcm_kona_gpio_irq_relres(struct irq_data *d)
465{ 483{
466 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d); 484 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
467 485
468 bcm_kona_gpio_irq_mask(d);
469 gpio_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq); 486 gpio_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
470} 487}
471 488
@@ -475,8 +492,8 @@ static struct irq_chip bcm_gpio_irq_chip = {
475 .irq_mask = bcm_kona_gpio_irq_mask, 492 .irq_mask = bcm_kona_gpio_irq_mask,
476 .irq_unmask = bcm_kona_gpio_irq_unmask, 493 .irq_unmask = bcm_kona_gpio_irq_unmask,
477 .irq_set_type = bcm_kona_gpio_irq_set_type, 494 .irq_set_type = bcm_kona_gpio_irq_set_type,
478 .irq_startup = bcm_kona_gpio_irq_startup, 495 .irq_request_resources = bcm_kona_gpio_irq_reqres,
479 .irq_shutdown = bcm_kona_gpio_irq_shutdown, 496 .irq_release_resources = bcm_kona_gpio_irq_relres,
480}; 497};
481 498
482static struct __initconst of_device_id bcm_kona_gpio_of_match[] = { 499static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
@@ -531,10 +548,12 @@ static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
531 reg_base = kona_gpio->reg_base; 548 reg_base = kona_gpio->reg_base;
532 /* disable interrupts and clear status */ 549 /* disable interrupts and clear status */
533 for (i = 0; i < kona_gpio->num_bank; i++) { 550 for (i = 0; i < kona_gpio->num_bank; i++) {
534 bcm_kona_gpio_unlock_bank(reg_base, i); 551 /* Unlock the entire bank first */
552 bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
535 writel(0xffffffff, reg_base + GPIO_INT_MASK(i)); 553 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
536 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i)); 554 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
537 bcm_kona_gpio_lock_bank(reg_base, i); 555 /* Now re-lock the bank */
556 bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
538 } 557 }
539} 558}
540 559
diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c
index 3c2ba2ad0ada..e1e861239e95 100644
--- a/drivers/gpio/gpio-clps711x.c
+++ b/drivers/gpio/gpio-clps711x.c
@@ -65,6 +65,7 @@ static int clps711x_gpio_probe(struct platform_device *pdev)
65 } 65 }
66 66
67 bgc->gc.base = id * 8; 67 bgc->gc.base = id * 8;
68 bgc->gc.owner = THIS_MODULE;
68 platform_set_drvdata(pdev, bgc); 69 platform_set_drvdata(pdev, bgc);
69 70
70 return gpiochip_add(&bgc->gc); 71 return gpiochip_add(&bgc->gc);
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index 7629b4f12b7f..339f9dac591b 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -37,6 +37,8 @@ struct davinci_gpio_regs {
37 u32 intstat; 37 u32 intstat;
38}; 38};
39 39
40typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
41
40#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ 42#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
41 43
42#define chip2controller(chip) \ 44#define chip2controller(chip) \
@@ -172,6 +174,27 @@ of_err:
172 return NULL; 174 return NULL;
173} 175}
174 176
177#ifdef CONFIG_OF_GPIO
178static int davinci_gpio_of_xlate(struct gpio_chip *gc,
179 const struct of_phandle_args *gpiospec,
180 u32 *flags)
181{
182 struct davinci_gpio_controller *chips = dev_get_drvdata(gc->dev);
183 struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->dev);
184
185 if (gpiospec->args[0] > pdata->ngpio)
186 return -EINVAL;
187
188 if (gc != &chips[gpiospec->args[0] / 32].chip)
189 return -EINVAL;
190
191 if (flags)
192 *flags = gpiospec->args[1];
193
194 return gpiospec->args[0] % 32;
195}
196#endif
197
175static int davinci_gpio_probe(struct platform_device *pdev) 198static int davinci_gpio_probe(struct platform_device *pdev)
176{ 199{
177 int i, base; 200 int i, base;
@@ -236,6 +259,9 @@ static int davinci_gpio_probe(struct platform_device *pdev)
236 chips[i].chip.ngpio = 32; 259 chips[i].chip.ngpio = 32;
237 260
238#ifdef CONFIG_OF_GPIO 261#ifdef CONFIG_OF_GPIO
262 chips[i].chip.of_gpio_n_cells = 2;
263 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
264 chips[i].chip.dev = dev;
239 chips[i].chip.of_node = dev->of_node; 265 chips[i].chip.of_node = dev->of_node;
240#endif 266#endif
241 spin_lock_init(&chips[i].lock); 267 spin_lock_init(&chips[i].lock);
@@ -413,6 +439,26 @@ static const struct irq_domain_ops davinci_gpio_irq_ops = {
413 .xlate = irq_domain_xlate_onetwocell, 439 .xlate = irq_domain_xlate_onetwocell,
414}; 440};
415 441
442static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
443{
444 static struct irq_chip_type gpio_unbanked;
445
446 gpio_unbanked = *container_of(irq_get_chip(irq),
447 struct irq_chip_type, chip);
448
449 return &gpio_unbanked.chip;
450};
451
452static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
453{
454 static struct irq_chip gpio_unbanked;
455
456 gpio_unbanked = *irq_get_chip(irq);
457 return &gpio_unbanked;
458};
459
460static const struct of_device_id davinci_gpio_ids[];
461
416/* 462/*
417 * NOTE: for suspend/resume, probably best to make a platform_device with 463 * NOTE: for suspend/resume, probably best to make a platform_device with
418 * suspend_late/resume_resume calls hooking into results of the set_wake() 464 * suspend_late/resume_resume calls hooking into results of the set_wake()
@@ -423,7 +469,8 @@ static const struct irq_domain_ops davinci_gpio_irq_ops = {
423 469
424static int davinci_gpio_irq_setup(struct platform_device *pdev) 470static int davinci_gpio_irq_setup(struct platform_device *pdev)
425{ 471{
426 unsigned gpio, irq, bank; 472 unsigned gpio, bank;
473 int irq;
427 struct clk *clk; 474 struct clk *clk;
428 u32 binten = 0; 475 u32 binten = 0;
429 unsigned ngpio, bank_irq; 476 unsigned ngpio, bank_irq;
@@ -433,6 +480,18 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
433 struct davinci_gpio_platform_data *pdata = dev->platform_data; 480 struct davinci_gpio_platform_data *pdata = dev->platform_data;
434 struct davinci_gpio_regs __iomem *g; 481 struct davinci_gpio_regs __iomem *g;
435 struct irq_domain *irq_domain = NULL; 482 struct irq_domain *irq_domain = NULL;
483 const struct of_device_id *match;
484 struct irq_chip *irq_chip;
485 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
486
487 /*
488 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
489 */
490 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
491 match = of_match_device(of_match_ptr(davinci_gpio_ids),
492 dev);
493 if (match)
494 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
436 495
437 ngpio = pdata->ngpio; 496 ngpio = pdata->ngpio;
438 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 497 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -489,8 +548,6 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
489 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. 548 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
490 */ 549 */
491 if (pdata->gpio_unbanked) { 550 if (pdata->gpio_unbanked) {
492 static struct irq_chip_type gpio_unbanked;
493
494 /* pass "bank 0" GPIO IRQs to AINTC */ 551 /* pass "bank 0" GPIO IRQs to AINTC */
495 chips[0].chip.to_irq = gpio_to_irq_unbanked; 552 chips[0].chip.to_irq = gpio_to_irq_unbanked;
496 chips[0].gpio_irq = bank_irq; 553 chips[0].gpio_irq = bank_irq;
@@ -499,10 +556,9 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
499 556
500 /* AINTC handles mask/unmask; GPIO handles triggering */ 557 /* AINTC handles mask/unmask; GPIO handles triggering */
501 irq = bank_irq; 558 irq = bank_irq;
502 gpio_unbanked = *container_of(irq_get_chip(irq), 559 irq_chip = gpio_get_irq_chip(irq);
503 struct irq_chip_type, chip); 560 irq_chip->name = "GPIO-AINTC";
504 gpio_unbanked.chip.name = "GPIO-AINTC"; 561 irq_chip->irq_set_type = gpio_irq_type_unbanked;
505 gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
506 562
507 /* default trigger: both edges */ 563 /* default trigger: both edges */
508 g = gpio2regs(0); 564 g = gpio2regs(0);
@@ -511,7 +567,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
511 567
512 /* set the direct IRQs up to use that irqchip */ 568 /* set the direct IRQs up to use that irqchip */
513 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { 569 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
514 irq_set_chip(irq, &gpio_unbanked.chip); 570 irq_set_chip(irq, irq_chip);
515 irq_set_handler_data(irq, &chips[gpio / 32]); 571 irq_set_handler_data(irq, &chips[gpio / 32]);
516 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); 572 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
517 } 573 }
@@ -554,7 +610,8 @@ done:
554 610
555#if IS_ENABLED(CONFIG_OF) 611#if IS_ENABLED(CONFIG_OF)
556static const struct of_device_id davinci_gpio_ids[] = { 612static const struct of_device_id davinci_gpio_ids[] = {
557 { .compatible = "ti,dm6441-gpio", }, 613 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
614 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
558 { /* sentinel */ }, 615 { /* sentinel */ },
559}; 616};
560MODULE_DEVICE_TABLE(of, davinci_gpio_ids); 617MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
new file mode 100644
index 000000000000..ed5711f77e2d
--- /dev/null
+++ b/drivers/gpio/gpio-dwapb.c
@@ -0,0 +1,438 @@
1/*
2 * Copyright (c) 2011 Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10#include <linux/basic_mmio_gpio.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <linux/platform_device.h>
23#include <linux/spinlock.h>
24
25#define GPIO_SWPORTA_DR 0x00
26#define GPIO_SWPORTA_DDR 0x04
27#define GPIO_SWPORTB_DR 0x0c
28#define GPIO_SWPORTB_DDR 0x10
29#define GPIO_SWPORTC_DR 0x18
30#define GPIO_SWPORTC_DDR 0x1c
31#define GPIO_SWPORTD_DR 0x24
32#define GPIO_SWPORTD_DDR 0x28
33#define GPIO_INTEN 0x30
34#define GPIO_INTMASK 0x34
35#define GPIO_INTTYPE_LEVEL 0x38
36#define GPIO_INT_POLARITY 0x3c
37#define GPIO_INTSTATUS 0x40
38#define GPIO_PORTA_EOI 0x4c
39#define GPIO_EXT_PORTA 0x50
40#define GPIO_EXT_PORTB 0x54
41#define GPIO_EXT_PORTC 0x58
42#define GPIO_EXT_PORTD 0x5c
43
44#define DWAPB_MAX_PORTS 4
45#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
46#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
47#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
48
49struct dwapb_gpio;
50
51struct dwapb_gpio_port {
52 struct bgpio_chip bgc;
53 bool is_registered;
54 struct dwapb_gpio *gpio;
55};
56
57struct dwapb_gpio {
58 struct device *dev;
59 void __iomem *regs;
60 struct dwapb_gpio_port *ports;
61 unsigned int nr_ports;
62 struct irq_domain *domain;
63};
64
65static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
66{
67 struct bgpio_chip *bgc = to_bgpio_chip(gc);
68 struct dwapb_gpio_port *port = container_of(bgc, struct
69 dwapb_gpio_port, bgc);
70 struct dwapb_gpio *gpio = port->gpio;
71
72 return irq_find_mapping(gpio->domain, offset);
73}
74
75static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
76{
77 u32 v = readl(gpio->regs + GPIO_INT_POLARITY);
78
79 if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
80 v &= ~BIT(offs);
81 else
82 v |= BIT(offs);
83
84 writel(v, gpio->regs + GPIO_INT_POLARITY);
85}
86
87static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
88{
89 struct dwapb_gpio *gpio = irq_get_handler_data(irq);
90 struct irq_chip *chip = irq_desc_get_chip(desc);
91 u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
92
93 while (irq_status) {
94 int hwirq = fls(irq_status) - 1;
95 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
96
97 generic_handle_irq(gpio_irq);
98 irq_status &= ~BIT(hwirq);
99
100 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
101 == IRQ_TYPE_EDGE_BOTH)
102 dwapb_toggle_trigger(gpio, hwirq);
103 }
104
105 if (chip->irq_eoi)
106 chip->irq_eoi(irq_desc_get_irq_data(desc));
107}
108
109static void dwapb_irq_enable(struct irq_data *d)
110{
111 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
112 struct dwapb_gpio *gpio = igc->private;
113 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
114 unsigned long flags;
115 u32 val;
116
117 spin_lock_irqsave(&bgc->lock, flags);
118 val = readl(gpio->regs + GPIO_INTEN);
119 val |= BIT(d->hwirq);
120 writel(val, gpio->regs + GPIO_INTEN);
121 spin_unlock_irqrestore(&bgc->lock, flags);
122}
123
124static void dwapb_irq_disable(struct irq_data *d)
125{
126 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
127 struct dwapb_gpio *gpio = igc->private;
128 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
129 unsigned long flags;
130 u32 val;
131
132 spin_lock_irqsave(&bgc->lock, flags);
133 val = readl(gpio->regs + GPIO_INTEN);
134 val &= ~BIT(d->hwirq);
135 writel(val, gpio->regs + GPIO_INTEN);
136 spin_unlock_irqrestore(&bgc->lock, flags);
137}
138
139static int dwapb_irq_reqres(struct irq_data *d)
140{
141 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
142 struct dwapb_gpio *gpio = igc->private;
143 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
144
145 if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
146 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
147 irqd_to_hwirq(d));
148 return -EINVAL;
149 }
150 return 0;
151}
152
153static void dwapb_irq_relres(struct irq_data *d)
154{
155 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
156 struct dwapb_gpio *gpio = igc->private;
157 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
158
159 gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
160}
161
162static int dwapb_irq_set_type(struct irq_data *d, u32 type)
163{
164 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
165 struct dwapb_gpio *gpio = igc->private;
166 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
167 int bit = d->hwirq;
168 unsigned long level, polarity, flags;
169
170 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
171 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
172 return -EINVAL;
173
174 spin_lock_irqsave(&bgc->lock, flags);
175 level = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
176 polarity = readl(gpio->regs + GPIO_INT_POLARITY);
177
178 switch (type) {
179 case IRQ_TYPE_EDGE_BOTH:
180 level |= BIT(bit);
181 dwapb_toggle_trigger(gpio, bit);
182 break;
183 case IRQ_TYPE_EDGE_RISING:
184 level |= BIT(bit);
185 polarity |= BIT(bit);
186 break;
187 case IRQ_TYPE_EDGE_FALLING:
188 level |= BIT(bit);
189 polarity &= ~BIT(bit);
190 break;
191 case IRQ_TYPE_LEVEL_HIGH:
192 level &= ~BIT(bit);
193 polarity |= BIT(bit);
194 break;
195 case IRQ_TYPE_LEVEL_LOW:
196 level &= ~BIT(bit);
197 polarity &= ~BIT(bit);
198 break;
199 }
200
201 writel(level, gpio->regs + GPIO_INTTYPE_LEVEL);
202 writel(polarity, gpio->regs + GPIO_INT_POLARITY);
203 spin_unlock_irqrestore(&bgc->lock, flags);
204
205 return 0;
206}
207
208static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
209 struct dwapb_gpio_port *port)
210{
211 struct gpio_chip *gc = &port->bgc.gc;
212 struct device_node *node = gc->of_node;
213 struct irq_chip_generic *irq_gc;
214 unsigned int hwirq, ngpio = gc->ngpio;
215 struct irq_chip_type *ct;
216 int err, irq;
217
218 irq = irq_of_parse_and_map(node, 0);
219 if (!irq) {
220 dev_warn(gpio->dev, "no irq for bank %s\n",
221 port->bgc.gc.of_node->full_name);
222 return;
223 }
224
225 gpio->domain = irq_domain_add_linear(node, ngpio,
226 &irq_generic_chip_ops, gpio);
227 if (!gpio->domain)
228 return;
229
230 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 1,
231 "gpio-dwapb", handle_level_irq,
232 IRQ_NOREQUEST, 0,
233 IRQ_GC_INIT_NESTED_LOCK);
234 if (err) {
235 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
236 irq_domain_remove(gpio->domain);
237 gpio->domain = NULL;
238 return;
239 }
240
241 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
242 if (!irq_gc) {
243 irq_domain_remove(gpio->domain);
244 gpio->domain = NULL;
245 return;
246 }
247
248 irq_gc->reg_base = gpio->regs;
249 irq_gc->private = gpio;
250
251 ct = irq_gc->chip_types;
252 ct->chip.irq_ack = irq_gc_ack_set_bit;
253 ct->chip.irq_mask = irq_gc_mask_set_bit;
254 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
255 ct->chip.irq_set_type = dwapb_irq_set_type;
256 ct->chip.irq_enable = dwapb_irq_enable;
257 ct->chip.irq_disable = dwapb_irq_disable;
258 ct->chip.irq_request_resources = dwapb_irq_reqres;
259 ct->chip.irq_release_resources = dwapb_irq_relres;
260 ct->regs.ack = GPIO_PORTA_EOI;
261 ct->regs.mask = GPIO_INTMASK;
262
263 irq_setup_generic_chip(irq_gc, IRQ_MSK(port->bgc.gc.ngpio),
264 IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
265
266 irq_set_chained_handler(irq, dwapb_irq_handler);
267 irq_set_handler_data(irq, gpio);
268
269 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
270 irq_create_mapping(gpio->domain, hwirq);
271
272 port->bgc.gc.to_irq = dwapb_gpio_to_irq;
273}
274
275static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
276{
277 struct dwapb_gpio_port *port = &gpio->ports[0];
278 struct gpio_chip *gc = &port->bgc.gc;
279 unsigned int ngpio = gc->ngpio;
280 irq_hw_number_t hwirq;
281
282 if (!gpio->domain)
283 return;
284
285 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
286 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
287
288 irq_domain_remove(gpio->domain);
289 gpio->domain = NULL;
290}
291
292static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
293 struct device_node *port_np,
294 unsigned int offs)
295{
296 struct dwapb_gpio_port *port;
297 u32 port_idx, ngpio;
298 void __iomem *dat, *set, *dirout;
299 int err;
300
301 if (of_property_read_u32(port_np, "reg", &port_idx) ||
302 port_idx >= DWAPB_MAX_PORTS) {
303 dev_err(gpio->dev, "missing/invalid port index for %s\n",
304 port_np->full_name);
305 return -EINVAL;
306 }
307
308 port = &gpio->ports[offs];
309 port->gpio = gpio;
310
311 if (of_property_read_u32(port_np, "snps,nr-gpios", &ngpio)) {
312 dev_info(gpio->dev, "failed to get number of gpios for %s\n",
313 port_np->full_name);
314 ngpio = 32;
315 }
316
317 dat = gpio->regs + GPIO_EXT_PORTA + (port_idx * GPIO_EXT_PORT_SIZE);
318 set = gpio->regs + GPIO_SWPORTA_DR + (port_idx * GPIO_SWPORT_DR_SIZE);
319 dirout = gpio->regs + GPIO_SWPORTA_DDR +
320 (port_idx * GPIO_SWPORT_DDR_SIZE);
321
322 err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
323 NULL, false);
324 if (err) {
325 dev_err(gpio->dev, "failed to init gpio chip for %s\n",
326 port_np->full_name);
327 return err;
328 }
329
330 port->bgc.gc.ngpio = ngpio;
331 port->bgc.gc.of_node = port_np;
332
333 /*
334 * Only port A can provide interrupts in all configurations of the IP.
335 */
336 if (port_idx == 0 &&
337 of_property_read_bool(port_np, "interrupt-controller"))
338 dwapb_configure_irqs(gpio, port);
339
340 err = gpiochip_add(&port->bgc.gc);
341 if (err)
342 dev_err(gpio->dev, "failed to register gpiochip for %s\n",
343 port_np->full_name);
344 else
345 port->is_registered = true;
346
347 return err;
348}
349
350static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
351{
352 unsigned int m;
353
354 for (m = 0; m < gpio->nr_ports; ++m)
355 if (gpio->ports[m].is_registered)
356 WARN_ON(gpiochip_remove(&gpio->ports[m].bgc.gc));
357}
358
359static int dwapb_gpio_probe(struct platform_device *pdev)
360{
361 struct resource *res;
362 struct dwapb_gpio *gpio;
363 struct device_node *np;
364 int err;
365 unsigned int offs = 0;
366
367 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
368 if (!gpio)
369 return -ENOMEM;
370 gpio->dev = &pdev->dev;
371
372 gpio->nr_ports = of_get_child_count(pdev->dev.of_node);
373 if (!gpio->nr_ports) {
374 err = -EINVAL;
375 goto out_err;
376 }
377 gpio->ports = devm_kzalloc(&pdev->dev, gpio->nr_ports *
378 sizeof(*gpio->ports), GFP_KERNEL);
379 if (!gpio->ports) {
380 err = -ENOMEM;
381 goto out_err;
382 }
383
384 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
385 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
386 if (IS_ERR(gpio->regs)) {
387 err = PTR_ERR(gpio->regs);
388 goto out_err;
389 }
390
391 for_each_child_of_node(pdev->dev.of_node, np) {
392 err = dwapb_gpio_add_port(gpio, np, offs++);
393 if (err)
394 goto out_unregister;
395 }
396 platform_set_drvdata(pdev, gpio);
397
398 return 0;
399
400out_unregister:
401 dwapb_gpio_unregister(gpio);
402 dwapb_irq_teardown(gpio);
403
404out_err:
405 return err;
406}
407
408static int dwapb_gpio_remove(struct platform_device *pdev)
409{
410 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
411
412 dwapb_gpio_unregister(gpio);
413 dwapb_irq_teardown(gpio);
414
415 return 0;
416}
417
418static const struct of_device_id dwapb_of_match[] = {
419 { .compatible = "snps,dw-apb-gpio" },
420 { /* Sentinel */ }
421};
422MODULE_DEVICE_TABLE(of, dwapb_of_match);
423
424static struct platform_driver dwapb_gpio_driver = {
425 .driver = {
426 .name = "gpio-dwapb",
427 .owner = THIS_MODULE,
428 .of_match_table = of_match_ptr(dwapb_of_match),
429 },
430 .probe = dwapb_gpio_probe,
431 .remove = dwapb_gpio_remove,
432};
433
434module_platform_driver(dwapb_gpio_driver);
435
436MODULE_LICENSE("GPL");
437MODULE_AUTHOR("Jamie Iles");
438MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c
index 1e98a9873967..8765bd6f48e1 100644
--- a/drivers/gpio/gpio-em.c
+++ b/drivers/gpio/gpio-em.c
@@ -99,23 +99,23 @@ static void em_gio_irq_enable(struct irq_data *d)
99 em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d))); 99 em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
100} 100}
101 101
102static unsigned int em_gio_irq_startup(struct irq_data *d) 102static int em_gio_irq_reqres(struct irq_data *d)
103{ 103{
104 struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 104 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
105 105
106 if (gpio_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) 106 if (gpio_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
107 dev_err(p->gpio_chip.dev, 107 dev_err(p->gpio_chip.dev,
108 "unable to lock HW IRQ %lu for IRQ\n", 108 "unable to lock HW IRQ %lu for IRQ\n",
109 irqd_to_hwirq(d)); 109 irqd_to_hwirq(d));
110 em_gio_irq_enable(d); 110 return -EINVAL;
111 }
111 return 0; 112 return 0;
112} 113}
113 114
114static void em_gio_irq_shutdown(struct irq_data *d) 115static void em_gio_irq_relres(struct irq_data *d)
115{ 116{
116 struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 117 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
117 118
118 em_gio_irq_disable(d);
119 gpio_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); 119 gpio_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
120} 120}
121 121
@@ -359,8 +359,8 @@ static int em_gio_probe(struct platform_device *pdev)
359 irq_chip->irq_mask = em_gio_irq_disable; 359 irq_chip->irq_mask = em_gio_irq_disable;
360 irq_chip->irq_unmask = em_gio_irq_enable; 360 irq_chip->irq_unmask = em_gio_irq_enable;
361 irq_chip->irq_set_type = em_gio_irq_set_type; 361 irq_chip->irq_set_type = em_gio_irq_set_type;
362 irq_chip->irq_startup = em_gio_irq_startup; 362 irq_chip->irq_request_resources = em_gio_irq_reqres;
363 irq_chip->irq_shutdown = em_gio_irq_shutdown; 363 irq_chip->irq_release_resources = em_gio_irq_relres;
364 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; 364 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
365 365
366 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 366 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
diff --git a/drivers/gpio/gpio-generic.c b/drivers/gpio/gpio-generic.c
index d2196bf73847..b5dff9e742f8 100644
--- a/drivers/gpio/gpio-generic.c
+++ b/drivers/gpio/gpio-generic.c
@@ -139,7 +139,7 @@ static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
139{ 139{
140 struct bgpio_chip *bgc = to_bgpio_chip(gc); 140 struct bgpio_chip *bgc = to_bgpio_chip(gc);
141 141
142 return bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio); 142 return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
143} 143}
144 144
145static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 145static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
@@ -488,7 +488,7 @@ static int bgpio_pdev_probe(struct platform_device *pdev)
488 void __iomem *dirout; 488 void __iomem *dirout;
489 void __iomem *dirin; 489 void __iomem *dirin;
490 unsigned long sz; 490 unsigned long sz;
491 unsigned long flags = 0; 491 unsigned long flags = pdev->id_entry->driver_data;
492 int err; 492 int err;
493 struct bgpio_chip *bgc; 493 struct bgpio_chip *bgc;
494 struct bgpio_pdata *pdata = dev_get_platdata(dev); 494 struct bgpio_pdata *pdata = dev_get_platdata(dev);
@@ -519,9 +519,6 @@ static int bgpio_pdev_probe(struct platform_device *pdev)
519 if (err) 519 if (err)
520 return err; 520 return err;
521 521
522 if (!strcmp(platform_get_device_id(pdev)->name, "basic-mmio-gpio-be"))
523 flags |= BGPIOF_BIG_ENDIAN;
524
525 bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL); 522 bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
526 if (!bgc) 523 if (!bgc)
527 return -ENOMEM; 524 return -ENOMEM;
@@ -531,6 +528,8 @@ static int bgpio_pdev_probe(struct platform_device *pdev)
531 return err; 528 return err;
532 529
533 if (pdata) { 530 if (pdata) {
531 if (pdata->label)
532 bgc->gc.label = pdata->label;
534 bgc->gc.base = pdata->base; 533 bgc->gc.base = pdata->base;
535 if (pdata->ngpio > 0) 534 if (pdata->ngpio > 0)
536 bgc->gc.ngpio = pdata->ngpio; 535 bgc->gc.ngpio = pdata->ngpio;
@@ -549,9 +548,14 @@ static int bgpio_pdev_remove(struct platform_device *pdev)
549} 548}
550 549
551static const struct platform_device_id bgpio_id_table[] = { 550static const struct platform_device_id bgpio_id_table[] = {
552 { "basic-mmio-gpio", }, 551 {
553 { "basic-mmio-gpio-be", }, 552 .name = "basic-mmio-gpio",
554 {}, 553 .driver_data = 0,
554 }, {
555 .name = "basic-mmio-gpio-be",
556 .driver_data = BGPIOF_BIG_ENDIAN,
557 },
558 { }
555}; 559};
556MODULE_DEVICE_TABLE(platform, bgpio_id_table); 560MODULE_DEVICE_TABLE(platform, bgpio_id_table);
557 561
diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index f5bf3c38bca6..70304220a479 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Intel ICH6-10, Series 5 and 6 GPIO driver 2 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
3 * 3 *
4 * Copyright (C) 2010 Extreme Engineering Solutions. 4 * Copyright (C) 2010 Extreme Engineering Solutions.
5 * 5 *
@@ -55,6 +55,16 @@ static const u8 ichx_reglen[3] = {
55 0x30, 0x10, 0x10, 55 0x30, 0x10, 0x10,
56}; 56};
57 57
58static const u8 avoton_regs[4][3] = {
59 {0x00, 0x80, 0x00},
60 {0x04, 0x84, 0x00},
61 {0x08, 0x88, 0x00},
62};
63
64static const u8 avoton_reglen[3] = {
65 0x10, 0x10, 0x00,
66};
67
58#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) 68#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
59#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) 69#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
60 70
@@ -62,6 +72,13 @@ struct ichx_desc {
62 /* Max GPIO pins the chipset can have */ 72 /* Max GPIO pins the chipset can have */
63 uint ngpio; 73 uint ngpio;
64 74
75 /* chipset registers */
76 const u8 (*regs)[3];
77 const u8 *reglen;
78
79 /* GPO_BLINK is available on this chipset */
80 bool have_blink;
81
65 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ 82 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
66 bool uses_gpe0; 83 bool uses_gpe0;
67 84
@@ -71,6 +88,12 @@ struct ichx_desc {
71 /* Some chipsets have quirks, let these use their own request/get */ 88 /* Some chipsets have quirks, let these use their own request/get */
72 int (*request)(struct gpio_chip *chip, unsigned offset); 89 int (*request)(struct gpio_chip *chip, unsigned offset);
73 int (*get)(struct gpio_chip *chip, unsigned offset); 90 int (*get)(struct gpio_chip *chip, unsigned offset);
91
92 /*
93 * Some chipsets don't let reading output values on GPIO_LVL register
94 * this option allows driver caching written output values
95 */
96 bool use_outlvl_cache;
74}; 97};
75 98
76static struct { 99static struct {
@@ -82,6 +105,7 @@ static struct {
82 struct ichx_desc *desc; /* Pointer to chipset-specific description */ 105 struct ichx_desc *desc; /* Pointer to chipset-specific description */
83 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */ 106 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
84 u8 use_gpio; /* Which GPIO groups are usable */ 107 u8 use_gpio; /* Which GPIO groups are usable */
108 int outlvl_cache[3]; /* cached output values */
85} ichx_priv; 109} ichx_priv;
86 110
87static int modparam_gpiobase = -1; /* dynamic */ 111static int modparam_gpiobase = -1; /* dynamic */
@@ -99,13 +123,23 @@ static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
99 123
100 spin_lock_irqsave(&ichx_priv.lock, flags); 124 spin_lock_irqsave(&ichx_priv.lock, flags);
101 125
102 data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base); 126 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
127 data = ichx_priv.outlvl_cache[reg_nr];
128 else
129 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
130 ichx_priv.gpio_base);
131
103 if (val) 132 if (val)
104 data |= 1 << bit; 133 data |= 1 << bit;
105 else 134 else
106 data &= ~(1 << bit); 135 data &= ~(1 << bit);
107 ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base); 136 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
108 tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base); 137 ichx_priv.gpio_base);
138 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
139 ichx_priv.outlvl_cache[reg_nr] = data;
140
141 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
142 ichx_priv.gpio_base);
109 if (verify && data != tmp) 143 if (verify && data != tmp)
110 ret = -EPERM; 144 ret = -EPERM;
111 145
@@ -123,7 +157,11 @@ static int ichx_read_bit(int reg, unsigned nr)
123 157
124 spin_lock_irqsave(&ichx_priv.lock, flags); 158 spin_lock_irqsave(&ichx_priv.lock, flags);
125 159
126 data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base); 160 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
161 ichx_priv.gpio_base);
162
163 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
164 data = ichx_priv.outlvl_cache[reg_nr] | data;
127 165
128 spin_unlock_irqrestore(&ichx_priv.lock, flags); 166 spin_unlock_irqrestore(&ichx_priv.lock, flags);
129 167
@@ -151,7 +189,7 @@ static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
151 int val) 189 int val)
152{ 190{
153 /* Disable blink hardware which is available for GPIOs from 0 to 31. */ 191 /* Disable blink hardware which is available for GPIOs from 0 to 31. */
154 if (nr < 32) 192 if (nr < 32 && ichx_priv.desc->have_blink)
155 ichx_write_bit(GPO_BLINK, nr, 0, 0); 193 ichx_write_bit(GPO_BLINK, nr, 0, 0);
156 194
157 /* Set GPIO output value. */ 195 /* Set GPIO output value. */
@@ -266,6 +304,9 @@ static struct ichx_desc ich6_desc = {
266 .uses_gpe0 = true, 304 .uses_gpe0 = true,
267 305
268 .ngpio = 50, 306 .ngpio = 50,
307 .have_blink = true,
308 .regs = ichx_regs,
309 .reglen = ichx_reglen,
269}; 310};
270 311
271/* Intel 3100 */ 312/* Intel 3100 */
@@ -285,29 +326,56 @@ static struct ichx_desc i3100_desc = {
285 .uses_gpe0 = true, 326 .uses_gpe0 = true,
286 327
287 .ngpio = 50, 328 .ngpio = 50,
329 .regs = ichx_regs,
330 .reglen = ichx_reglen,
288}; 331};
289 332
290/* ICH7 and ICH8-based */ 333/* ICH7 and ICH8-based */
291static struct ichx_desc ich7_desc = { 334static struct ichx_desc ich7_desc = {
292 .ngpio = 50, 335 .ngpio = 50,
336 .have_blink = true,
337 .regs = ichx_regs,
338 .reglen = ichx_reglen,
293}; 339};
294 340
295/* ICH9-based */ 341/* ICH9-based */
296static struct ichx_desc ich9_desc = { 342static struct ichx_desc ich9_desc = {
297 .ngpio = 61, 343 .ngpio = 61,
344 .have_blink = true,
345 .regs = ichx_regs,
346 .reglen = ichx_reglen,
298}; 347};
299 348
300/* ICH10-based - Consumer/corporate versions have different amount of GPIO */ 349/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
301static struct ichx_desc ich10_cons_desc = { 350static struct ichx_desc ich10_cons_desc = {
302 .ngpio = 61, 351 .ngpio = 61,
352 .have_blink = true,
353 .regs = ichx_regs,
354 .reglen = ichx_reglen,
303}; 355};
304static struct ichx_desc ich10_corp_desc = { 356static struct ichx_desc ich10_corp_desc = {
305 .ngpio = 72, 357 .ngpio = 72,
358 .have_blink = true,
359 .regs = ichx_regs,
360 .reglen = ichx_reglen,
306}; 361};
307 362
308/* Intel 5 series, 6 series, 3400 series, and C200 series */ 363/* Intel 5 series, 6 series, 3400 series, and C200 series */
309static struct ichx_desc intel5_desc = { 364static struct ichx_desc intel5_desc = {
310 .ngpio = 76, 365 .ngpio = 76,
366 .regs = ichx_regs,
367 .reglen = ichx_reglen,
368};
369
370/* Avoton */
371static struct ichx_desc avoton_desc = {
372 /* Avoton has only 59 GPIOs, but we assume the first set of register
373 * (Core) has 32 instead of 31 to keep gpio-ich compliance
374 */
375 .ngpio = 60,
376 .regs = avoton_regs,
377 .reglen = avoton_reglen,
378 .use_outlvl_cache = true,
311}; 379};
312 380
313static int ichx_gpio_request_regions(struct resource *res_base, 381static int ichx_gpio_request_regions(struct resource *res_base,
@@ -318,11 +386,12 @@ static int ichx_gpio_request_regions(struct resource *res_base,
318 if (!res_base || !res_base->start || !res_base->end) 386 if (!res_base || !res_base->start || !res_base->end)
319 return -ENODEV; 387 return -ENODEV;
320 388
321 for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) { 389 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
322 if (!(use_gpio & (1 << i))) 390 if (!(use_gpio & (1 << i)))
323 continue; 391 continue;
324 if (!request_region(res_base->start + ichx_regs[0][i], 392 if (!request_region(
325 ichx_reglen[i], name)) 393 res_base->start + ichx_priv.desc->regs[0][i],
394 ichx_priv.desc->reglen[i], name))
326 goto request_err; 395 goto request_err;
327 } 396 }
328 return 0; 397 return 0;
@@ -332,8 +401,8 @@ request_err:
332 for (i--; i >= 0; i--) { 401 for (i--; i >= 0; i--) {
333 if (!(use_gpio & (1 << i))) 402 if (!(use_gpio & (1 << i)))
334 continue; 403 continue;
335 release_region(res_base->start + ichx_regs[0][i], 404 release_region(res_base->start + ichx_priv.desc->regs[0][i],
336 ichx_reglen[i]); 405 ichx_priv.desc->reglen[i]);
337 } 406 }
338 return -EBUSY; 407 return -EBUSY;
339} 408}
@@ -342,11 +411,11 @@ static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
342{ 411{
343 int i; 412 int i;
344 413
345 for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) { 414 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
346 if (!(use_gpio & (1 << i))) 415 if (!(use_gpio & (1 << i)))
347 continue; 416 continue;
348 release_region(res_base->start + ichx_regs[0][i], 417 release_region(res_base->start + ichx_priv.desc->regs[0][i],
349 ichx_reglen[i]); 418 ichx_priv.desc->reglen[i]);
350 } 419 }
351} 420}
352 421
@@ -383,6 +452,9 @@ static int ichx_gpio_probe(struct platform_device *pdev)
383 case ICH_V10CONS_GPIO: 452 case ICH_V10CONS_GPIO:
384 ichx_priv.desc = &ich10_cons_desc; 453 ichx_priv.desc = &ich10_cons_desc;
385 break; 454 break;
455 case AVOTON_GPIO:
456 ichx_priv.desc = &avoton_desc;
457 break;
386 default: 458 default:
387 return -ENODEV; 459 return -ENODEV;
388 } 460 }
diff --git a/drivers/gpio/gpio-intel-mid.c b/drivers/gpio/gpio-intel-mid.c
index e585163f1ad5..118a6bf455d9 100644
--- a/drivers/gpio/gpio-intel-mid.c
+++ b/drivers/gpio/gpio-intel-mid.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Moorestown platform Langwell chip GPIO driver 2 * Intel MID GPIO driver
3 * 3 *
4 * Copyright (c) 2008, 2009, 2013, Intel Corporation. 4 * Copyright (c) 2008-2014 Intel Corporation.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 14 */
19 15
20/* Supports: 16/* Supports:
@@ -235,23 +231,23 @@ static void intel_mid_irq_mask(struct irq_data *d)
235{ 231{
236} 232}
237 233
238static unsigned int intel_mid_irq_startup(struct irq_data *d) 234static int intel_mid_irq_reqres(struct irq_data *d)
239{ 235{
240 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); 236 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
241 237
242 if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) 238 if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) {
243 dev_err(priv->chip.dev, 239 dev_err(priv->chip.dev,
244 "unable to lock HW IRQ %lu for IRQ\n", 240 "unable to lock HW IRQ %lu for IRQ\n",
245 irqd_to_hwirq(d)); 241 irqd_to_hwirq(d));
246 intel_mid_irq_unmask(d); 242 return -EINVAL;
243 }
247 return 0; 244 return 0;
248} 245}
249 246
250static void intel_mid_irq_shutdown(struct irq_data *d) 247static void intel_mid_irq_relres(struct irq_data *d)
251{ 248{
252 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); 249 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
253 250
254 intel_mid_irq_mask(d);
255 gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d)); 251 gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
256} 252}
257 253
@@ -260,8 +256,8 @@ static struct irq_chip intel_mid_irqchip = {
260 .irq_mask = intel_mid_irq_mask, 256 .irq_mask = intel_mid_irq_mask,
261 .irq_unmask = intel_mid_irq_unmask, 257 .irq_unmask = intel_mid_irq_unmask,
262 .irq_set_type = intel_mid_irq_type, 258 .irq_set_type = intel_mid_irq_type,
263 .irq_startup = intel_mid_irq_startup, 259 .irq_request_resources = intel_mid_irq_reqres,
264 .irq_shutdown = intel_mid_irq_shutdown, 260 .irq_release_resources = intel_mid_irq_relres,
265}; 261};
266 262
267static const struct intel_mid_gpio_ddata gpio_lincroft = { 263static const struct intel_mid_gpio_ddata gpio_lincroft = {
diff --git a/drivers/gpio/gpio-iop.c b/drivers/gpio/gpio-iop.c
index c22a61be3a9c..0a5e9d3f308c 100644
--- a/drivers/gpio/gpio-iop.c
+++ b/drivers/gpio/gpio-iop.c
@@ -111,6 +111,8 @@ static int iop3xx_gpio_probe(struct platform_device *pdev)
111 111
112 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 112 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
113 base = devm_ioremap_resource(&pdev->dev, res); 113 base = devm_ioremap_resource(&pdev->dev, res);
114 if (IS_ERR(base))
115 return PTR_ERR(base);
114 116
115 return gpiochip_add(&iop3xx_chip); 117 return gpiochip_add(&iop3xx_chip);
116} 118}
diff --git a/drivers/gpio/gpio-lynxpoint.c b/drivers/gpio/gpio-lynxpoint.c
index 66b18535b5ae..9a82a9074a2c 100644
--- a/drivers/gpio/gpio-lynxpoint.c
+++ b/drivers/gpio/gpio-lynxpoint.c
@@ -188,7 +188,7 @@ static int lp_irq_type(struct irq_data *d, unsigned type)
188static int lp_gpio_get(struct gpio_chip *chip, unsigned offset) 188static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
189{ 189{
190 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 190 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
191 return inl(reg) & IN_LVL_BIT; 191 return !!(inl(reg) & IN_LVL_BIT);
192} 192}
193 193
194static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 194static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -301,23 +301,23 @@ static void lp_irq_disable(struct irq_data *d)
301 spin_unlock_irqrestore(&lg->lock, flags); 301 spin_unlock_irqrestore(&lg->lock, flags);
302} 302}
303 303
304static unsigned int lp_irq_startup(struct irq_data *d) 304static int lp_irq_reqres(struct irq_data *d)
305{ 305{
306 struct lp_gpio *lg = irq_data_get_irq_chip_data(d); 306 struct lp_gpio *lg = irq_data_get_irq_chip_data(d);
307 307
308 if (gpio_lock_as_irq(&lg->chip, irqd_to_hwirq(d))) 308 if (gpio_lock_as_irq(&lg->chip, irqd_to_hwirq(d))) {
309 dev_err(lg->chip.dev, 309 dev_err(lg->chip.dev,
310 "unable to lock HW IRQ %lu for IRQ\n", 310 "unable to lock HW IRQ %lu for IRQ\n",
311 irqd_to_hwirq(d)); 311 irqd_to_hwirq(d));
312 lp_irq_enable(d); 312 return -EINVAL;
313 }
313 return 0; 314 return 0;
314} 315}
315 316
316static void lp_irq_shutdown(struct irq_data *d) 317static void lp_irq_relres(struct irq_data *d)
317{ 318{
318 struct lp_gpio *lg = irq_data_get_irq_chip_data(d); 319 struct lp_gpio *lg = irq_data_get_irq_chip_data(d);
319 320
320 lp_irq_disable(d);
321 gpio_unlock_as_irq(&lg->chip, irqd_to_hwirq(d)); 321 gpio_unlock_as_irq(&lg->chip, irqd_to_hwirq(d));
322} 322}
323 323
@@ -328,8 +328,8 @@ static struct irq_chip lp_irqchip = {
328 .irq_enable = lp_irq_enable, 328 .irq_enable = lp_irq_enable,
329 .irq_disable = lp_irq_disable, 329 .irq_disable = lp_irq_disable,
330 .irq_set_type = lp_irq_type, 330 .irq_set_type = lp_irq_type,
331 .irq_startup = lp_irq_startup, 331 .irq_request_resources = lp_irq_reqres,
332 .irq_shutdown = lp_irq_shutdown, 332 .irq_release_resources = lp_irq_relres,
333 .flags = IRQCHIP_SKIP_SET_WAKE, 333 .flags = IRQCHIP_SKIP_SET_WAKE,
334}; 334};
335 335
diff --git a/drivers/gpio/gpio-max732x.c b/drivers/gpio/gpio-max732x.c
index 36cb290764b6..7c36f2b0983d 100644
--- a/drivers/gpio/gpio-max732x.c
+++ b/drivers/gpio/gpio-max732x.c
@@ -622,6 +622,13 @@ static int max732x_probe(struct i2c_client *client,
622 goto out_failed; 622 goto out_failed;
623 } 623 }
624 624
625 if (nr_port > 8 && !chip->client_dummy) {
626 dev_err(&client->dev,
627 "Failed to allocate second group I2C device\n");
628 ret = -ENODEV;
629 goto out_failed;
630 }
631
625 mutex_init(&chip->lock); 632 mutex_init(&chip->lock);
626 633
627 max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]); 634 max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]);
@@ -647,6 +654,8 @@ static int max732x_probe(struct i2c_client *client,
647 return 0; 654 return 0;
648 655
649out_failed: 656out_failed:
657 if (chip->client_dummy)
658 i2c_unregister_device(chip->client_dummy);
650 max732x_irq_teardown(chip); 659 max732x_irq_teardown(chip);
651 return ret; 660 return ret;
652} 661}
diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
index 1ac288ea810d..3d53fd6880d1 100644
--- a/drivers/gpio/gpio-mcp23s08.c
+++ b/drivers/gpio/gpio-mcp23s08.c
@@ -173,7 +173,7 @@ static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
173 173
174 tx[0] = mcp->addr | 0x01; 174 tx[0] = mcp->addr | 0x01;
175 tx[1] = reg; 175 tx[1] = reg;
176 status = spi_write_then_read(mcp->data, tx, sizeof tx, rx, sizeof rx); 176 status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
177 return (status < 0) ? status : rx[0]; 177 return (status < 0) ? status : rx[0];
178} 178}
179 179
@@ -184,7 +184,7 @@ static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
184 tx[0] = mcp->addr; 184 tx[0] = mcp->addr;
185 tx[1] = reg; 185 tx[1] = reg;
186 tx[2] = val; 186 tx[2] = val;
187 return spi_write_then_read(mcp->data, tx, sizeof tx, NULL, 0); 187 return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
188} 188}
189 189
190static int 190static int
@@ -193,13 +193,13 @@ mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
193 u8 tx[2], *tmp; 193 u8 tx[2], *tmp;
194 int status; 194 int status;
195 195
196 if ((n + reg) > sizeof mcp->cache) 196 if ((n + reg) > sizeof(mcp->cache))
197 return -EINVAL; 197 return -EINVAL;
198 tx[0] = mcp->addr | 0x01; 198 tx[0] = mcp->addr | 0x01;
199 tx[1] = reg; 199 tx[1] = reg;
200 200
201 tmp = (u8 *)vals; 201 tmp = (u8 *)vals;
202 status = spi_write_then_read(mcp->data, tx, sizeof tx, tmp, n); 202 status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n);
203 if (status >= 0) { 203 if (status >= 0) {
204 while (n--) 204 while (n--)
205 vals[n] = tmp[n]; /* expand to 16bit */ 205 vals[n] = tmp[n]; /* expand to 16bit */
@@ -214,7 +214,7 @@ static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg)
214 214
215 tx[0] = mcp->addr | 0x01; 215 tx[0] = mcp->addr | 0x01;
216 tx[1] = reg << 1; 216 tx[1] = reg << 1;
217 status = spi_write_then_read(mcp->data, tx, sizeof tx, rx, sizeof rx); 217 status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
218 return (status < 0) ? status : (rx[0] | (rx[1] << 8)); 218 return (status < 0) ? status : (rx[0] | (rx[1] << 8));
219} 219}
220 220
@@ -226,7 +226,7 @@ static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
226 tx[1] = reg << 1; 226 tx[1] = reg << 1;
227 tx[2] = val; 227 tx[2] = val;
228 tx[3] = val >> 8; 228 tx[3] = val >> 8;
229 return spi_write_then_read(mcp->data, tx, sizeof tx, NULL, 0); 229 return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
230} 230}
231 231
232static int 232static int
@@ -235,12 +235,12 @@ mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
235 u8 tx[2]; 235 u8 tx[2];
236 int status; 236 int status;
237 237
238 if ((n + reg) > sizeof mcp->cache) 238 if ((n + reg) > sizeof(mcp->cache))
239 return -EINVAL; 239 return -EINVAL;
240 tx[0] = mcp->addr | 0x01; 240 tx[0] = mcp->addr | 0x01;
241 tx[1] = reg << 1; 241 tx[1] = reg << 1;
242 242
243 status = spi_write_then_read(mcp->data, tx, sizeof tx, 243 status = spi_write_then_read(mcp->data, tx, sizeof(tx),
244 (u8 *)vals, n * 2); 244 (u8 *)vals, n * 2);
245 if (status >= 0) { 245 if (status >= 0) {
246 while (n--) 246 while (n--)
@@ -440,24 +440,24 @@ static void mcp23s08_irq_bus_unlock(struct irq_data *data)
440 mutex_unlock(&mcp->irq_lock); 440 mutex_unlock(&mcp->irq_lock);
441} 441}
442 442
443static unsigned int mcp23s08_irq_startup(struct irq_data *data) 443static int mcp23s08_irq_reqres(struct irq_data *data)
444{ 444{
445 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); 445 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
446 446
447 if (gpio_lock_as_irq(&mcp->chip, data->hwirq)) 447 if (gpio_lock_as_irq(&mcp->chip, data->hwirq)) {
448 dev_err(mcp->chip.dev, 448 dev_err(mcp->chip.dev,
449 "unable to lock HW IRQ %lu for IRQ usage\n", 449 "unable to lock HW IRQ %lu for IRQ usage\n",
450 data->hwirq); 450 data->hwirq);
451 return -EINVAL;
452 }
451 453
452 mcp23s08_irq_unmask(data);
453 return 0; 454 return 0;
454} 455}
455 456
456static void mcp23s08_irq_shutdown(struct irq_data *data) 457static void mcp23s08_irq_relres(struct irq_data *data)
457{ 458{
458 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); 459 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
459 460
460 mcp23s08_irq_mask(data);
461 gpio_unlock_as_irq(&mcp->chip, data->hwirq); 461 gpio_unlock_as_irq(&mcp->chip, data->hwirq);
462} 462}
463 463
@@ -468,8 +468,8 @@ static struct irq_chip mcp23s08_irq_chip = {
468 .irq_set_type = mcp23s08_irq_set_type, 468 .irq_set_type = mcp23s08_irq_set_type,
469 .irq_bus_lock = mcp23s08_irq_bus_lock, 469 .irq_bus_lock = mcp23s08_irq_bus_lock,
470 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, 470 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
471 .irq_startup = mcp23s08_irq_startup, 471 .irq_request_resources = mcp23s08_irq_reqres,
472 .irq_shutdown = mcp23s08_irq_shutdown, 472 .irq_release_resources = mcp23s08_irq_relres,
473}; 473};
474 474
475static int mcp23s08_irq_setup(struct mcp23s08 *mcp) 475static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
@@ -567,7 +567,7 @@ static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
567 (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo", 567 (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
568 (mcp->cache[MCP_GPPU] & mask) ? "up" : " "); 568 (mcp->cache[MCP_GPPU] & mask) ? "up" : " ");
569 /* NOTE: ignoring the irq-related registers */ 569 /* NOTE: ignoring the irq-related registers */
570 seq_printf(s, "\n"); 570 seq_puts(s, "\n");
571 } 571 }
572done: 572done:
573 mutex_unlock(&mcp->lock); 573 mutex_unlock(&mcp->lock);
@@ -789,7 +789,7 @@ static int mcp230xx_probe(struct i2c_client *client,
789 pullups = pdata->chip[0].pullups; 789 pullups = pdata->chip[0].pullups;
790 } 790 }
791 791
792 mcp = kzalloc(sizeof *mcp, GFP_KERNEL); 792 mcp = kzalloc(sizeof(*mcp), GFP_KERNEL);
793 if (!mcp) 793 if (!mcp)
794 return -ENOMEM; 794 return -ENOMEM;
795 795
@@ -894,9 +894,11 @@ static int mcp23s08_probe(struct spi_device *spi)
894 dev_err(&spi->dev, "invalid spi-present-mask\n"); 894 dev_err(&spi->dev, "invalid spi-present-mask\n");
895 return -ENODEV; 895 return -ENODEV;
896 } 896 }
897 897 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
898 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) 898 if ((spi_present_mask & (1 << addr)))
899 chips++;
899 pullups[addr] = 0; 900 pullups[addr] = 0;
901 }
900 } else { 902 } else {
901 type = spi_get_device_id(spi)->driver_data; 903 type = spi_get_device_id(spi)->driver_data;
902 pdata = dev_get_platdata(&spi->dev); 904 pdata = dev_get_platdata(&spi->dev);
@@ -919,13 +921,13 @@ static int mcp23s08_probe(struct spi_device *spi)
919 pullups[addr] = pdata->chip[addr].pullups; 921 pullups[addr] = pdata->chip[addr].pullups;
920 } 922 }
921 923
922 if (!chips)
923 return -ENODEV;
924
925 base = pdata->base; 924 base = pdata->base;
926 } 925 }
927 926
928 data = kzalloc(sizeof *data + chips * sizeof(struct mcp23s08), 927 if (!chips)
928 return -ENODEV;
929
930 data = kzalloc(sizeof(*data) + chips * sizeof(struct mcp23s08),
929 GFP_KERNEL); 931 GFP_KERNEL);
930 if (!data) 932 if (!data)
931 return -ENOMEM; 933 return -ENOMEM;
diff --git a/drivers/gpio/gpio-moxart.c b/drivers/gpio/gpio-moxart.c
index 2af990022cc9..ccd45704e5fd 100644
--- a/drivers/gpio/gpio-moxart.c
+++ b/drivers/gpio/gpio-moxart.c
@@ -48,25 +48,6 @@ static void moxart_gpio_free(struct gpio_chip *chip, unsigned offset)
48 pinctrl_free_gpio(offset); 48 pinctrl_free_gpio(offset);
49} 49}
50 50
51static int moxart_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
52{
53 struct moxart_gpio_chip *gc = to_moxart_gpio(chip);
54 void __iomem *ioaddr = gc->base + GPIO_PIN_DIRECTION;
55
56 writel(readl(ioaddr) & ~BIT(offset), ioaddr);
57 return 0;
58}
59
60static int moxart_gpio_direction_output(struct gpio_chip *chip,
61 unsigned offset, int value)
62{
63 struct moxart_gpio_chip *gc = to_moxart_gpio(chip);
64 void __iomem *ioaddr = gc->base + GPIO_PIN_DIRECTION;
65
66 writel(readl(ioaddr) | BIT(offset), ioaddr);
67 return 0;
68}
69
70static void moxart_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 51static void moxart_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
71{ 52{
72 struct moxart_gpio_chip *gc = to_moxart_gpio(chip); 53 struct moxart_gpio_chip *gc = to_moxart_gpio(chip);
@@ -78,7 +59,6 @@ static void moxart_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
78 else 59 else
79 reg = reg & ~BIT(offset); 60 reg = reg & ~BIT(offset);
80 61
81
82 writel(reg, ioaddr); 62 writel(reg, ioaddr);
83} 63}
84 64
@@ -93,6 +73,26 @@ static int moxart_gpio_get(struct gpio_chip *chip, unsigned offset)
93 return !!(readl(gc->base + GPIO_DATA_IN) & BIT(offset)); 73 return !!(readl(gc->base + GPIO_DATA_IN) & BIT(offset));
94} 74}
95 75
76static int moxart_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
77{
78 struct moxart_gpio_chip *gc = to_moxart_gpio(chip);
79 void __iomem *ioaddr = gc->base + GPIO_PIN_DIRECTION;
80
81 writel(readl(ioaddr) & ~BIT(offset), ioaddr);
82 return 0;
83}
84
85static int moxart_gpio_direction_output(struct gpio_chip *chip,
86 unsigned offset, int value)
87{
88 struct moxart_gpio_chip *gc = to_moxart_gpio(chip);
89 void __iomem *ioaddr = gc->base + GPIO_PIN_DIRECTION;
90
91 moxart_gpio_set(chip, offset, value);
92 writel(readl(ioaddr) | BIT(offset), ioaddr);
93 return 0;
94}
95
96static struct gpio_chip moxart_template_chip = { 96static struct gpio_chip moxart_template_chip = {
97 .label = "moxart-gpio", 97 .label = "moxart-gpio",
98 .request = moxart_gpio_request, 98 .request = moxart_gpio_request,
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 3b1fd1ce460f..d42509422394 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -44,6 +44,7 @@
44#include <linux/of_device.h> 44#include <linux/of_device.h>
45#include <linux/clk.h> 45#include <linux/clk.h>
46#include <linux/pinctrl/consumer.h> 46#include <linux/pinctrl/consumer.h>
47#include <linux/irqchip/chained_irq.h>
47 48
48/* 49/*
49 * GPIO unit register offsets. 50 * GPIO unit register offsets.
@@ -438,12 +439,15 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
438static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 439static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
439{ 440{
440 struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq); 441 struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
442 struct irq_chip *chip = irq_desc_get_chip(desc);
441 u32 cause, type; 443 u32 cause, type;
442 int i; 444 int i;
443 445
444 if (mvchip == NULL) 446 if (mvchip == NULL)
445 return; 447 return;
446 448
449 chained_irq_enter(chip, desc);
450
447 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & 451 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
448 readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 452 readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
449 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & 453 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
@@ -466,8 +470,11 @@ static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
466 polarity ^= 1 << i; 470 polarity ^= 1 << i;
467 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); 471 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
468 } 472 }
473
469 generic_handle_irq(irq); 474 generic_handle_irq(irq);
470 } 475 }
476
477 chained_irq_exit(chip, desc);
471} 478}
472 479
473#ifdef CONFIG_DEBUG_FS 480#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index 532bcb336eff..8ffdd7d2bade 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -214,7 +214,8 @@ static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
214 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR; 214 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
215 ct->regs.mask = PINCTRL_IRQEN(port); 215 ct->regs.mask = PINCTRL_IRQEN(port);
216 216
217 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 217 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
218 IRQ_NOREQUEST, 0);
218} 219}
219 220
220static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 221static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 424319061e09..19b886c21b1d 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1214,24 +1214,10 @@ static int omap_gpio_probe(struct platform_device *pdev)
1214 1214
1215 /* Static mapping, never released */ 1215 /* Static mapping, never released */
1216 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1216 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1217 if (unlikely(!res)) { 1217 bank->base = devm_ioremap_resource(dev, res);
1218 dev_err(dev, "Invalid mem resource\n"); 1218 if (IS_ERR(bank->base)) {
1219 irq_domain_remove(bank->domain);
1220 return -ENODEV;
1221 }
1222
1223 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1224 pdev->name)) {
1225 dev_err(dev, "Region already claimed\n");
1226 irq_domain_remove(bank->domain); 1219 irq_domain_remove(bank->domain);
1227 return -EBUSY; 1220 return PTR_ERR(bank->base);
1228 }
1229
1230 bank->base = devm_ioremap(dev, res->start, resource_size(res));
1231 if (!bank->base) {
1232 dev_err(dev, "Could not ioremap\n");
1233 irq_domain_remove(bank->domain);
1234 return -ENOMEM;
1235 } 1221 }
1236 1222
1237 platform_set_drvdata(pdev, bank); 1223 platform_set_drvdata(pdev, bank);
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 019b23b955a2..d550d8e58705 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * PCA953x 4/8/16 bit I/O ports 2 * PCA953x 4/8/16/24/40 bit I/O ports
3 * 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd. 5 * Copyright (C) 2007 Marvell International Ltd.
@@ -59,6 +59,7 @@ static const struct i2c_device_id pca953x_id[] = {
59 { "pca9557", 8 | PCA953X_TYPE, }, 59 { "pca9557", 8 | PCA953X_TYPE, },
60 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 60 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
61 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 61 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
62 { "pca9698", 40 | PCA953X_TYPE, },
62 63
63 { "max7310", 8 | PCA953X_TYPE, }, 64 { "max7310", 8 | PCA953X_TYPE, },
64 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 65 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
@@ -68,6 +69,7 @@ static const struct i2c_device_id pca953x_id[] = {
68 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 69 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
69 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 70 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
70 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 71 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
72 { "xra1202", 8 | PCA953X_TYPE },
71 { } 73 { }
72}; 74};
73MODULE_DEVICE_TABLE(i2c, pca953x_id); 75MODULE_DEVICE_TABLE(i2c, pca953x_id);
@@ -625,11 +627,12 @@ pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
625 const __be32 *val; 627 const __be32 *val;
626 int size; 628 int size;
627 629
630 *gpio_base = -1;
631
628 node = client->dev.of_node; 632 node = client->dev.of_node;
629 if (node == NULL) 633 if (node == NULL)
630 return; 634 return;
631 635
632 *gpio_base = -1;
633 val = of_get_property(node, "linux,gpio-base", &size); 636 val = of_get_property(node, "linux,gpio-base", &size);
634 WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__); 637 WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__);
635 if (val) { 638 if (val) {
@@ -812,6 +815,7 @@ static const struct of_device_id pca953x_dt_ids[] = {
812 { .compatible = "nxp,pca9557", }, 815 { .compatible = "nxp,pca9557", },
813 { .compatible = "nxp,pca9574", }, 816 { .compatible = "nxp,pca9574", },
814 { .compatible = "nxp,pca9575", }, 817 { .compatible = "nxp,pca9575", },
818 { .compatible = "nxp,pca9698", },
815 819
816 { .compatible = "maxim,max7310", }, 820 { .compatible = "maxim,max7310", },
817 { .compatible = "maxim,max7312", }, 821 { .compatible = "maxim,max7312", },
@@ -822,6 +826,8 @@ static const struct of_device_id pca953x_dt_ids[] = {
822 { .compatible = "ti,tca6408", }, 826 { .compatible = "ti,tca6408", },
823 { .compatible = "ti,tca6416", }, 827 { .compatible = "ti,tca6416", },
824 { .compatible = "ti,tca6424", }, 828 { .compatible = "ti,tca6424", },
829
830 { .compatible = "exar,xra1202", },
825 { } 831 { }
826}; 832};
827 833
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
index 9656c196772e..83a156397474 100644
--- a/drivers/gpio/gpio-pch.c
+++ b/drivers/gpio/gpio-pch.c
@@ -138,9 +138,6 @@ static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
138 unsigned long flags; 138 unsigned long flags;
139 139
140 spin_lock_irqsave(&chip->spinlock, flags); 140 spin_lock_irqsave(&chip->spinlock, flags);
141 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
142 pm |= (1 << nr);
143 iowrite32(pm, &chip->reg->pm);
144 141
145 reg_val = ioread32(&chip->reg->po); 142 reg_val = ioread32(&chip->reg->po);
146 if (val) 143 if (val)
@@ -148,6 +145,11 @@ static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
148 else 145 else
149 reg_val &= ~(1 << nr); 146 reg_val &= ~(1 << nr);
150 iowrite32(reg_val, &chip->reg->po); 147 iowrite32(reg_val, &chip->reg->po);
148
149 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
150 pm |= (1 << nr);
151 iowrite32(pm, &chip->reg->pm);
152
151 spin_unlock_irqrestore(&chip->spinlock, flags); 153 spin_unlock_irqrestore(&chip->spinlock, flags);
152 154
153 return 0; 155 return 0;
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index b4d42112d02d..b0f475243cef 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -15,7 +15,6 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/ioport.h> 16#include <linux/ioport.h>
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/irqchip/chained_irq.h> 18#include <linux/irqchip/chained_irq.h>
20#include <linux/bitops.h> 19#include <linux/bitops.h>
21#include <linux/workqueue.h> 20#include <linux/workqueue.h>
@@ -53,7 +52,6 @@ struct pl061_gpio {
53 spinlock_t lock; 52 spinlock_t lock;
54 53
55 void __iomem *base; 54 void __iomem *base;
56 struct irq_domain *domain;
57 struct gpio_chip gc; 55 struct gpio_chip gc;
58 56
59#ifdef CONFIG_PM 57#ifdef CONFIG_PM
@@ -137,19 +135,14 @@ static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
137 writeb(!!value << offset, chip->base + (1 << (offset + 2))); 135 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
138} 136}
139 137
140static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
141{
142 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
143
144 return irq_create_mapping(chip->domain, offset);
145}
146
147static int pl061_irq_type(struct irq_data *d, unsigned trigger) 138static int pl061_irq_type(struct irq_data *d, unsigned trigger)
148{ 139{
149 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); 140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
150 int offset = irqd_to_hwirq(d); 142 int offset = irqd_to_hwirq(d);
151 unsigned long flags; 143 unsigned long flags;
152 u8 gpiois, gpioibe, gpioiev; 144 u8 gpiois, gpioibe, gpioiev;
145 u8 bit = BIT(offset);
153 146
154 if (offset < 0 || offset >= PL061_GPIO_NR) 147 if (offset < 0 || offset >= PL061_GPIO_NR)
155 return -EINVAL; 148 return -EINVAL;
@@ -157,30 +150,31 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
157 spin_lock_irqsave(&chip->lock, flags); 150 spin_lock_irqsave(&chip->lock, flags);
158 151
159 gpioiev = readb(chip->base + GPIOIEV); 152 gpioiev = readb(chip->base + GPIOIEV);
160
161 gpiois = readb(chip->base + GPIOIS); 153 gpiois = readb(chip->base + GPIOIS);
154 gpioibe = readb(chip->base + GPIOIBE);
155
162 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 156 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
163 gpiois |= 1 << offset; 157 gpiois |= bit;
164 if (trigger & IRQ_TYPE_LEVEL_HIGH) 158 if (trigger & IRQ_TYPE_LEVEL_HIGH)
165 gpioiev |= 1 << offset; 159 gpioiev |= bit;
166 else 160 else
167 gpioiev &= ~(1 << offset); 161 gpioiev &= ~bit;
168 } else 162 } else
169 gpiois &= ~(1 << offset); 163 gpiois &= ~bit;
170 writeb(gpiois, chip->base + GPIOIS);
171 164
172 gpioibe = readb(chip->base + GPIOIBE);
173 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 165 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
174 gpioibe |= 1 << offset; 166 /* Setting this makes GPIOEV be ignored */
167 gpioibe |= bit;
175 else { 168 else {
176 gpioibe &= ~(1 << offset); 169 gpioibe &= ~bit;
177 if (trigger & IRQ_TYPE_EDGE_RISING) 170 if (trigger & IRQ_TYPE_EDGE_RISING)
178 gpioiev |= 1 << offset; 171 gpioiev |= bit;
179 else if (trigger & IRQ_TYPE_EDGE_FALLING) 172 else if (trigger & IRQ_TYPE_EDGE_FALLING)
180 gpioiev &= ~(1 << offset); 173 gpioiev &= ~bit;
181 } 174 }
182 writeb(gpioibe, chip->base + GPIOIBE);
183 175
176 writeb(gpiois, chip->base + GPIOIS);
177 writeb(gpioibe, chip->base + GPIOIBE);
184 writeb(gpioiev, chip->base + GPIOIEV); 178 writeb(gpioiev, chip->base + GPIOIEV);
185 179
186 spin_unlock_irqrestore(&chip->lock, flags); 180 spin_unlock_irqrestore(&chip->lock, flags);
@@ -192,7 +186,8 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
192{ 186{
193 unsigned long pending; 187 unsigned long pending;
194 int offset; 188 int offset;
195 struct pl061_gpio *chip = irq_desc_get_handler_data(desc); 189 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
190 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
196 struct irq_chip *irqchip = irq_desc_get_chip(desc); 191 struct irq_chip *irqchip = irq_desc_get_chip(desc);
197 192
198 chained_irq_enter(irqchip, desc); 193 chained_irq_enter(irqchip, desc);
@@ -201,7 +196,8 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
201 writeb(pending, chip->base + GPIOIC); 196 writeb(pending, chip->base + GPIOIC);
202 if (pending) { 197 if (pending) {
203 for_each_set_bit(offset, &pending, PL061_GPIO_NR) 198 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
204 generic_handle_irq(pl061_to_irq(&chip->gc, offset)); 199 generic_handle_irq(irq_find_mapping(gc->irqdomain,
200 offset));
205 } 201 }
206 202
207 chained_irq_exit(irqchip, desc); 203 chained_irq_exit(irqchip, desc);
@@ -209,7 +205,8 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
209 205
210static void pl061_irq_mask(struct irq_data *d) 206static void pl061_irq_mask(struct irq_data *d)
211{ 207{
212 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); 208 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
209 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
213 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR); 210 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
214 u8 gpioie; 211 u8 gpioie;
215 212
@@ -221,7 +218,8 @@ static void pl061_irq_mask(struct irq_data *d)
221 218
222static void pl061_irq_unmask(struct irq_data *d) 219static void pl061_irq_unmask(struct irq_data *d)
223{ 220{
224 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); 221 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
222 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
225 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR); 223 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
226 u8 gpioie; 224 u8 gpioie;
227 225
@@ -232,30 +230,12 @@ static void pl061_irq_unmask(struct irq_data *d)
232} 230}
233 231
234static struct irq_chip pl061_irqchip = { 232static struct irq_chip pl061_irqchip = {
235 .name = "pl061 gpio", 233 .name = "pl061",
236 .irq_mask = pl061_irq_mask, 234 .irq_mask = pl061_irq_mask,
237 .irq_unmask = pl061_irq_unmask, 235 .irq_unmask = pl061_irq_unmask,
238 .irq_set_type = pl061_irq_type, 236 .irq_set_type = pl061_irq_type,
239}; 237};
240 238
241static int pl061_irq_map(struct irq_domain *d, unsigned int irq,
242 irq_hw_number_t hwirq)
243{
244 struct pl061_gpio *chip = d->host_data;
245
246 irq_set_chip_and_handler_name(irq, &pl061_irqchip, handle_simple_irq,
247 "pl061");
248 irq_set_chip_data(irq, chip);
249 irq_set_irq_type(irq, IRQ_TYPE_NONE);
250
251 return 0;
252}
253
254static const struct irq_domain_ops pl061_domain_ops = {
255 .map = pl061_irq_map,
256 .xlate = irq_domain_xlate_twocell,
257};
258
259static int pl061_probe(struct amba_device *adev, const struct amba_id *id) 239static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
260{ 240{
261 struct device *dev = &adev->dev; 241 struct device *dev = &adev->dev;
@@ -270,21 +250,18 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
270 if (pdata) { 250 if (pdata) {
271 chip->gc.base = pdata->gpio_base; 251 chip->gc.base = pdata->gpio_base;
272 irq_base = pdata->irq_base; 252 irq_base = pdata->irq_base;
273 if (irq_base <= 0) 253 if (irq_base <= 0) {
254 dev_err(&adev->dev, "invalid IRQ base in pdata\n");
274 return -ENODEV; 255 return -ENODEV;
256 }
275 } else { 257 } else {
276 chip->gc.base = -1; 258 chip->gc.base = -1;
277 irq_base = 0; 259 irq_base = 0;
278 } 260 }
279 261
280 if (!devm_request_mem_region(dev, adev->res.start, 262 chip->base = devm_ioremap_resource(dev, &adev->res);
281 resource_size(&adev->res), "pl061")) 263 if (IS_ERR(chip->base))
282 return -EBUSY; 264 return PTR_ERR(chip->base);
283
284 chip->base = devm_ioremap(dev, adev->res.start,
285 resource_size(&adev->res));
286 if (!chip->base)
287 return -ENOMEM;
288 265
289 spin_lock_init(&chip->lock); 266 spin_lock_init(&chip->lock);
290 267
@@ -294,7 +271,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
294 chip->gc.direction_output = pl061_direction_output; 271 chip->gc.direction_output = pl061_direction_output;
295 chip->gc.get = pl061_get_value; 272 chip->gc.get = pl061_get_value;
296 chip->gc.set = pl061_set_value; 273 chip->gc.set = pl061_set_value;
297 chip->gc.to_irq = pl061_to_irq;
298 chip->gc.ngpio = PL061_GPIO_NR; 274 chip->gc.ngpio = PL061_GPIO_NR;
299 chip->gc.label = dev_name(dev); 275 chip->gc.label = dev_name(dev);
300 chip->gc.dev = dev; 276 chip->gc.dev = dev;
@@ -309,16 +285,20 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
309 */ 285 */
310 writeb(0, chip->base + GPIOIE); /* disable irqs */ 286 writeb(0, chip->base + GPIOIE); /* disable irqs */
311 irq = adev->irq[0]; 287 irq = adev->irq[0];
312 if (irq < 0) 288 if (irq < 0) {
289 dev_err(&adev->dev, "invalid IRQ\n");
313 return -ENODEV; 290 return -ENODEV;
291 }
314 292
315 irq_set_chained_handler(irq, pl061_irq_handler); 293 ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
316 irq_set_handler_data(irq, chip); 294 irq_base, handle_simple_irq,
317 295 IRQ_TYPE_NONE);
318 chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR, 296 if (ret) {
319 irq_base, &pl061_domain_ops, chip); 297 dev_info(&adev->dev, "could not add irqchip\n");
320 if (!chip->domain) 298 return ret;
321 return -ENODEV; 299 }
300 gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
301 irq, pl061_irq_handler);
322 302
323 for (i = 0; i < PL061_GPIO_NR; i++) { 303 for (i = 0; i < PL061_GPIO_NR; i++) {
324 if (pdata) { 304 if (pdata) {
@@ -331,6 +311,8 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
331 } 311 }
332 312
333 amba_set_drvdata(adev, chip); 313 amba_set_drvdata(adev, chip);
314 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
315 &adev->res.start);
334 316
335 return 0; 317 return 0;
336} 318}
diff --git a/drivers/gpio/gpio-rc5t583.c b/drivers/gpio/gpio-rc5t583.c
index 122b776fdc0b..9b423173ab50 100644
--- a/drivers/gpio/gpio-rc5t583.c
+++ b/drivers/gpio/gpio-rc5t583.c
@@ -97,7 +97,7 @@ static int rc5t583_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
97{ 97{
98 struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc); 98 struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
99 99
100 if ((offset >= 0) && (offset < 8)) 100 if (offset < RC5T583_MAX_GPIO)
101 return rc5t583_gpio->rc5t583->irq_base + 101 return rc5t583_gpio->rc5t583->irq_base +
102 RC5T583_IRQ_GPIO0 + offset; 102 RC5T583_IRQ_GPIO0 + offset;
103 return -EINVAL; 103 return -EINVAL;
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index ca76ce751540..03c91482432c 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -356,12 +356,13 @@ static int gpio_rcar_probe(struct platform_device *pdev)
356 struct resource *io, *irq; 356 struct resource *io, *irq;
357 struct gpio_chip *gpio_chip; 357 struct gpio_chip *gpio_chip;
358 struct irq_chip *irq_chip; 358 struct irq_chip *irq_chip;
359 const char *name = dev_name(&pdev->dev); 359 struct device *dev = &pdev->dev;
360 const char *name = dev_name(dev);
360 int ret; 361 int ret;
361 362
362 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); 363 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
363 if (!p) { 364 if (!p) {
364 dev_err(&pdev->dev, "failed to allocate driver data\n"); 365 dev_err(dev, "failed to allocate driver data\n");
365 ret = -ENOMEM; 366 ret = -ENOMEM;
366 goto err0; 367 goto err0;
367 } 368 }
@@ -380,15 +381,14 @@ static int gpio_rcar_probe(struct platform_device *pdev)
380 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 381 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
381 382
382 if (!io || !irq) { 383 if (!io || !irq) {
383 dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); 384 dev_err(dev, "missing IRQ or IOMEM\n");
384 ret = -EINVAL; 385 ret = -EINVAL;
385 goto err0; 386 goto err0;
386 } 387 }
387 388
388 p->base = devm_ioremap_nocache(&pdev->dev, io->start, 389 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
389 resource_size(io));
390 if (!p->base) { 390 if (!p->base) {
391 dev_err(&pdev->dev, "failed to remap I/O memory\n"); 391 dev_err(dev, "failed to remap I/O memory\n");
392 ret = -ENXIO; 392 ret = -ENXIO;
393 goto err0; 393 goto err0;
394 } 394 }
@@ -402,7 +402,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
402 gpio_chip->set = gpio_rcar_set; 402 gpio_chip->set = gpio_rcar_set;
403 gpio_chip->to_irq = gpio_rcar_to_irq; 403 gpio_chip->to_irq = gpio_rcar_to_irq;
404 gpio_chip->label = name; 404 gpio_chip->label = name;
405 gpio_chip->dev = &pdev->dev; 405 gpio_chip->dev = dev;
406 gpio_chip->owner = THIS_MODULE; 406 gpio_chip->owner = THIS_MODULE;
407 gpio_chip->base = p->config.gpio_base; 407 gpio_chip->base = p->config.gpio_base;
408 gpio_chip->ngpio = p->config.number_of_pins; 408 gpio_chip->ngpio = p->config.number_of_pins;
@@ -421,30 +421,30 @@ static int gpio_rcar_probe(struct platform_device *pdev)
421 &gpio_rcar_irq_domain_ops, p); 421 &gpio_rcar_irq_domain_ops, p);
422 if (!p->irq_domain) { 422 if (!p->irq_domain) {
423 ret = -ENXIO; 423 ret = -ENXIO;
424 dev_err(&pdev->dev, "cannot initialize irq domain\n"); 424 dev_err(dev, "cannot initialize irq domain\n");
425 goto err0; 425 goto err0;
426 } 426 }
427 427
428 if (devm_request_irq(&pdev->dev, irq->start, 428 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
429 gpio_rcar_irq_handler, IRQF_SHARED, name, p)) { 429 IRQF_SHARED, name, p)) {
430 dev_err(&pdev->dev, "failed to request IRQ\n"); 430 dev_err(dev, "failed to request IRQ\n");
431 ret = -ENOENT; 431 ret = -ENOENT;
432 goto err1; 432 goto err1;
433 } 433 }
434 434
435 ret = gpiochip_add(gpio_chip); 435 ret = gpiochip_add(gpio_chip);
436 if (ret) { 436 if (ret) {
437 dev_err(&pdev->dev, "failed to add GPIO controller\n"); 437 dev_err(dev, "failed to add GPIO controller\n");
438 goto err1; 438 goto err1;
439 } 439 }
440 440
441 dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins); 441 dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);
442 442
443 /* warn in case of mismatch if irq base is specified */ 443 /* warn in case of mismatch if irq base is specified */
444 if (p->config.irq_base) { 444 if (p->config.irq_base) {
445 ret = irq_find_mapping(p->irq_domain, 0); 445 ret = irq_find_mapping(p->irq_domain, 0);
446 if (p->config.irq_base != ret) 446 if (p->config.irq_base != ret)
447 dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n", 447 dev_warn(dev, "irq base mismatch (%u/%u)\n",
448 p->config.irq_base, ret); 448 p->config.irq_base, ret);
449 } 449 }
450 450
@@ -452,7 +452,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
452 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, 452 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
453 gpio_chip->base, gpio_chip->ngpio); 453 gpio_chip->base, gpio_chip->ngpio);
454 if (ret < 0) 454 if (ret < 0)
455 dev_warn(&pdev->dev, "failed to add pin range\n"); 455 dev_warn(dev, "failed to add pin range\n");
456 } 456 }
457 457
458 return 0; 458 return 0;
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index a85e00bf9834..07105ee5c9ae 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -379,6 +379,7 @@ static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
379 case 6: 379 case 6:
380 shift = ((off + 1) & 7) * 4; 380 shift = ((off + 1) & 7) * 4;
381 reg -= 4; 381 reg -= 4;
382 break;
382 default: 383 default:
383 shift = ((off + 1) & 7) * 4; 384 shift = ((off + 1) & 7) * 4;
384 break; 385 break;
diff --git a/drivers/gpio/gpio-spear-spics.c b/drivers/gpio/gpio-spear-spics.c
index e9a0415834ea..30bcc539425d 100644
--- a/drivers/gpio/gpio-spear-spics.c
+++ b/drivers/gpio/gpio-spear-spics.c
@@ -2,7 +2,7 @@
2 * SPEAr platform SPI chipselect abstraction over gpiolib 2 * SPEAr platform SPI chipselect abstraction over gpiolib
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Shiraz Hashim <shiraz.hashim@st.com> 5 * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
@@ -205,6 +205,6 @@ static int __init spics_gpio_init(void)
205} 205}
206subsys_initcall(spics_gpio_init); 206subsys_initcall(spics_gpio_init);
207 207
208MODULE_AUTHOR("Shiraz Hashim <shiraz.hashim@st.com>"); 208MODULE_AUTHOR("Shiraz Hashim <shiraz.linux.kernel@gmail.com>");
209MODULE_DESCRIPTION("ST Microlectronics SPEAr SPI Chip Select Abstraction"); 209MODULE_DESCRIPTION("ST Microlectronics SPEAr SPI Chip Select Abstraction");
210MODULE_LICENSE("GPL"); 210MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 2776a09bee58..628b58494294 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -23,7 +23,8 @@
23enum { REG_RE, REG_FE, REG_IE }; 23enum { REG_RE, REG_FE, REG_IE };
24 24
25#define CACHE_NR_REGS 3 25#define CACHE_NR_REGS 3
26#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8) 26/* No variant has more than 24 GPIOs */
27#define CACHE_NR_BANKS (24 / 8)
27 28
28struct stmpe_gpio { 29struct stmpe_gpio {
29 struct gpio_chip chip; 30 struct gpio_chip chip;
@@ -31,8 +32,6 @@ struct stmpe_gpio {
31 struct device *dev; 32 struct device *dev;
32 struct mutex irq_lock; 33 struct mutex irq_lock;
33 struct irq_domain *domain; 34 struct irq_domain *domain;
34
35 int irq_base;
36 unsigned norequest_mask; 35 unsigned norequest_mask;
37 36
38 /* Caches of interrupt control registers for bus_lock */ 37 /* Caches of interrupt control registers for bus_lock */
@@ -311,13 +310,8 @@ static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
311static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio, 310static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
312 struct device_node *np) 311 struct device_node *np)
313{ 312{
314 int base = 0;
315
316 if (!np)
317 base = stmpe_gpio->irq_base;
318
319 stmpe_gpio->domain = irq_domain_add_simple(np, 313 stmpe_gpio->domain = irq_domain_add_simple(np,
320 stmpe_gpio->chip.ngpio, base, 314 stmpe_gpio->chip.ngpio, 0,
321 &stmpe_gpio_irq_simple_ops, stmpe_gpio); 315 &stmpe_gpio_irq_simple_ops, stmpe_gpio);
322 if (!stmpe_gpio->domain) { 316 if (!stmpe_gpio->domain) {
323 dev_err(stmpe_gpio->dev, "failed to create irqdomain\n"); 317 dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
@@ -354,7 +348,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
354#ifdef CONFIG_OF 348#ifdef CONFIG_OF
355 stmpe_gpio->chip.of_node = np; 349 stmpe_gpio->chip.of_node = np;
356#endif 350#endif
357 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1; 351 stmpe_gpio->chip.base = -1;
358 352
359 if (pdata) 353 if (pdata)
360 stmpe_gpio->norequest_mask = pdata->norequest_mask; 354 stmpe_gpio->norequest_mask = pdata->norequest_mask;
@@ -362,9 +356,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
362 of_property_read_u32(np, "st,norequest-mask", 356 of_property_read_u32(np, "st,norequest-mask",
363 &stmpe_gpio->norequest_mask); 357 &stmpe_gpio->norequest_mask);
364 358
365 if (irq >= 0) 359 if (irq < 0)
366 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
367 else
368 dev_info(&pdev->dev, 360 dev_info(&pdev->dev,
369 "device configured in no-irq mode; " 361 "device configured in no-irq mode; "
370 "irqs are not available\n"); 362 "irqs are not available\n");
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
new file mode 100644
index 000000000000..b50fe1297748
--- /dev/null
+++ b/drivers/gpio/gpio-syscon.c
@@ -0,0 +1,191 @@
1/*
2 * SYSCON GPIO driver
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/err.h>
13#include <linux/gpio.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19#include <linux/mfd/syscon.h>
20
21#define GPIO_SYSCON_FEAT_IN BIT(0)
22#define GPIO_SYSCON_FEAT_OUT BIT(1)
23#define GPIO_SYSCON_FEAT_DIR BIT(2)
24
25/* SYSCON driver is designed to use 32-bit wide registers */
26#define SYSCON_REG_SIZE (4)
27#define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8)
28
29/**
30 * struct syscon_gpio_data - Configuration for the device.
31 * compatible: SYSCON driver compatible string.
32 * flags: Set of GPIO_SYSCON_FEAT_ flags:
33 * GPIO_SYSCON_FEAT_IN: GPIOs supports input,
34 * GPIO_SYSCON_FEAT_OUT: GPIOs supports output,
35 * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction.
36 * bit_count: Number of bits used as GPIOs.
37 * dat_bit_offset: Offset (in bits) to the first GPIO bit.
38 * dir_bit_offset: Optional offset (in bits) to the first bit to switch
39 * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
40 */
41
42struct syscon_gpio_data {
43 const char *compatible;
44 unsigned int flags;
45 unsigned int bit_count;
46 unsigned int dat_bit_offset;
47 unsigned int dir_bit_offset;
48};
49
50struct syscon_gpio_priv {
51 struct gpio_chip chip;
52 struct regmap *syscon;
53 const struct syscon_gpio_data *data;
54};
55
56static inline struct syscon_gpio_priv *to_syscon_gpio(struct gpio_chip *chip)
57{
58 return container_of(chip, struct syscon_gpio_priv, chip);
59}
60
61static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
62{
63 struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
64 unsigned int val, offs = priv->data->dat_bit_offset + offset;
65 int ret;
66
67 ret = regmap_read(priv->syscon,
68 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
69 if (ret)
70 return ret;
71
72 return !!(val & BIT(offs % SYSCON_REG_BITS));
73}
74
75static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
76{
77 struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
78 unsigned int offs = priv->data->dat_bit_offset + offset;
79
80 regmap_update_bits(priv->syscon,
81 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
82 BIT(offs % SYSCON_REG_BITS),
83 val ? BIT(offs % SYSCON_REG_BITS) : 0);
84}
85
86static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
87{
88 struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
89
90 if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
91 unsigned int offs = priv->data->dir_bit_offset + offset;
92
93 regmap_update_bits(priv->syscon,
94 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
95 BIT(offs % SYSCON_REG_BITS), 0);
96 }
97
98 return 0;
99}
100
101static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
102{
103 struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
104
105 if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
106 unsigned int offs = priv->data->dir_bit_offset + offset;
107
108 regmap_update_bits(priv->syscon,
109 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
110 BIT(offs % SYSCON_REG_BITS),
111 BIT(offs % SYSCON_REG_BITS));
112 }
113
114 syscon_gpio_set(chip, offset, val);
115
116 return 0;
117}
118
119static const struct syscon_gpio_data clps711x_mctrl_gpio = {
120 /* ARM CLPS711X SYSFLG1 Bits 8-10 */
121 .compatible = "cirrus,clps711x-syscon1",
122 .flags = GPIO_SYSCON_FEAT_IN,
123 .bit_count = 3,
124 .dat_bit_offset = 0x40 * 8 + 8,
125};
126
127static const struct of_device_id syscon_gpio_ids[] = {
128 {
129 .compatible = "cirrus,clps711x-mctrl-gpio",
130 .data = &clps711x_mctrl_gpio,
131 },
132 { }
133};
134MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
135
136static int syscon_gpio_probe(struct platform_device *pdev)
137{
138 struct device *dev = &pdev->dev;
139 const struct of_device_id *of_id = of_match_device(syscon_gpio_ids, dev);
140 struct syscon_gpio_priv *priv;
141
142 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
143 if (!priv)
144 return -ENOMEM;
145
146 priv->data = of_id->data;
147
148 priv->syscon =
149 syscon_regmap_lookup_by_compatible(priv->data->compatible);
150 if (IS_ERR(priv->syscon))
151 return PTR_ERR(priv->syscon);
152
153 priv->chip.dev = dev;
154 priv->chip.owner = THIS_MODULE;
155 priv->chip.label = dev_name(dev);
156 priv->chip.base = -1;
157 priv->chip.ngpio = priv->data->bit_count;
158 priv->chip.get = syscon_gpio_get;
159 if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
160 priv->chip.direction_input = syscon_gpio_dir_in;
161 if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
162 priv->chip.set = syscon_gpio_set;
163 priv->chip.direction_output = syscon_gpio_dir_out;
164 }
165
166 platform_set_drvdata(pdev, priv);
167
168 return gpiochip_add(&priv->chip);
169}
170
171static int syscon_gpio_remove(struct platform_device *pdev)
172{
173 struct syscon_gpio_priv *priv = platform_get_drvdata(pdev);
174
175 return gpiochip_remove(&priv->chip);
176}
177
178static struct platform_driver syscon_gpio_driver = {
179 .driver = {
180 .name = "gpio-syscon",
181 .owner = THIS_MODULE,
182 .of_match_table = syscon_gpio_ids,
183 },
184 .probe = syscon_gpio_probe,
185 .remove = syscon_gpio_remove,
186};
187module_platform_driver(syscon_gpio_driver);
188
189MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
190MODULE_DESCRIPTION("SYSCON GPIO driver");
191MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-tnetv107x.c b/drivers/gpio/gpio-tnetv107x.c
deleted file mode 100644
index 4aa481579a05..000000000000
--- a/drivers/gpio/gpio-tnetv107x.c
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 * Texas Instruments TNETV107X GPIO Controller
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/gpio.h>
18#include <linux/platform_data/gpio-davinci.h>
19
20#include <mach/common.h>
21#include <mach/tnetv107x.h>
22
23struct tnetv107x_gpio_regs {
24 u32 idver;
25 u32 data_in[3];
26 u32 data_out[3];
27 u32 direction[3];
28 u32 enable[3];
29};
30
31#define gpio_reg_index(gpio) ((gpio) >> 5)
32#define gpio_reg_bit(gpio) BIT((gpio) & 0x1f)
33
34#define gpio_reg_rmw(reg, mask, val) \
35 __raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
36
37#define gpio_reg_set_bit(reg, gpio) \
38 gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
39
40#define gpio_reg_clear_bit(reg, gpio) \
41 gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
42
43#define gpio_reg_get_bit(reg, gpio) \
44 (__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
45
46#define chip2controller(chip) \
47 container_of(chip, struct davinci_gpio_controller, chip)
48
49#define TNETV107X_GPIO_CTLRS DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
50
51static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
52
53static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
54{
55 struct davinci_gpio_controller *ctlr = chip2controller(chip);
56 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
57 unsigned gpio = chip->base + offset;
58 unsigned long flags;
59
60 spin_lock_irqsave(&ctlr->lock, flags);
61
62 gpio_reg_set_bit(regs->enable, gpio);
63
64 spin_unlock_irqrestore(&ctlr->lock, flags);
65
66 return 0;
67}
68
69static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
70{
71 struct davinci_gpio_controller *ctlr = chip2controller(chip);
72 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
73 unsigned gpio = chip->base + offset;
74 unsigned long flags;
75
76 spin_lock_irqsave(&ctlr->lock, flags);
77
78 gpio_reg_clear_bit(regs->enable, gpio);
79
80 spin_unlock_irqrestore(&ctlr->lock, flags);
81}
82
83static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
84{
85 struct davinci_gpio_controller *ctlr = chip2controller(chip);
86 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
87 unsigned gpio = chip->base + offset;
88 unsigned long flags;
89
90 spin_lock_irqsave(&ctlr->lock, flags);
91
92 gpio_reg_set_bit(regs->direction, gpio);
93
94 spin_unlock_irqrestore(&ctlr->lock, flags);
95
96 return 0;
97}
98
99static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
100 unsigned offset, int value)
101{
102 struct davinci_gpio_controller *ctlr = chip2controller(chip);
103 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
104 unsigned gpio = chip->base + offset;
105 unsigned long flags;
106
107 spin_lock_irqsave(&ctlr->lock, flags);
108
109 if (value)
110 gpio_reg_set_bit(regs->data_out, gpio);
111 else
112 gpio_reg_clear_bit(regs->data_out, gpio);
113
114 gpio_reg_clear_bit(regs->direction, gpio);
115
116 spin_unlock_irqrestore(&ctlr->lock, flags);
117
118 return 0;
119}
120
121static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
122{
123 struct davinci_gpio_controller *ctlr = chip2controller(chip);
124 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
125 unsigned gpio = chip->base + offset;
126 int ret;
127
128 ret = gpio_reg_get_bit(regs->data_in, gpio);
129
130 return ret ? 1 : 0;
131}
132
133static void tnetv107x_gpio_set(struct gpio_chip *chip,
134 unsigned offset, int value)
135{
136 struct davinci_gpio_controller *ctlr = chip2controller(chip);
137 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
138 unsigned gpio = chip->base + offset;
139 unsigned long flags;
140
141 spin_lock_irqsave(&ctlr->lock, flags);
142
143 if (value)
144 gpio_reg_set_bit(regs->data_out, gpio);
145 else
146 gpio_reg_clear_bit(regs->data_out, gpio);
147
148 spin_unlock_irqrestore(&ctlr->lock, flags);
149}
150
151static int __init tnetv107x_gpio_setup(void)
152{
153 int i, base;
154 unsigned ngpio;
155 struct davinci_soc_info *soc_info = &davinci_soc_info;
156 struct tnetv107x_gpio_regs *regs;
157 struct davinci_gpio_controller *ctlr;
158
159 if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
160 return 0;
161
162 ngpio = soc_info->gpio_num;
163 if (ngpio == 0) {
164 pr_err("GPIO setup: how many GPIOs?\n");
165 return -EINVAL;
166 }
167
168 if (WARN_ON(TNETV107X_N_GPIO < ngpio))
169 ngpio = TNETV107X_N_GPIO;
170
171 regs = ioremap(soc_info->gpio_base, SZ_4K);
172 if (WARN_ON(!regs))
173 return -EINVAL;
174
175 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
176 ctlr = &chips[i];
177
178 ctlr->chip.label = "tnetv107x";
179 ctlr->chip.can_sleep = false;
180 ctlr->chip.base = base;
181 ctlr->chip.ngpio = ngpio - base;
182 if (ctlr->chip.ngpio > 32)
183 ctlr->chip.ngpio = 32;
184
185 ctlr->chip.request = tnetv107x_gpio_request;
186 ctlr->chip.free = tnetv107x_gpio_free;
187 ctlr->chip.direction_input = tnetv107x_gpio_dir_in;
188 ctlr->chip.get = tnetv107x_gpio_get;
189 ctlr->chip.direction_output = tnetv107x_gpio_dir_out;
190 ctlr->chip.set = tnetv107x_gpio_set;
191
192 spin_lock_init(&ctlr->lock);
193
194 ctlr->regs = regs;
195 ctlr->set_data = &regs->data_out[i];
196 ctlr->clr_data = &regs->data_out[i];
197 ctlr->in_data = &regs->data_in[i];
198
199 gpiochip_add(&ctlr->chip);
200 }
201
202 soc_info->gpio_ctlrs = chips;
203 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
204 return 0;
205}
206pure_initcall(tnetv107x_gpio_setup);
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index 8b88ca2eda9c..3ebb1a5ff22e 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -139,7 +139,6 @@ static u8 cached_leden;
139static void twl4030_led_set_value(int led, int value) 139static void twl4030_led_set_value(int led, int value)
140{ 140{
141 u8 mask = LEDEN_LEDAON | LEDEN_LEDAPWM; 141 u8 mask = LEDEN_LEDAON | LEDEN_LEDAPWM;
142 int status;
143 142
144 if (led) 143 if (led)
145 mask <<= 1; 144 mask <<= 1;
@@ -148,8 +147,9 @@ static void twl4030_led_set_value(int led, int value)
148 cached_leden &= ~mask; 147 cached_leden &= ~mask;
149 else 148 else
150 cached_leden |= mask; 149 cached_leden |= mask;
151 status = twl_i2c_write_u8(TWL4030_MODULE_LED, cached_leden, 150
152 TWL4030_LED_LEDEN_REG); 151 WARN_ON_ONCE(twl_i2c_write_u8(TWL4030_MODULE_LED, cached_leden,
152 TWL4030_LED_LEDEN_REG));
153} 153}
154 154
155static int twl4030_set_gpio_direction(int gpio, int is_input) 155static int twl4030_set_gpio_direction(int gpio, int is_input)
diff --git a/drivers/gpio/gpio-tz1090.c b/drivers/gpio/gpio-tz1090.c
index 23e061392411..5246a60eff6d 100644
--- a/drivers/gpio/gpio-tz1090.c
+++ b/drivers/gpio/gpio-tz1090.c
@@ -488,26 +488,26 @@ static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
488 gc->chip_types[0].handler = handle_level_irq; 488 gc->chip_types[0].handler = handle_level_irq;
489 gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS; 489 gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS;
490 gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN; 490 gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN;
491 gc->chip_types[0].chip.irq_startup = gpio_startup_irq, 491 gc->chip_types[0].chip.irq_startup = gpio_startup_irq;
492 gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit, 492 gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
493 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit, 493 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
494 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit, 494 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
495 gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type, 495 gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type;
496 gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake, 496 gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake;
497 gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND, 497 gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
498 498
499 /* edge chip type */ 499 /* edge chip type */
500 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; 500 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
501 gc->chip_types[1].handler = handle_edge_irq; 501 gc->chip_types[1].handler = handle_edge_irq;
502 gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS; 502 gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS;
503 gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN; 503 gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN;
504 gc->chip_types[1].chip.irq_startup = gpio_startup_irq, 504 gc->chip_types[1].chip.irq_startup = gpio_startup_irq;
505 gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit, 505 gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit;
506 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit, 506 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
507 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit, 507 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
508 gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type, 508 gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type;
509 gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake, 509 gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake;
510 gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND, 510 gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
511 511
512 /* Setup chained handler for this GPIO bank */ 512 /* Setup chained handler for this GPIO bank */
513 irq_set_handler_data(bank->irq, bank); 513 irq_set_handler_data(bank->irq, bank);
diff --git a/drivers/gpio/gpio-vr41xx.c b/drivers/gpio/gpio-vr41xx.c
index 9902732a382d..66cbcc108e62 100644
--- a/drivers/gpio/gpio-vr41xx.c
+++ b/drivers/gpio/gpio-vr41xx.c
@@ -81,6 +81,7 @@ static DEFINE_SPINLOCK(giu_lock);
81static unsigned long giu_flags; 81static unsigned long giu_flags;
82 82
83static void __iomem *giu_base; 83static void __iomem *giu_base;
84static struct gpio_chip vr41xx_gpio_chip;
84 85
85#define giu_read(offset) readw(giu_base + (offset)) 86#define giu_read(offset) readw(giu_base + (offset))
86#define giu_write(offset, value) writew((value), giu_base + (offset)) 87#define giu_write(offset, value) writew((value), giu_base + (offset))
@@ -135,12 +136,31 @@ static void unmask_giuint_low(struct irq_data *d)
135 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq)); 136 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
136} 137}
137 138
139static unsigned int startup_giuint(struct irq_data *data)
140{
141 if (gpio_lock_as_irq(&vr41xx_gpio_chip, data->hwirq))
142 dev_err(vr41xx_gpio_chip.dev,
143 "unable to lock HW IRQ %lu for IRQ\n",
144 data->hwirq);
145 /* Satisfy the .enable semantics by unmasking the line */
146 unmask_giuint_low(data);
147 return 0;
148}
149
150static void shutdown_giuint(struct irq_data *data)
151{
152 mask_giuint_low(data);
153 gpio_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq);
154}
155
138static struct irq_chip giuint_low_irq_chip = { 156static struct irq_chip giuint_low_irq_chip = {
139 .name = "GIUINTL", 157 .name = "GIUINTL",
140 .irq_ack = ack_giuint_low, 158 .irq_ack = ack_giuint_low,
141 .irq_mask = mask_giuint_low, 159 .irq_mask = mask_giuint_low,
142 .irq_mask_ack = mask_ack_giuint_low, 160 .irq_mask_ack = mask_ack_giuint_low,
143 .irq_unmask = unmask_giuint_low, 161 .irq_unmask = unmask_giuint_low,
162 .irq_startup = startup_giuint,
163 .irq_shutdown = shutdown_giuint,
144}; 164};
145 165
146static void ack_giuint_high(struct irq_data *d) 166static void ack_giuint_high(struct irq_data *d)
diff --git a/drivers/gpio/gpio-zevio.c b/drivers/gpio/gpio-zevio.c
new file mode 100644
index 000000000000..9bf5034b6cdb
--- /dev/null
+++ b/drivers/gpio/gpio-zevio.c
@@ -0,0 +1,220 @@
1/*
2 * GPIO controller in LSI ZEVIO SoCs.
3 *
4 * Author: Fabian Vogt <fabian@ritter-vogt.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/spinlock.h>
12#include <linux/errno.h>
13#include <linux/module.h>
14#include <linux/bitops.h>
15#include <linux/io.h>
16#include <linux/of_device.h>
17#include <linux/of_gpio.h>
18#include <linux/slab.h>
19#include <linux/gpio.h>
20
21/*
22 * Memory layout:
23 * This chip has four gpio sections, each controls 8 GPIOs.
24 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
25 * Disclaimer: Reverse engineered!
26 * For more information refer to:
27 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
28 *
29 * 0x00-0x3F: Section 0
30 * +0x00: Masked interrupt status (read-only)
31 * +0x04: R: Interrupt status W: Reset interrupt status
32 * +0x08: R: Interrupt mask W: Mask interrupt
33 * +0x0C: W: Unmask interrupt (write-only)
34 * +0x10: Direction: I/O=1/0
35 * +0x14: Output
36 * +0x18: Input (read-only)
37 * +0x20: R: Level interrupt W: Set as level interrupt
38 * 0x40-0x7F: Section 1
39 * 0x80-0xBF: Section 2
40 * 0xC0-0xFF: Section 3
41 */
42
43#define ZEVIO_GPIO_SECTION_SIZE 0x40
44
45/* Offsets to various registers */
46#define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
47#define ZEVIO_GPIO_INT_STATUS 0x04
48#define ZEVIO_GPIO_INT_UNMASK 0x08
49#define ZEVIO_GPIO_INT_MASK 0x0C
50#define ZEVIO_GPIO_DIRECTION 0x10
51#define ZEVIO_GPIO_OUTPUT 0x14
52#define ZEVIO_GPIO_INPUT 0x18
53#define ZEVIO_GPIO_INT_STICKY 0x20
54
55#define to_zevio_gpio(chip) container_of(to_of_mm_gpio_chip(chip), \
56 struct zevio_gpio, chip)
57
58/* Bit number of GPIO in its section */
59#define ZEVIO_GPIO_BIT(gpio) (gpio&7)
60
61struct zevio_gpio {
62 spinlock_t lock;
63 struct of_mm_gpio_chip chip;
64};
65
66static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
67 unsigned port_offset)
68{
69 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
70 return readl(IOMEM(c->chip.regs + section_offset + port_offset));
71}
72
73static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
74 unsigned port_offset, u32 val)
75{
76 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
77 writel(val, IOMEM(c->chip.regs + section_offset + port_offset));
78}
79
80/* Functions for struct gpio_chip */
81static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
82{
83 struct zevio_gpio *controller = to_zevio_gpio(chip);
84
85 /* Only reading allowed, so no spinlock needed */
86 u32 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
87
88 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
89}
90
91static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
92{
93 struct zevio_gpio *controller = to_zevio_gpio(chip);
94 u32 val;
95
96 spin_lock(&controller->lock);
97 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
98 if (value)
99 val |= BIT(ZEVIO_GPIO_BIT(pin));
100 else
101 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
102
103 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
104 spin_unlock(&controller->lock);
105}
106
107static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
108{
109 struct zevio_gpio *controller = to_zevio_gpio(chip);
110 u32 val;
111
112 spin_lock(&controller->lock);
113
114 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
115 val |= BIT(ZEVIO_GPIO_BIT(pin));
116 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
117
118 spin_unlock(&controller->lock);
119
120 return 0;
121}
122
123static int zevio_gpio_direction_output(struct gpio_chip *chip,
124 unsigned pin, int value)
125{
126 struct zevio_gpio *controller = to_zevio_gpio(chip);
127 u32 val;
128
129 spin_lock(&controller->lock);
130 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
131 if (value)
132 val |= BIT(ZEVIO_GPIO_BIT(pin));
133 else
134 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
135
136 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
137 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
138 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
139 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
140
141 spin_unlock(&controller->lock);
142
143 return 0;
144}
145
146static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
147{
148 /*
149 * TODO: Implement IRQs.
150 * Not implemented yet due to weird lockups
151 */
152
153 return -ENXIO;
154}
155
156static struct gpio_chip zevio_gpio_chip = {
157 .direction_input = zevio_gpio_direction_input,
158 .direction_output = zevio_gpio_direction_output,
159 .set = zevio_gpio_set,
160 .get = zevio_gpio_get,
161 .to_irq = zevio_gpio_to_irq,
162 .base = 0,
163 .owner = THIS_MODULE,
164 .ngpio = 32,
165 .of_gpio_n_cells = 2,
166};
167
168/* Initialization */
169static int zevio_gpio_probe(struct platform_device *pdev)
170{
171 struct zevio_gpio *controller;
172 int status, i;
173
174 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
175 if (!controller) {
176 dev_err(&pdev->dev, "not enough free memory\n");
177 return -ENOMEM;
178 }
179
180 /* Copy our reference */
181 controller->chip.gc = zevio_gpio_chip;
182 controller->chip.gc.dev = &pdev->dev;
183
184 status = of_mm_gpiochip_add(pdev->dev.of_node, &(controller->chip));
185 if (status) {
186 dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
187 return status;
188 }
189
190 spin_lock_init(&controller->lock);
191
192 /* Disable interrupts, they only cause errors */
193 for (i = 0; i < controller->chip.gc.ngpio; i += 8)
194 zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
195
196 dev_dbg(controller->chip.gc.dev, "ZEVIO GPIO controller set up!\n");
197
198 return 0;
199}
200
201static struct of_device_id zevio_gpio_of_match[] = {
202 { .compatible = "lsi,zevio-gpio", },
203 { },
204};
205
206MODULE_DEVICE_TABLE(of, zevio_gpio_of_match);
207
208static struct platform_driver zevio_gpio_driver = {
209 .driver = {
210 .name = "gpio-zevio",
211 .owner = THIS_MODULE,
212 .of_match_table = of_match_ptr(zevio_gpio_of_match),
213 },
214 .probe = zevio_gpio_probe,
215};
216module_platform_driver(zevio_gpio_driver);
217
218MODULE_LICENSE("GPL");
219MODULE_AUTHOR("Fabian Vogt <fabian@ritter-vogt.de>");
220MODULE_DESCRIPTION("LSI ZEVIO SoC GPIO driver");
diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c
index 716ee9843110..401add28933f 100644
--- a/drivers/gpio/gpiolib-acpi.c
+++ b/drivers/gpio/gpiolib-acpi.c
@@ -16,16 +16,35 @@
16#include <linux/export.h> 16#include <linux/export.h>
17#include <linux/acpi.h> 17#include <linux/acpi.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/mutex.h>
19 20
20#include "gpiolib.h" 21#include "gpiolib.h"
21 22
22struct acpi_gpio_evt_pin { 23struct acpi_gpio_event {
23 struct list_head node; 24 struct list_head node;
24 acpi_handle *evt_handle; 25 acpi_handle handle;
25 unsigned int pin; 26 unsigned int pin;
26 unsigned int irq; 27 unsigned int irq;
27}; 28};
28 29
30struct acpi_gpio_connection {
31 struct list_head node;
32 struct gpio_desc *desc;
33};
34
35struct acpi_gpio_chip {
36 /*
37 * ACPICA requires that the first field of the context parameter
38 * passed to acpi_install_address_space_handler() is large enough
39 * to hold struct acpi_connection_info.
40 */
41 struct acpi_connection_info conn_info;
42 struct list_head conns;
43 struct mutex conn_lock;
44 struct gpio_chip *chip;
45 struct list_head events;
46};
47
29static int acpi_gpiochip_find(struct gpio_chip *gc, void *data) 48static int acpi_gpiochip_find(struct gpio_chip *gc, void *data)
30{ 49{
31 if (!gc->dev) 50 if (!gc->dev)
@@ -60,176 +79,195 @@ static struct gpio_desc *acpi_get_gpiod(char *path, int pin)
60 if (pin < 0 || pin > chip->ngpio) 79 if (pin < 0 || pin > chip->ngpio)
61 return ERR_PTR(-EINVAL); 80 return ERR_PTR(-EINVAL);
62 81
63 return gpio_to_desc(chip->base + pin); 82 return gpiochip_get_desc(chip, pin);
64} 83}
65 84
66static irqreturn_t acpi_gpio_irq_handler(int irq, void *data) 85static irqreturn_t acpi_gpio_irq_handler(int irq, void *data)
67{ 86{
68 acpi_handle handle = data; 87 struct acpi_gpio_event *event = data;
69 88
70 acpi_evaluate_object(handle, NULL, NULL, NULL); 89 acpi_evaluate_object(event->handle, NULL, NULL, NULL);
71 90
72 return IRQ_HANDLED; 91 return IRQ_HANDLED;
73} 92}
74 93
75static irqreturn_t acpi_gpio_irq_handler_evt(int irq, void *data) 94static irqreturn_t acpi_gpio_irq_handler_evt(int irq, void *data)
76{ 95{
77 struct acpi_gpio_evt_pin *evt_pin = data; 96 struct acpi_gpio_event *event = data;
78 97
79 acpi_execute_simple_method(evt_pin->evt_handle, NULL, evt_pin->pin); 98 acpi_execute_simple_method(event->handle, NULL, event->pin);
80 99
81 return IRQ_HANDLED; 100 return IRQ_HANDLED;
82} 101}
83 102
84static void acpi_gpio_evt_dh(acpi_handle handle, void *data) 103static void acpi_gpio_chip_dh(acpi_handle handle, void *data)
85{ 104{
86 /* The address of this function is used as a key. */ 105 /* The address of this function is used as a key. */
87} 106}
88 107
89/** 108static acpi_status acpi_gpiochip_request_interrupt(struct acpi_resource *ares,
90 * acpi_gpiochip_request_interrupts() - Register isr for gpio chip ACPI events 109 void *context)
91 * @chip: gpio chip
92 *
93 * ACPI5 platforms can use GPIO signaled ACPI events. These GPIO interrupts are
94 * handled by ACPI event methods which need to be called from the GPIO
95 * chip's interrupt handler. acpi_gpiochip_request_interrupts finds out which
96 * gpio pins have acpi event methods and assigns interrupt handlers that calls
97 * the acpi event methods for those pins.
98 */
99static void acpi_gpiochip_request_interrupts(struct gpio_chip *chip)
100{ 110{
101 struct acpi_buffer buf = {ACPI_ALLOCATE_BUFFER, NULL}; 111 struct acpi_gpio_chip *acpi_gpio = context;
102 struct acpi_resource *res; 112 struct gpio_chip *chip = acpi_gpio->chip;
113 struct acpi_resource_gpio *agpio;
103 acpi_handle handle, evt_handle; 114 acpi_handle handle, evt_handle;
104 struct list_head *evt_pins = NULL; 115 struct acpi_gpio_event *event;
105 acpi_status status; 116 irq_handler_t handler = NULL;
106 unsigned int pin; 117 struct gpio_desc *desc;
107 int irq, ret; 118 unsigned long irqflags;
108 char ev_name[5]; 119 int ret, pin, irq;
109 120
110 if (!chip->dev || !chip->to_irq) 121 if (ares->type != ACPI_RESOURCE_TYPE_GPIO)
111 return; 122 return AE_OK;
112 123
113 handle = ACPI_HANDLE(chip->dev); 124 agpio = &ares->data.gpio;
114 if (!handle) 125 if (agpio->connection_type != ACPI_RESOURCE_GPIO_TYPE_INT)
115 return; 126 return AE_OK;
116 127
117 status = acpi_get_event_resources(handle, &buf); 128 handle = ACPI_HANDLE(chip->dev);
118 if (ACPI_FAILURE(status)) 129 pin = agpio->pin_table[0];
119 return; 130
131 if (pin <= 255) {
132 char ev_name[5];
133 sprintf(ev_name, "_%c%02X",
134 agpio->triggering == ACPI_EDGE_SENSITIVE ? 'E' : 'L',
135 pin);
136 if (ACPI_SUCCESS(acpi_get_handle(handle, ev_name, &evt_handle)))
137 handler = acpi_gpio_irq_handler;
138 }
139 if (!handler) {
140 if (ACPI_SUCCESS(acpi_get_handle(handle, "_EVT", &evt_handle)))
141 handler = acpi_gpio_irq_handler_evt;
142 }
143 if (!handler)
144 return AE_BAD_PARAMETER;
120 145
121 status = acpi_get_handle(handle, "_EVT", &evt_handle); 146 desc = gpiochip_get_desc(chip, pin);
122 if (ACPI_SUCCESS(status)) { 147 if (IS_ERR(desc)) {
123 evt_pins = kzalloc(sizeof(*evt_pins), GFP_KERNEL); 148 dev_err(chip->dev, "Failed to get GPIO descriptor\n");
124 if (evt_pins) { 149 return AE_ERROR;
125 INIT_LIST_HEAD(evt_pins);
126 status = acpi_attach_data(handle, acpi_gpio_evt_dh,
127 evt_pins);
128 if (ACPI_FAILURE(status)) {
129 kfree(evt_pins);
130 evt_pins = NULL;
131 }
132 }
133 } 150 }
134 151
135 /* 152 ret = gpiochip_request_own_desc(desc, "ACPI:Event");
136 * If a GPIO interrupt has an ACPI event handler method, or _EVT is 153 if (ret) {
137 * present, set up an interrupt handler that calls the ACPI event 154 dev_err(chip->dev, "Failed to request GPIO\n");
138 * handler. 155 return AE_ERROR;
139 */ 156 }
140 for (res = buf.pointer;
141 res && (res->type != ACPI_RESOURCE_TYPE_END_TAG);
142 res = ACPI_NEXT_RESOURCE(res)) {
143 irq_handler_t handler = NULL;
144 void *data;
145
146 if (res->type != ACPI_RESOURCE_TYPE_GPIO ||
147 res->data.gpio.connection_type !=
148 ACPI_RESOURCE_GPIO_TYPE_INT)
149 continue;
150 157
151 pin = res->data.gpio.pin_table[0]; 158 gpiod_direction_input(desc);
152 if (pin > chip->ngpio)
153 continue;
154 159
155 irq = chip->to_irq(chip, pin); 160 ret = gpiod_lock_as_irq(desc);
156 if (irq < 0) 161 if (ret) {
157 continue; 162 dev_err(chip->dev, "Failed to lock GPIO as interrupt\n");
163 goto fail_free_desc;
164 }
158 165
159 if (pin <= 255) { 166 irq = gpiod_to_irq(desc);
160 acpi_handle ev_handle; 167 if (irq < 0) {
168 dev_err(chip->dev, "Failed to translate GPIO to IRQ\n");
169 goto fail_unlock_irq;
170 }
161 171
162 sprintf(ev_name, "_%c%02X", 172 irqflags = IRQF_ONESHOT;
163 res->data.gpio.triggering ? 'E' : 'L', pin); 173 if (agpio->triggering == ACPI_LEVEL_SENSITIVE) {
164 status = acpi_get_handle(handle, ev_name, &ev_handle); 174 if (agpio->polarity == ACPI_ACTIVE_HIGH)
165 if (ACPI_SUCCESS(status)) { 175 irqflags |= IRQF_TRIGGER_HIGH;
166 handler = acpi_gpio_irq_handler; 176 else
167 data = ev_handle; 177 irqflags |= IRQF_TRIGGER_LOW;
168 } 178 } else {
179 switch (agpio->polarity) {
180 case ACPI_ACTIVE_HIGH:
181 irqflags |= IRQF_TRIGGER_RISING;
182 break;
183 case ACPI_ACTIVE_LOW:
184 irqflags |= IRQF_TRIGGER_FALLING;
185 break;
186 default:
187 irqflags |= IRQF_TRIGGER_RISING |
188 IRQF_TRIGGER_FALLING;
189 break;
169 } 190 }
170 if (!handler && evt_pins) { 191 }
171 struct acpi_gpio_evt_pin *evt_pin;
172 192
173 evt_pin = kzalloc(sizeof(*evt_pin), GFP_KERNEL); 193 event = kzalloc(sizeof(*event), GFP_KERNEL);
174 if (!evt_pin) 194 if (!event)
175 continue; 195 goto fail_unlock_irq;
176 196
177 list_add_tail(&evt_pin->node, evt_pins); 197 event->handle = evt_handle;
178 evt_pin->evt_handle = evt_handle; 198 event->irq = irq;
179 evt_pin->pin = pin; 199 event->pin = pin;
180 evt_pin->irq = irq;
181 handler = acpi_gpio_irq_handler_evt;
182 data = evt_pin;
183 }
184 if (!handler)
185 continue;
186 200
187 /* Assume BIOS sets the triggering, so no flags */ 201 ret = request_threaded_irq(event->irq, NULL, handler, irqflags,
188 ret = devm_request_threaded_irq(chip->dev, irq, NULL, handler, 202 "ACPI:Event", event);
189 0, "GPIO-signaled-ACPI-event", 203 if (ret) {
190 data); 204 dev_err(chip->dev, "Failed to setup interrupt handler for %d\n",
191 if (ret) 205 event->irq);
192 dev_err(chip->dev, 206 goto fail_free_event;
193 "Failed to request IRQ %d ACPI event handler\n",
194 irq);
195 } 207 }
208
209 list_add_tail(&event->node, &acpi_gpio->events);
210 return AE_OK;
211
212fail_free_event:
213 kfree(event);
214fail_unlock_irq:
215 gpiod_unlock_as_irq(desc);
216fail_free_desc:
217 gpiochip_free_own_desc(desc);
218
219 return AE_ERROR;
196} 220}
197 221
198/** 222/**
199 * acpi_gpiochip_free_interrupts() - Free GPIO _EVT ACPI event interrupts. 223 * acpi_gpiochip_request_interrupts() - Register isr for gpio chip ACPI events
200 * @chip: gpio chip 224 * @acpi_gpio: ACPI GPIO chip
201 *
202 * Free interrupts associated with the _EVT method for the given GPIO chip.
203 * 225 *
204 * The remaining ACPI event interrupts associated with the chip are freed 226 * ACPI5 platforms can use GPIO signaled ACPI events. These GPIO interrupts are
205 * automatically. 227 * handled by ACPI event methods which need to be called from the GPIO
228 * chip's interrupt handler. acpi_gpiochip_request_interrupts finds out which
229 * gpio pins have acpi event methods and assigns interrupt handlers that calls
230 * the acpi event methods for those pins.
206 */ 231 */
207static void acpi_gpiochip_free_interrupts(struct gpio_chip *chip) 232static void acpi_gpiochip_request_interrupts(struct acpi_gpio_chip *acpi_gpio)
208{ 233{
209 acpi_handle handle; 234 struct gpio_chip *chip = acpi_gpio->chip;
210 acpi_status status;
211 struct list_head *evt_pins;
212 struct acpi_gpio_evt_pin *evt_pin, *ep;
213 235
214 if (!chip->dev || !chip->to_irq) 236 if (!chip->to_irq)
215 return; 237 return;
216 238
217 handle = ACPI_HANDLE(chip->dev); 239 INIT_LIST_HEAD(&acpi_gpio->events);
218 if (!handle) 240 acpi_walk_resources(ACPI_HANDLE(chip->dev), "_AEI",
219 return; 241 acpi_gpiochip_request_interrupt, acpi_gpio);
242}
220 243
221 status = acpi_get_data(handle, acpi_gpio_evt_dh, (void **)&evt_pins); 244/**
222 if (ACPI_FAILURE(status)) 245 * acpi_gpiochip_free_interrupts() - Free GPIO ACPI event interrupts.
246 * @acpi_gpio: ACPI GPIO chip
247 *
248 * Free interrupts associated with GPIO ACPI event method for the given
249 * GPIO chip.
250 */
251static void acpi_gpiochip_free_interrupts(struct acpi_gpio_chip *acpi_gpio)
252{
253 struct acpi_gpio_event *event, *ep;
254 struct gpio_chip *chip = acpi_gpio->chip;
255
256 if (!chip->to_irq)
223 return; 257 return;
224 258
225 list_for_each_entry_safe_reverse(evt_pin, ep, evt_pins, node) { 259 list_for_each_entry_safe_reverse(event, ep, &acpi_gpio->events, node) {
226 devm_free_irq(chip->dev, evt_pin->irq, evt_pin); 260 struct gpio_desc *desc;
227 list_del(&evt_pin->node);
228 kfree(evt_pin);
229 }
230 261
231 acpi_detach_data(handle, acpi_gpio_evt_dh); 262 free_irq(event->irq, event);
232 kfree(evt_pins); 263 desc = gpiochip_get_desc(chip, event->pin);
264 if (WARN_ON(IS_ERR(desc)))
265 continue;
266 gpiod_unlock_as_irq(desc);
267 gpiochip_free_own_desc(desc);
268 list_del(&event->node);
269 kfree(event);
270 }
233} 271}
234 272
235struct acpi_gpio_lookup { 273struct acpi_gpio_lookup {
@@ -310,12 +348,208 @@ struct gpio_desc *acpi_get_gpiod_by_index(struct device *dev, int index,
310 return lookup.desc ? lookup.desc : ERR_PTR(-ENOENT); 348 return lookup.desc ? lookup.desc : ERR_PTR(-ENOENT);
311} 349}
312 350
351static acpi_status
352acpi_gpio_adr_space_handler(u32 function, acpi_physical_address address,
353 u32 bits, u64 *value, void *handler_context,
354 void *region_context)
355{
356 struct acpi_gpio_chip *achip = region_context;
357 struct gpio_chip *chip = achip->chip;
358 struct acpi_resource_gpio *agpio;
359 struct acpi_resource *ares;
360 acpi_status status;
361 bool pull_up;
362 int i;
363
364 status = acpi_buffer_to_resource(achip->conn_info.connection,
365 achip->conn_info.length, &ares);
366 if (ACPI_FAILURE(status))
367 return status;
368
369 if (WARN_ON(ares->type != ACPI_RESOURCE_TYPE_GPIO)) {
370 ACPI_FREE(ares);
371 return AE_BAD_PARAMETER;
372 }
373
374 agpio = &ares->data.gpio;
375 pull_up = agpio->pin_config == ACPI_PIN_CONFIG_PULLUP;
376
377 if (WARN_ON(agpio->io_restriction == ACPI_IO_RESTRICT_INPUT &&
378 function == ACPI_WRITE)) {
379 ACPI_FREE(ares);
380 return AE_BAD_PARAMETER;
381 }
382
383 for (i = 0; i < agpio->pin_table_length; i++) {
384 unsigned pin = agpio->pin_table[i];
385 struct acpi_gpio_connection *conn;
386 struct gpio_desc *desc;
387 bool found;
388
389 desc = gpiochip_get_desc(chip, pin);
390 if (IS_ERR(desc)) {
391 status = AE_ERROR;
392 goto out;
393 }
394
395 mutex_lock(&achip->conn_lock);
396
397 found = false;
398 list_for_each_entry(conn, &achip->conns, node) {
399 if (conn->desc == desc) {
400 found = true;
401 break;
402 }
403 }
404 if (!found) {
405 int ret;
406
407 ret = gpiochip_request_own_desc(desc, "ACPI:OpRegion");
408 if (ret) {
409 status = AE_ERROR;
410 mutex_unlock(&achip->conn_lock);
411 goto out;
412 }
413
414 switch (agpio->io_restriction) {
415 case ACPI_IO_RESTRICT_INPUT:
416 gpiod_direction_input(desc);
417 break;
418 case ACPI_IO_RESTRICT_OUTPUT:
419 /*
420 * ACPI GPIO resources don't contain an
421 * initial value for the GPIO. Therefore we
422 * deduce that value from the pull field
423 * instead. If the pin is pulled up we
424 * assume default to be high, otherwise
425 * low.
426 */
427 gpiod_direction_output(desc, pull_up);
428 break;
429 default:
430 /*
431 * Assume that the BIOS has configured the
432 * direction and pull accordingly.
433 */
434 break;
435 }
436
437 conn = kzalloc(sizeof(*conn), GFP_KERNEL);
438 if (!conn) {
439 status = AE_NO_MEMORY;
440 gpiochip_free_own_desc(desc);
441 mutex_unlock(&achip->conn_lock);
442 goto out;
443 }
444
445 conn->desc = desc;
446 list_add_tail(&conn->node, &achip->conns);
447 }
448
449 mutex_unlock(&achip->conn_lock);
450
451 if (function == ACPI_WRITE)
452 gpiod_set_raw_value(desc, !!((1 << i) & *value));
453 else
454 *value |= (u64)gpiod_get_raw_value(desc) << i;
455 }
456
457out:
458 ACPI_FREE(ares);
459 return status;
460}
461
462static void acpi_gpiochip_request_regions(struct acpi_gpio_chip *achip)
463{
464 struct gpio_chip *chip = achip->chip;
465 acpi_handle handle = ACPI_HANDLE(chip->dev);
466 acpi_status status;
467
468 INIT_LIST_HEAD(&achip->conns);
469 mutex_init(&achip->conn_lock);
470 status = acpi_install_address_space_handler(handle, ACPI_ADR_SPACE_GPIO,
471 acpi_gpio_adr_space_handler,
472 NULL, achip);
473 if (ACPI_FAILURE(status))
474 dev_err(chip->dev, "Failed to install GPIO OpRegion handler\n");
475}
476
477static void acpi_gpiochip_free_regions(struct acpi_gpio_chip *achip)
478{
479 struct gpio_chip *chip = achip->chip;
480 acpi_handle handle = ACPI_HANDLE(chip->dev);
481 struct acpi_gpio_connection *conn, *tmp;
482 acpi_status status;
483
484 status = acpi_remove_address_space_handler(handle, ACPI_ADR_SPACE_GPIO,
485 acpi_gpio_adr_space_handler);
486 if (ACPI_FAILURE(status)) {
487 dev_err(chip->dev, "Failed to remove GPIO OpRegion handler\n");
488 return;
489 }
490
491 list_for_each_entry_safe_reverse(conn, tmp, &achip->conns, node) {
492 gpiochip_free_own_desc(conn->desc);
493 list_del(&conn->node);
494 kfree(conn);
495 }
496}
497
313void acpi_gpiochip_add(struct gpio_chip *chip) 498void acpi_gpiochip_add(struct gpio_chip *chip)
314{ 499{
315 acpi_gpiochip_request_interrupts(chip); 500 struct acpi_gpio_chip *acpi_gpio;
501 acpi_handle handle;
502 acpi_status status;
503
504 if (!chip || !chip->dev)
505 return;
506
507 handle = ACPI_HANDLE(chip->dev);
508 if (!handle)
509 return;
510
511 acpi_gpio = kzalloc(sizeof(*acpi_gpio), GFP_KERNEL);
512 if (!acpi_gpio) {
513 dev_err(chip->dev,
514 "Failed to allocate memory for ACPI GPIO chip\n");
515 return;
516 }
517
518 acpi_gpio->chip = chip;
519
520 status = acpi_attach_data(handle, acpi_gpio_chip_dh, acpi_gpio);
521 if (ACPI_FAILURE(status)) {
522 dev_err(chip->dev, "Failed to attach ACPI GPIO chip\n");
523 kfree(acpi_gpio);
524 return;
525 }
526
527 acpi_gpiochip_request_interrupts(acpi_gpio);
528 acpi_gpiochip_request_regions(acpi_gpio);
316} 529}
317 530
318void acpi_gpiochip_remove(struct gpio_chip *chip) 531void acpi_gpiochip_remove(struct gpio_chip *chip)
319{ 532{
320 acpi_gpiochip_free_interrupts(chip); 533 struct acpi_gpio_chip *acpi_gpio;
534 acpi_handle handle;
535 acpi_status status;
536
537 if (!chip || !chip->dev)
538 return;
539
540 handle = ACPI_HANDLE(chip->dev);
541 if (!handle)
542 return;
543
544 status = acpi_get_data(handle, acpi_gpio_chip_dh, (void **)&acpi_gpio);
545 if (ACPI_FAILURE(status)) {
546 dev_warn(chip->dev, "Failed to retrieve ACPI GPIO chip\n");
547 return;
548 }
549
550 acpi_gpiochip_free_regions(acpi_gpio);
551 acpi_gpiochip_free_interrupts(acpi_gpio);
552
553 acpi_detach_data(handle, acpi_gpio_chip_dh);
554 kfree(acpi_gpio);
321} 555}
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index e0a98f581f58..2024d45e5503 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -12,6 +12,7 @@
12 */ 12 */
13 13
14#include <linux/device.h> 14#include <linux/device.h>
15#include <linux/err.h>
15#include <linux/errno.h> 16#include <linux/errno.h>
16#include <linux/module.h> 17#include <linux/module.h>
17#include <linux/io.h> 18#include <linux/io.h>
@@ -90,7 +91,7 @@ struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np,
90 91
91 of_node_put(gg_data.gpiospec.np); 92 of_node_put(gg_data.gpiospec.np);
92 pr_debug("%s exited with status %d\n", __func__, 93 pr_debug("%s exited with status %d\n", __func__,
93 PTR_RET(gg_data.out_gpio)); 94 PTR_ERR_OR_ZERO(gg_data.out_gpio));
94 return gg_data.out_gpio; 95 return gg_data.out_gpio;
95} 96}
96EXPORT_SYMBOL(of_get_named_gpiod_flags); 97EXPORT_SYMBOL(of_get_named_gpiod_flags);
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 50c4922fe53a..f48817d97480 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -164,16 +164,17 @@ struct gpio_desc *gpio_to_desc(unsigned gpio)
164EXPORT_SYMBOL_GPL(gpio_to_desc); 164EXPORT_SYMBOL_GPL(gpio_to_desc);
165 165
166/** 166/**
167 * Convert an offset on a certain chip to a corresponding descriptor 167 * Get the GPIO descriptor corresponding to the given hw number for this chip.
168 */ 168 */
169static struct gpio_desc *gpiochip_offset_to_desc(struct gpio_chip *chip, 169struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip,
170 unsigned int offset) 170 u16 hwnum)
171{ 171{
172 if (offset >= chip->ngpio) 172 if (hwnum >= chip->ngpio)
173 return ERR_PTR(-EINVAL); 173 return ERR_PTR(-EINVAL);
174 174
175 return &chip->desc[offset]; 175 return &chip->desc[hwnum];
176} 176}
177EXPORT_SYMBOL_GPL(gpiochip_get_desc);
177 178
178/** 179/**
179 * Convert a GPIO descriptor to the integer namespace. 180 * Convert a GPIO descriptor to the integer namespace.
@@ -350,9 +351,9 @@ static ssize_t gpio_direction_store(struct device *dev,
350 if (!test_bit(FLAG_EXPORT, &desc->flags)) 351 if (!test_bit(FLAG_EXPORT, &desc->flags))
351 status = -EIO; 352 status = -EIO;
352 else if (sysfs_streq(buf, "high")) 353 else if (sysfs_streq(buf, "high"))
353 status = gpiod_direction_output(desc, 1); 354 status = gpiod_direction_output_raw(desc, 1);
354 else if (sysfs_streq(buf, "out") || sysfs_streq(buf, "low")) 355 else if (sysfs_streq(buf, "out") || sysfs_streq(buf, "low"))
355 status = gpiod_direction_output(desc, 0); 356 status = gpiod_direction_output_raw(desc, 0);
356 else if (sysfs_streq(buf, "in")) 357 else if (sysfs_streq(buf, "in"))
357 status = gpiod_direction_input(desc); 358 status = gpiod_direction_input(desc);
358 else 359 else
@@ -1253,6 +1254,9 @@ fail:
1253} 1254}
1254EXPORT_SYMBOL_GPL(gpiochip_add); 1255EXPORT_SYMBOL_GPL(gpiochip_add);
1255 1256
1257/* Forward-declaration */
1258static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip);
1259
1256/** 1260/**
1257 * gpiochip_remove() - unregister a gpio_chip 1261 * gpiochip_remove() - unregister a gpio_chip
1258 * @chip: the chip to unregister 1262 * @chip: the chip to unregister
@@ -1265,11 +1269,13 @@ int gpiochip_remove(struct gpio_chip *chip)
1265 int status = 0; 1269 int status = 0;
1266 unsigned id; 1270 unsigned id;
1267 1271
1272 acpi_gpiochip_remove(chip);
1273
1268 spin_lock_irqsave(&gpio_lock, flags); 1274 spin_lock_irqsave(&gpio_lock, flags);
1269 1275
1276 gpiochip_irqchip_remove(chip);
1270 gpiochip_remove_pin_ranges(chip); 1277 gpiochip_remove_pin_ranges(chip);
1271 of_gpiochip_remove(chip); 1278 of_gpiochip_remove(chip);
1272 acpi_gpiochip_remove(chip);
1273 1279
1274 for (id = 0; id < chip->ngpio; id++) { 1280 for (id = 0; id < chip->ngpio; id++) {
1275 if (test_bit(FLAG_REQUESTED, &chip->desc[id].flags)) { 1281 if (test_bit(FLAG_REQUESTED, &chip->desc[id].flags)) {
@@ -1337,6 +1343,215 @@ static struct gpio_chip *find_chip_by_name(const char *name)
1337 return gpiochip_find((void *)name, gpiochip_match_name); 1343 return gpiochip_find((void *)name, gpiochip_match_name);
1338} 1344}
1339 1345
1346#ifdef CONFIG_GPIOLIB_IRQCHIP
1347
1348/*
1349 * The following is irqchip helper code for gpiochips.
1350 */
1351
1352/**
1353 * gpiochip_add_chained_irqchip() - adds a chained irqchip to a gpiochip
1354 * @gpiochip: the gpiochip to add the irqchip to
1355 * @irqchip: the irqchip to add to the gpiochip
1356 * @parent_irq: the irq number corresponding to the parent IRQ for this
1357 * chained irqchip
1358 * @parent_handler: the parent interrupt handler for the accumulated IRQ
1359 * coming out of the gpiochip
1360 */
1361void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
1362 struct irq_chip *irqchip,
1363 int parent_irq,
1364 irq_flow_handler_t parent_handler)
1365{
1366 irq_set_chained_handler(parent_irq, parent_handler);
1367 /*
1368 * The parent irqchip is already using the chip_data for this
1369 * irqchip, so our callbacks simply use the handler_data.
1370 */
1371 irq_set_handler_data(parent_irq, gpiochip);
1372}
1373EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip);
1374
1375/**
1376 * gpiochip_irq_map() - maps an IRQ into a GPIO irqchip
1377 * @d: the irqdomain used by this irqchip
1378 * @irq: the global irq number used by this GPIO irqchip irq
1379 * @hwirq: the local IRQ/GPIO line offset on this gpiochip
1380 *
1381 * This function will set up the mapping for a certain IRQ line on a
1382 * gpiochip by assigning the gpiochip as chip data, and using the irqchip
1383 * stored inside the gpiochip.
1384 */
1385static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
1386 irq_hw_number_t hwirq)
1387{
1388 struct gpio_chip *chip = d->host_data;
1389
1390 irq_set_chip_data(irq, chip);
1391 irq_set_chip_and_handler(irq, chip->irqchip, chip->irq_handler);
1392#ifdef CONFIG_ARM
1393 set_irq_flags(irq, IRQF_VALID);
1394#else
1395 irq_set_noprobe(irq);
1396#endif
1397 irq_set_irq_type(irq, chip->irq_default_type);
1398
1399 return 0;
1400}
1401
1402static void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)
1403{
1404#ifdef CONFIG_ARM
1405 set_irq_flags(irq, 0);
1406#endif
1407 irq_set_chip_and_handler(irq, NULL, NULL);
1408 irq_set_chip_data(irq, NULL);
1409}
1410
1411static const struct irq_domain_ops gpiochip_domain_ops = {
1412 .map = gpiochip_irq_map,
1413 .unmap = gpiochip_irq_unmap,
1414 /* Virtually all GPIO irqchips are twocell:ed */
1415 .xlate = irq_domain_xlate_twocell,
1416};
1417
1418static int gpiochip_irq_reqres(struct irq_data *d)
1419{
1420 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
1421
1422 if (gpio_lock_as_irq(chip, d->hwirq)) {
1423 chip_err(chip,
1424 "unable to lock HW IRQ %lu for IRQ\n",
1425 d->hwirq);
1426 return -EINVAL;
1427 }
1428 return 0;
1429}
1430
1431static void gpiochip_irq_relres(struct irq_data *d)
1432{
1433 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
1434
1435 gpio_unlock_as_irq(chip, d->hwirq);
1436}
1437
1438static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset)
1439{
1440 return irq_find_mapping(chip->irqdomain, offset);
1441}
1442
1443/**
1444 * gpiochip_irqchip_remove() - removes an irqchip added to a gpiochip
1445 * @gpiochip: the gpiochip to remove the irqchip from
1446 *
1447 * This is called only from gpiochip_remove()
1448 */
1449static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip)
1450{
1451 unsigned int offset;
1452
1453 /* Remove all IRQ mappings and delete the domain */
1454 if (gpiochip->irqdomain) {
1455 for (offset = 0; offset < gpiochip->ngpio; offset++)
1456 irq_dispose_mapping(gpiochip->irq_base + offset);
1457 irq_domain_remove(gpiochip->irqdomain);
1458 }
1459
1460 if (gpiochip->irqchip) {
1461 gpiochip->irqchip->irq_request_resources = NULL;
1462 gpiochip->irqchip->irq_release_resources = NULL;
1463 gpiochip->irqchip = NULL;
1464 }
1465}
1466
1467/**
1468 * gpiochip_irqchip_add() - adds an irqchip to a gpiochip
1469 * @gpiochip: the gpiochip to add the irqchip to
1470 * @irqchip: the irqchip to add to the gpiochip
1471 * @first_irq: if not dynamically assigned, the base (first) IRQ to
1472 * allocate gpiochip irqs from
1473 * @handler: the irq handler to use (often a predefined irq core function)
1474 * @type: the default type for IRQs on this irqchip
1475 *
1476 * This function closely associates a certain irqchip with a certain
1477 * gpiochip, providing an irq domain to translate the local IRQs to
1478 * global irqs in the gpiolib core, and making sure that the gpiochip
1479 * is passed as chip data to all related functions. Driver callbacks
1480 * need to use container_of() to get their local state containers back
1481 * from the gpiochip passed as chip data. An irqdomain will be stored
1482 * in the gpiochip that shall be used by the driver to handle IRQ number
1483 * translation. The gpiochip will need to be initialized and registered
1484 * before calling this function.
1485 *
1486 * This function will handle two cell:ed simple IRQs and assumes all
1487 * the pins on the gpiochip can generate a unique IRQ. Everything else
1488 * need to be open coded.
1489 */
1490int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
1491 struct irq_chip *irqchip,
1492 unsigned int first_irq,
1493 irq_flow_handler_t handler,
1494 unsigned int type)
1495{
1496 struct device_node *of_node;
1497 unsigned int offset;
1498 unsigned irq_base = 0;
1499
1500 if (!gpiochip || !irqchip)
1501 return -EINVAL;
1502
1503 if (!gpiochip->dev) {
1504 pr_err("missing gpiochip .dev parent pointer\n");
1505 return -EINVAL;
1506 }
1507 of_node = gpiochip->dev->of_node;
1508#ifdef CONFIG_OF_GPIO
1509 /*
1510 * If the gpiochip has an assigned OF node this takes precendence
1511 * FIXME: get rid of this and use gpiochip->dev->of_node everywhere
1512 */
1513 if (gpiochip->of_node)
1514 of_node = gpiochip->of_node;
1515#endif
1516 gpiochip->irqchip = irqchip;
1517 gpiochip->irq_handler = handler;
1518 gpiochip->irq_default_type = type;
1519 gpiochip->to_irq = gpiochip_to_irq;
1520 gpiochip->irqdomain = irq_domain_add_simple(of_node,
1521 gpiochip->ngpio, first_irq,
1522 &gpiochip_domain_ops, gpiochip);
1523 if (!gpiochip->irqdomain) {
1524 gpiochip->irqchip = NULL;
1525 return -EINVAL;
1526 }
1527 irqchip->irq_request_resources = gpiochip_irq_reqres;
1528 irqchip->irq_release_resources = gpiochip_irq_relres;
1529
1530 /*
1531 * Prepare the mapping since the irqchip shall be orthogonal to
1532 * any gpiochip calls. If the first_irq was zero, this is
1533 * necessary to allocate descriptors for all IRQs.
1534 */
1535 for (offset = 0; offset < gpiochip->ngpio; offset++) {
1536 irq_base = irq_create_mapping(gpiochip->irqdomain, offset);
1537 if (offset == 0)
1538 /*
1539 * Store the base into the gpiochip to be used when
1540 * unmapping the irqs.
1541 */
1542 gpiochip->irq_base = irq_base;
1543 }
1544
1545 return 0;
1546}
1547EXPORT_SYMBOL_GPL(gpiochip_irqchip_add);
1548
1549#else /* CONFIG_GPIOLIB_IRQCHIP */
1550
1551static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) {}
1552
1553#endif /* CONFIG_GPIOLIB_IRQCHIP */
1554
1340#ifdef CONFIG_PINCTRL 1555#ifdef CONFIG_PINCTRL
1341 1556
1342/** 1557/**
@@ -1457,26 +1672,14 @@ EXPORT_SYMBOL_GPL(gpiochip_remove_pin_ranges);
1457 * on each other, and help provide better diagnostics in debugfs. 1672 * on each other, and help provide better diagnostics in debugfs.
1458 * They're called even less than the "set direction" calls. 1673 * They're called even less than the "set direction" calls.
1459 */ 1674 */
1460static int gpiod_request(struct gpio_desc *desc, const char *label) 1675static int __gpiod_request(struct gpio_desc *desc, const char *label)
1461{ 1676{
1462 struct gpio_chip *chip; 1677 struct gpio_chip *chip = desc->chip;
1463 int status = -EPROBE_DEFER; 1678 int status;
1464 unsigned long flags; 1679 unsigned long flags;
1465 1680
1466 if (!desc) {
1467 pr_warn("%s: invalid GPIO\n", __func__);
1468 return -EINVAL;
1469 }
1470
1471 spin_lock_irqsave(&gpio_lock, flags); 1681 spin_lock_irqsave(&gpio_lock, flags);
1472 1682
1473 chip = desc->chip;
1474 if (chip == NULL)
1475 goto done;
1476
1477 if (!try_module_get(chip->owner))
1478 goto done;
1479
1480 /* NOTE: gpio_request() can be called in early boot, 1683 /* NOTE: gpio_request() can be called in early boot,
1481 * before IRQs are enabled, for non-sleeping (SOC) GPIOs. 1684 * before IRQs are enabled, for non-sleeping (SOC) GPIOs.
1482 */ 1685 */
@@ -1486,7 +1689,6 @@ static int gpiod_request(struct gpio_desc *desc, const char *label)
1486 status = 0; 1689 status = 0;
1487 } else { 1690 } else {
1488 status = -EBUSY; 1691 status = -EBUSY;
1489 module_put(chip->owner);
1490 goto done; 1692 goto done;
1491 } 1693 }
1492 1694
@@ -1498,7 +1700,6 @@ static int gpiod_request(struct gpio_desc *desc, const char *label)
1498 1700
1499 if (status < 0) { 1701 if (status < 0) {
1500 desc_set_label(desc, NULL); 1702 desc_set_label(desc, NULL);
1501 module_put(chip->owner);
1502 clear_bit(FLAG_REQUESTED, &desc->flags); 1703 clear_bit(FLAG_REQUESTED, &desc->flags);
1503 goto done; 1704 goto done;
1504 } 1705 }
@@ -1510,9 +1711,34 @@ static int gpiod_request(struct gpio_desc *desc, const char *label)
1510 spin_lock_irqsave(&gpio_lock, flags); 1711 spin_lock_irqsave(&gpio_lock, flags);
1511 } 1712 }
1512done: 1713done:
1714 spin_unlock_irqrestore(&gpio_lock, flags);
1715 return status;
1716}
1717
1718static int gpiod_request(struct gpio_desc *desc, const char *label)
1719{
1720 int status = -EPROBE_DEFER;
1721 struct gpio_chip *chip;
1722
1723 if (!desc) {
1724 pr_warn("%s: invalid GPIO\n", __func__);
1725 return -EINVAL;
1726 }
1727
1728 chip = desc->chip;
1729 if (!chip)
1730 goto done;
1731
1732 if (try_module_get(chip->owner)) {
1733 status = __gpiod_request(desc, label);
1734 if (status < 0)
1735 module_put(chip->owner);
1736 }
1737
1738done:
1513 if (status) 1739 if (status)
1514 gpiod_dbg(desc, "%s: status %d\n", __func__, status); 1740 gpiod_dbg(desc, "%s: status %d\n", __func__, status);
1515 spin_unlock_irqrestore(&gpio_lock, flags); 1741
1516 return status; 1742 return status;
1517} 1743}
1518 1744
@@ -1522,18 +1748,14 @@ int gpio_request(unsigned gpio, const char *label)
1522} 1748}
1523EXPORT_SYMBOL_GPL(gpio_request); 1749EXPORT_SYMBOL_GPL(gpio_request);
1524 1750
1525static void gpiod_free(struct gpio_desc *desc) 1751static bool __gpiod_free(struct gpio_desc *desc)
1526{ 1752{
1753 bool ret = false;
1527 unsigned long flags; 1754 unsigned long flags;
1528 struct gpio_chip *chip; 1755 struct gpio_chip *chip;
1529 1756
1530 might_sleep(); 1757 might_sleep();
1531 1758
1532 if (!desc) {
1533 WARN_ON(extra_checks);
1534 return;
1535 }
1536
1537 gpiod_unexport(desc); 1759 gpiod_unexport(desc);
1538 1760
1539 spin_lock_irqsave(&gpio_lock, flags); 1761 spin_lock_irqsave(&gpio_lock, flags);
@@ -1547,15 +1769,23 @@ static void gpiod_free(struct gpio_desc *desc)
1547 spin_lock_irqsave(&gpio_lock, flags); 1769 spin_lock_irqsave(&gpio_lock, flags);
1548 } 1770 }
1549 desc_set_label(desc, NULL); 1771 desc_set_label(desc, NULL);
1550 module_put(desc->chip->owner);
1551 clear_bit(FLAG_ACTIVE_LOW, &desc->flags); 1772 clear_bit(FLAG_ACTIVE_LOW, &desc->flags);
1552 clear_bit(FLAG_REQUESTED, &desc->flags); 1773 clear_bit(FLAG_REQUESTED, &desc->flags);
1553 clear_bit(FLAG_OPEN_DRAIN, &desc->flags); 1774 clear_bit(FLAG_OPEN_DRAIN, &desc->flags);
1554 clear_bit(FLAG_OPEN_SOURCE, &desc->flags); 1775 clear_bit(FLAG_OPEN_SOURCE, &desc->flags);
1555 } else 1776 ret = true;
1556 WARN_ON(extra_checks); 1777 }
1557 1778
1558 spin_unlock_irqrestore(&gpio_lock, flags); 1779 spin_unlock_irqrestore(&gpio_lock, flags);
1780 return ret;
1781}
1782
1783static void gpiod_free(struct gpio_desc *desc)
1784{
1785 if (desc && __gpiod_free(desc))
1786 module_put(desc->chip->owner);
1787 else
1788 WARN_ON(extra_checks);
1559} 1789}
1560 1790
1561void gpio_free(unsigned gpio) 1791void gpio_free(unsigned gpio)
@@ -1590,7 +1820,7 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
1590 if (flags & GPIOF_DIR_IN) 1820 if (flags & GPIOF_DIR_IN)
1591 err = gpiod_direction_input(desc); 1821 err = gpiod_direction_input(desc);
1592 else 1822 else
1593 err = gpiod_direction_output(desc, 1823 err = gpiod_direction_output_raw(desc,
1594 (flags & GPIOF_INIT_HIGH) ? 1 : 0); 1824 (flags & GPIOF_INIT_HIGH) ? 1 : 0);
1595 1825
1596 if (err) 1826 if (err)
@@ -1677,6 +1907,37 @@ const char *gpiochip_is_requested(struct gpio_chip *chip, unsigned offset)
1677} 1907}
1678EXPORT_SYMBOL_GPL(gpiochip_is_requested); 1908EXPORT_SYMBOL_GPL(gpiochip_is_requested);
1679 1909
1910/**
1911 * gpiochip_request_own_desc - Allow GPIO chip to request its own descriptor
1912 * @desc: GPIO descriptor to request
1913 * @label: label for the GPIO
1914 *
1915 * Function allows GPIO chip drivers to request and use their own GPIO
1916 * descriptors via gpiolib API. Difference to gpiod_request() is that this
1917 * function will not increase reference count of the GPIO chip module. This
1918 * allows the GPIO chip module to be unloaded as needed (we assume that the
1919 * GPIO chip driver handles freeing the GPIOs it has requested).
1920 */
1921int gpiochip_request_own_desc(struct gpio_desc *desc, const char *label)
1922{
1923 if (!desc || !desc->chip)
1924 return -EINVAL;
1925
1926 return __gpiod_request(desc, label);
1927}
1928
1929/**
1930 * gpiochip_free_own_desc - Free GPIO requested by the chip driver
1931 * @desc: GPIO descriptor to free
1932 *
1933 * Function frees the given GPIO requested previously with
1934 * gpiochip_request_own_desc().
1935 */
1936void gpiochip_free_own_desc(struct gpio_desc *desc)
1937{
1938 if (desc)
1939 __gpiod_free(desc);
1940}
1680 1941
1681/* Drivers MUST set GPIO direction before making get/set calls. In 1942/* Drivers MUST set GPIO direction before making get/set calls. In
1682 * some cases this is done in early boot, before IRQs are enabled. 1943 * some cases this is done in early boot, before IRQs are enabled.
@@ -1756,28 +2017,13 @@ fail:
1756} 2017}
1757EXPORT_SYMBOL_GPL(gpiod_direction_input); 2018EXPORT_SYMBOL_GPL(gpiod_direction_input);
1758 2019
1759/** 2020static int _gpiod_direction_output_raw(struct gpio_desc *desc, int value)
1760 * gpiod_direction_output - set the GPIO direction to input
1761 * @desc: GPIO to set to output
1762 * @value: initial output value of the GPIO
1763 *
1764 * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
1765 * be called safely on it. The initial value of the output must be specified.
1766 *
1767 * Return 0 in case of success, else an error code.
1768 */
1769int gpiod_direction_output(struct gpio_desc *desc, int value)
1770{ 2021{
1771 unsigned long flags; 2022 unsigned long flags;
1772 struct gpio_chip *chip; 2023 struct gpio_chip *chip;
1773 int status = -EINVAL; 2024 int status = -EINVAL;
1774 int offset; 2025 int offset;
1775 2026
1776 if (!desc || !desc->chip) {
1777 pr_warn("%s: invalid GPIO\n", __func__);
1778 return -EINVAL;
1779 }
1780
1781 /* GPIOs used for IRQs shall not be set as output */ 2027 /* GPIOs used for IRQs shall not be set as output */
1782 if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) { 2028 if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
1783 gpiod_err(desc, 2029 gpiod_err(desc,
@@ -1840,6 +2086,50 @@ fail:
1840 gpiod_dbg(desc, "%s: gpio status %d\n", __func__, status); 2086 gpiod_dbg(desc, "%s: gpio status %d\n", __func__, status);
1841 return status; 2087 return status;
1842} 2088}
2089
2090/**
2091 * gpiod_direction_output_raw - set the GPIO direction to output
2092 * @desc: GPIO to set to output
2093 * @value: initial output value of the GPIO
2094 *
2095 * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
2096 * be called safely on it. The initial value of the output must be specified
2097 * as raw value on the physical line without regard for the ACTIVE_LOW status.
2098 *
2099 * Return 0 in case of success, else an error code.
2100 */
2101int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
2102{
2103 if (!desc || !desc->chip) {
2104 pr_warn("%s: invalid GPIO\n", __func__);
2105 return -EINVAL;
2106 }
2107 return _gpiod_direction_output_raw(desc, value);
2108}
2109EXPORT_SYMBOL_GPL(gpiod_direction_output_raw);
2110
2111/**
2112 * gpiod_direction_output - set the GPIO direction to output
2113 * @desc: GPIO to set to output
2114 * @value: initial output value of the GPIO
2115 *
2116 * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
2117 * be called safely on it. The initial value of the output must be specified
2118 * as the logical value of the GPIO, i.e. taking its ACTIVE_LOW status into
2119 * account.
2120 *
2121 * Return 0 in case of success, else an error code.
2122 */
2123int gpiod_direction_output(struct gpio_desc *desc, int value)
2124{
2125 if (!desc || !desc->chip) {
2126 pr_warn("%s: invalid GPIO\n", __func__);
2127 return -EINVAL;
2128 }
2129 if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
2130 value = !value;
2131 return _gpiod_direction_output_raw(desc, value);
2132}
1843EXPORT_SYMBOL_GPL(gpiod_direction_output); 2133EXPORT_SYMBOL_GPL(gpiod_direction_output);
1844 2134
1845/** 2135/**
@@ -1928,15 +2218,15 @@ EXPORT_SYMBOL_GPL(gpiod_is_active_low);
1928 * that the GPIO was actually requested. 2218 * that the GPIO was actually requested.
1929 */ 2219 */
1930 2220
1931static int _gpiod_get_raw_value(const struct gpio_desc *desc) 2221static bool _gpiod_get_raw_value(const struct gpio_desc *desc)
1932{ 2222{
1933 struct gpio_chip *chip; 2223 struct gpio_chip *chip;
1934 int value; 2224 bool value;
1935 int offset; 2225 int offset;
1936 2226
1937 chip = desc->chip; 2227 chip = desc->chip;
1938 offset = gpio_chip_hwgpio(desc); 2228 offset = gpio_chip_hwgpio(desc);
1939 value = chip->get ? chip->get(chip, offset) : 0; 2229 value = chip->get ? chip->get(chip, offset) : false;
1940 trace_gpio_value(desc_to_gpio(desc), 1, value); 2230 trace_gpio_value(desc_to_gpio(desc), 1, value);
1941 return value; 2231 return value;
1942} 2232}
@@ -1992,7 +2282,7 @@ EXPORT_SYMBOL_GPL(gpiod_get_value);
1992 * @desc: gpio descriptor whose state need to be set. 2282 * @desc: gpio descriptor whose state need to be set.
1993 * @value: Non-zero for setting it HIGH otherise it will set to LOW. 2283 * @value: Non-zero for setting it HIGH otherise it will set to LOW.
1994 */ 2284 */
1995static void _gpio_set_open_drain_value(struct gpio_desc *desc, int value) 2285static void _gpio_set_open_drain_value(struct gpio_desc *desc, bool value)
1996{ 2286{
1997 int err = 0; 2287 int err = 0;
1998 struct gpio_chip *chip = desc->chip; 2288 struct gpio_chip *chip = desc->chip;
@@ -2019,7 +2309,7 @@ static void _gpio_set_open_drain_value(struct gpio_desc *desc, int value)
2019 * @desc: gpio descriptor whose state need to be set. 2309 * @desc: gpio descriptor whose state need to be set.
2020 * @value: Non-zero for setting it HIGH otherise it will set to LOW. 2310 * @value: Non-zero for setting it HIGH otherise it will set to LOW.
2021 */ 2311 */
2022static void _gpio_set_open_source_value(struct gpio_desc *desc, int value) 2312static void _gpio_set_open_source_value(struct gpio_desc *desc, bool value)
2023{ 2313{
2024 int err = 0; 2314 int err = 0;
2025 struct gpio_chip *chip = desc->chip; 2315 struct gpio_chip *chip = desc->chip;
@@ -2041,7 +2331,7 @@ static void _gpio_set_open_source_value(struct gpio_desc *desc, int value)
2041 __func__, err); 2331 __func__, err);
2042} 2332}
2043 2333
2044static void _gpiod_set_raw_value(struct gpio_desc *desc, int value) 2334static void _gpiod_set_raw_value(struct gpio_desc *desc, bool value)
2045{ 2335{
2046 struct gpio_chip *chip; 2336 struct gpio_chip *chip;
2047 2337
@@ -2137,10 +2427,7 @@ EXPORT_SYMBOL_GPL(gpiod_to_irq);
2137 * @gpio: the GPIO line to lock as used for IRQ 2427 * @gpio: the GPIO line to lock as used for IRQ
2138 * 2428 *
2139 * This is used directly by GPIO drivers that want to lock down 2429 * This is used directly by GPIO drivers that want to lock down
2140 * a certain GPIO line to be used as IRQs, for example in the 2430 * a certain GPIO line to be used for IRQs.
2141 * .to_irq() callback of their gpio_chip, or in the .irq_enable()
2142 * of its irq_chip implementation if the GPIO is known from that
2143 * code.
2144 */ 2431 */
2145int gpiod_lock_as_irq(struct gpio_desc *desc) 2432int gpiod_lock_as_irq(struct gpio_desc *desc)
2146{ 2433{
@@ -2161,7 +2448,7 @@ EXPORT_SYMBOL_GPL(gpiod_lock_as_irq);
2161 2448
2162int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset) 2449int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset)
2163{ 2450{
2164 return gpiod_lock_as_irq(gpiochip_offset_to_desc(chip, offset)); 2451 return gpiod_lock_as_irq(gpiochip_get_desc(chip, offset));
2165} 2452}
2166EXPORT_SYMBOL_GPL(gpio_lock_as_irq); 2453EXPORT_SYMBOL_GPL(gpio_lock_as_irq);
2167 2454
@@ -2183,7 +2470,7 @@ EXPORT_SYMBOL_GPL(gpiod_unlock_as_irq);
2183 2470
2184void gpio_unlock_as_irq(struct gpio_chip *chip, unsigned int offset) 2471void gpio_unlock_as_irq(struct gpio_chip *chip, unsigned int offset)
2185{ 2472{
2186 return gpiod_unlock_as_irq(gpiochip_offset_to_desc(chip, offset)); 2473 return gpiod_unlock_as_irq(gpiochip_get_desc(chip, offset));
2187} 2474}
2188EXPORT_SYMBOL_GPL(gpio_unlock_as_irq); 2475EXPORT_SYMBOL_GPL(gpio_unlock_as_irq);
2189 2476
@@ -2404,7 +2691,7 @@ static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
2404 return ERR_PTR(-EINVAL); 2691 return ERR_PTR(-EINVAL);
2405 } 2692 }
2406 2693
2407 desc = gpiochip_offset_to_desc(chip, p->chip_hwnum); 2694 desc = gpiochip_get_desc(chip, p->chip_hwnum);
2408 *flags = p->flags; 2695 *flags = p->flags;
2409 2696
2410 return desc; 2697 return desc;
diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h
index 82be586c1f90..cf092941a9fd 100644
--- a/drivers/gpio/gpiolib.h
+++ b/drivers/gpio/gpiolib.h
@@ -43,4 +43,7 @@ acpi_get_gpiod_by_index(struct device *dev, int index,
43} 43}
44#endif 44#endif
45 45
46int gpiochip_request_own_desc(struct gpio_desc *desc, const char *label);
47void gpiochip_free_own_desc(struct gpio_desc *desc);
48
46#endif /* GPIOLIB_H */ 49#endif /* GPIOLIB_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 16:32:36 -0500