8 files changed, 459 insertions, 63 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index fee678f74a19..4fd0f276df5a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -139,6 +139,13 @@ config GPIO_MAX732X
           Board setup code must specify the model to use, and the start
           number for these GPIOs.
 
+config GPIO_MAX732X_IRQ
+        bool "Interrupt controller support for MAX732x"
+        depends on GPIO_MAX732X=y && GENERIC_HARDIRQS
+        help
+          Say yes here to enable the max732x to be used as an interrupt
+          controller. It requires the driver to be built in the kernel.
+
 config GPIO_PCA953X
         tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports"
         depends on I2C
@@ -264,10 +271,10 @@ config GPIO_BT8XX
           If unsure, say N.
 
 config GPIO_LANGWELL
-        bool "Intel Moorestown Platform Langwell GPIO support"
+        bool "Intel Langwell/Penwell GPIO support"
         depends on PCI
         help
-          Say Y here to support Intel Moorestown platform GPIO.
+          Say Y here to support Intel Langwell/Penwell GPIO.
 
 config GPIO_TIMBERDALE
         bool "Support for timberdale GPIO IP"
diff --git a/drivers/gpio/cs5535-gpio.c b/drivers/gpio/cs5535-gpio.c
index 0c3c498f2260..f73a1555e49d 100644
--- a/drivers/gpio/cs5535-gpio.c
+++ b/drivers/gpio/cs5535-gpio.c
@@ -197,7 +197,7 @@ static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
         return 0;
 }
 
-static char *cs5535_gpio_names[] = {
+static const char * const cs5535_gpio_names[] = {
         "GPIO0", "GPIO1", "GPIO2", "GPIO3",
         "GPIO4", "GPIO5", "GPIO6", "GPIO7",
         "GPIO8", "GPIO9", "GPIO10", "GPIO11",
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index cae1b8c5b08c..3ca36542e338 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -722,7 +722,7 @@ int gpio_export(unsigned gpio, bool direction_may_change)
         unsigned long           flags;
         struct gpio_desc        *desc;
         int                     status = -EINVAL;
-        char                    *ioname = NULL;
+        const char              *ioname = NULL;
 
         /* can't export until sysfs is available ... */
         if (!gpio_class.p) {
@@ -753,7 +753,7 @@ int gpio_export(unsigned gpio, bool direction_may_change)
                 struct device   *dev;
 
                 dev = device_create(&gpio_class, desc->chip->dev, MKDEV(0, 0),
-                                desc, ioname ? ioname : "gpio%d", gpio);
+                                desc, ioname ? ioname : "gpio%u", gpio);
                 if (!IS_ERR(dev)) {
                         status = sysfs_create_group(&dev->kobj,
                                                 &gpio_attr_group);
@@ -1106,7 +1106,7 @@ unlock:
 fail:
         /* failures here can mean systems won't boot... */
         if (status)
-                pr_err("gpiochip_add: gpios %d..%d (%s) not registered\n",
+                pr_err("gpiochip_add: gpios %d..%d (%s) failed to register\n",
                         chip->base, chip->base + chip->ngpio - 1,
                         chip->label ? : "generic");
         return status;
@@ -1447,6 +1447,49 @@ fail:
 }
 EXPORT_SYMBOL_GPL(gpio_direction_output);
 
+/**
+ * gpio_set_debounce - sets @debounce time for a @gpio
+ * @gpio: the gpio to set debounce time
+ * @debounce: debounce time is microseconds
+ */
+int gpio_set_debounce(unsigned gpio, unsigned debounce)
+{
+        unsigned long           flags;
+        struct gpio_chip        *chip;
+        struct gpio_desc        *desc = &gpio_desc[gpio];
+        int                     status = -EINVAL;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        if (!gpio_is_valid(gpio))
+                goto fail;
+        chip = desc->chip;
+        if (!chip || !chip->set || !chip->set_debounce)
+                goto fail;
+        gpio -= chip->base;
+        if (gpio >= chip->ngpio)
+                goto fail;
+        status = gpio_ensure_requested(desc, gpio);
+        if (status < 0)
+                goto fail;
+
+        /* now we know the gpio is valid and chip won't vanish */
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+
+        might_sleep_if(extra_checks && chip->can_sleep);
+
+        return chip->set_debounce(chip, gpio, debounce);
+
+fail:
+        spin_unlock_irqrestore(&gpio_lock, flags);
+        if (status)
+                pr_debug("%s: gpio-%d status %d\n",
+                        __func__, gpio, status);
+
+        return status;
+}
+EXPORT_SYMBOL_GPL(gpio_set_debounce);
 
 /* I/O calls are only valid after configuration completed; the relevant
  * "is this a valid GPIO" error checks should already have been done.
diff --git a/drivers/gpio/it8761e_gpio.c b/drivers/gpio/it8761e_gpio.c
index 41a9388f2fde..48fc43c4bdd1 100644
--- a/drivers/gpio/it8761e_gpio.c
+++ b/drivers/gpio/it8761e_gpio.c
@@ -217,7 +217,10 @@ gpiochip_add_err:
 static void __exit it8761e_gpio_exit(void)
 {
         if (gpio_ba) {
-                gpiochip_remove(&it8761e_gpio_chip);
+                int ret = gpiochip_remove(&it8761e_gpio_chip);
+
+                WARN(ret, "%s(): gpiochip_remove() failed, ret=%d\n",
+                                __func__, ret);
 
                 release_region(gpio_ba, GPIO_IOSIZE);
                 gpio_ba = 0;
diff --git a/drivers/gpio/langwell_gpio.c b/drivers/gpio/langwell_gpio.c
index 00c3a14127af..8383a8d7f994 100644
--- a/drivers/gpio/langwell_gpio.c
+++ b/drivers/gpio/langwell_gpio.c
@@ -17,6 +17,7 @@
 
 /* Supports:
  * Moorestown platform Langwell chip.
+ * Medfield platform Penwell chip.
  */
 
 #include <linux/module.h>
@@ -31,44 +32,65 @@
 #include <linux/gpio.h>
 #include <linux/slab.h>
 
-struct lnw_gpio_register {
-        u32     GPLR[2];
-        u32     GPDR[2];
-        u32     GPSR[2];
-        u32     GPCR[2];
-        u32     GRER[2];
-        u32     GFER[2];
-        u32     GEDR[2];
+/*
+ * Langwell chip has 64 pins and thus there are 2 32bit registers to control
+ * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
+ * registers to control them, so we only define the order here instead of a
+ * structure, to get a bit offset for a pin (use GPDR as an example):
+ *
+ * nreg = ngpio / 32;
+ * reg = offset / 32;
+ * bit = offset % 32;
+ * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
+ *
+ * so the bit of reg_addr is to control pin offset's GPDR feature
+*/
+
+enum GPIO_REG {
+        GPLR = 0,       /* pin level read-only */
+        GPDR,           /* pin direction */
+        GPSR,           /* pin set */
+        GPCR,           /* pin clear */
+        GRER,           /* rising edge detect */
+        GFER,           /* falling edge detect */
+        GEDR,           /* edge detect result */
 };
 
 struct lnw_gpio {
         struct gpio_chip                chip;
-        struct lnw_gpio_register        *reg_base;
+        void                            *reg_base;
         spinlock_t                      lock;
         unsigned                        irq_base;
 };
 
-static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
+static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
+                        enum GPIO_REG reg_type)
 {
         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
+        unsigned nreg = chip->ngpio / 32;
         u8 reg = offset / 32;
-        void __iomem *gplr;
+        void __iomem *ptr;
+
+        ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
+        return ptr;
+}
+
+static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        void __iomem *gplr = gpio_reg(chip, offset, GPLR);
 
-        gplr = (void __iomem *)(&lnw->reg_base->GPLR[reg]);
         return readl(gplr) & BIT(offset % 32);
 }
 
 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-        struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
-        u8 reg = offset / 32;
         void __iomem *gpsr, *gpcr;
 
         if (value) {
-                gpsr = (void __iomem *)(&lnw->reg_base->GPSR[reg]);
+                gpsr = gpio_reg(chip, offset, GPSR);
                 writel(BIT(offset % 32), gpsr);
         } else {
-                gpcr = (void __iomem *)(&lnw->reg_base->GPCR[reg]);
+                gpcr = gpio_reg(chip, offset, GPCR);
                 writel(BIT(offset % 32), gpcr);
         }
 }
@@ -76,12 +98,10 @@ static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
-        u8 reg = offset / 32;
+        void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
         u32 value;
         unsigned long flags;
-        void __iomem *gpdr;
 
-        gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
         spin_lock_irqsave(&lnw->lock, flags);
         value = readl(gpdr);
         value &= ~BIT(offset % 32);
@@ -94,12 +114,10 @@ static int lnw_gpio_direction_output(struct gpio_chip *chip,
                         unsigned offset, int value)
 {
         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
-        u8 reg = offset / 32;
+        void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
         unsigned long flags;
-        void __iomem *gpdr;
 
         lnw_gpio_set(chip, offset, value);
-        gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
         spin_lock_irqsave(&lnw->lock, flags);
         value = readl(gpdr);
         value |= BIT(offset % 32);;
@@ -118,11 +136,10 @@ static int lnw_irq_type(unsigned irq, unsigned type)
 {
         struct lnw_gpio *lnw = get_irq_chip_data(irq);
         u32 gpio = irq - lnw->irq_base;
-        u8 reg = gpio / 32;
         unsigned long flags;
         u32 value;
-        void __iomem *grer = (void __iomem *)(&lnw->reg_base->GRER[reg]);
-        void __iomem *gfer = (void __iomem *)(&lnw->reg_base->GFER[reg]);
+        void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
+        void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
 
         if (gpio >= lnw->chip.ngpio)
                 return -EINVAL;
@@ -158,8 +175,10 @@ static struct irq_chip lnw_irqchip = {
         .set_type       = lnw_irq_type,
 };
 
-static struct pci_device_id lnw_gpio_ids[] = {
-        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f) },
+static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = {   /* pin number */
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
         { 0, }
 };
 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
@@ -167,17 +186,17 @@ MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
 {
         struct lnw_gpio *lnw = (struct lnw_gpio *)get_irq_data(irq);
-        u32 reg, gpio;
+        u32 base, gpio;
         void __iomem *gedr;
         u32 gedr_v;
 
         /* check GPIO controller to check which pin triggered the interrupt */
-        for (reg = 0; reg < lnw->chip.ngpio / 32; reg++) {
-                gedr = (void __iomem *)(&lnw->reg_base->GEDR[reg]);
+        for (base = 0; base < lnw->chip.ngpio; base += 32) {
+                gedr = gpio_reg(&lnw->chip, base, GEDR);
                 gedr_v = readl(gedr);
                 if (!gedr_v)
                         continue;
-                for (gpio = reg*32; gpio < reg*32+32; gpio++)
+                for (gpio = base; gpio < base + 32; gpio++)
                         if (gedr_v & BIT(gpio % 32)) {
                                 pr_debug("pin %d triggered\n", gpio);
                                 generic_handle_irq(lnw->irq_base + gpio);
@@ -245,7 +264,7 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
         lnw->chip.set = lnw_gpio_set;
         lnw->chip.to_irq = lnw_gpio_to_irq;
         lnw->chip.base = gpio_base;
-        lnw->chip.ngpio = 64;
+        lnw->chip.ngpio = id->driver_data;
         lnw->chip.can_sleep = 0;
         pci_set_drvdata(pdev, lnw);
         retval = gpiochip_add(&lnw->chip);
diff --git a/drivers/gpio/max732x.c b/drivers/gpio/max732x.c
index f7868243af89..9cad60f9e962 100644
--- a/drivers/gpio/max732x.c
+++ b/drivers/gpio/max732x.c
@@ -17,7 +17,8 @@
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/gpio.h>
-
+#include <linux/interrupt.h>
+#include <linux/irq.h>
 #include <linux/i2c.h>
 #include <linux/i2c/max732x.h>
 
@@ -31,7 +32,8 @@
  *   - Open Drain I/O
  *
  * designated by 'O', 'I' and 'P' individually according to MAXIM's
- * datasheets.
+ * datasheets. 'I' and 'P' ports are interrupt capables, some with
+ * a dedicated interrupt mask.
  *
  * There are two groups of I/O ports, each group usually includes
  * up to 8 I/O ports, and is accessed by a specific I2C address:
@@ -44,7 +46,8 @@
  *
  * Within each group of ports, there are five known combinations of
  * I/O ports: 4I4O, 4P4O, 8I, 8P, 8O, see the definitions below for
- * the detailed organization of these ports.
+ * the detailed organization of these ports. Only Goup A is interrupt
+ * capable.
  *
  * GPIO numbers start from 'gpio_base + 0' to 'gpio_base + 8/16',
  * and GPIOs from GROUP_A are numbered before those from GROUP_B
@@ -68,16 +71,47 @@
 #define GROUP_A(x)      ((x) & 0xffff)  /* I2C Addr: 0b'110xxxx */
 #define GROUP_B(x)      ((x) << 16)     /* I2C Addr: 0b'101xxxx */
 
+#define INT_NONE        0x0     /* No interrupt capability */
+#define INT_NO_MASK     0x1     /* Has interrupts, no mask */
+#define INT_INDEP_MASK  0x2     /* Has interrupts, independent mask */
+#define INT_MERGED_MASK 0x3     /* Has interrupts, merged mask */
+
+#define INT_CAPS(x)     (((uint64_t)(x)) << 32)
+
+enum {
+        MAX7319,
+        MAX7320,
+        MAX7321,
+        MAX7322,
+        MAX7323,
+        MAX7324,
+        MAX7325,
+        MAX7326,
+        MAX7327,
+};
+
+static uint64_t max732x_features[] = {
+        [MAX7319] = GROUP_A(IO_8I) | INT_CAPS(INT_MERGED_MASK),
+        [MAX7320] = GROUP_B(IO_8O),
+        [MAX7321] = GROUP_A(IO_8P) | INT_CAPS(INT_NO_MASK),
+        [MAX7322] = GROUP_A(IO_4I4O) | INT_CAPS(INT_MERGED_MASK),
+        [MAX7323] = GROUP_A(IO_4P4O) | INT_CAPS(INT_INDEP_MASK),
+        [MAX7324] = GROUP_A(IO_8I) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK),
+        [MAX7325] = GROUP_A(IO_8P) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK),
+        [MAX7326] = GROUP_A(IO_4I4O) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK),
+        [MAX7327] = GROUP_A(IO_4P4O) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK),
+};
+
 static const struct i2c_device_id max732x_id[] = {
-        { "max7319", GROUP_A(IO_8I) },
-        { "max7320", GROUP_B(IO_8O) },
-        { "max7321", GROUP_A(IO_8P) },
-        { "max7322", GROUP_A(IO_4I4O) },
-        { "max7323", GROUP_A(IO_4P4O) },
-        { "max7324", GROUP_A(IO_8I) | GROUP_B(IO_8O) },
-        { "max7325", GROUP_A(IO_8P) | GROUP_B(IO_8O) },
-        { "max7326", GROUP_A(IO_4I4O) | GROUP_B(IO_8O) },
-        { "max7327", GROUP_A(IO_4P4O) | GROUP_B(IO_8O) },
+        { "max7319", MAX7319 },
+        { "max7320", MAX7320 },
+        { "max7321", MAX7321 },
+        { "max7322", MAX7322 },
+        { "max7323", MAX7323 },
+        { "max7324", MAX7324 },
+        { "max7325", MAX7325 },
+        { "max7326", MAX7326 },
+        { "max7327", MAX7327 },
         { },
 };
 MODULE_DEVICE_TABLE(i2c, max732x_id);
@@ -96,9 +130,19 @@ struct max732x_chip {
 
         struct mutex    lock;
         uint8_t         reg_out[2];
+
+#ifdef CONFIG_GPIO_MAX732X_IRQ
+        struct mutex    irq_lock;
+        int             irq_base;
+        uint8_t         irq_mask;
+        uint8_t         irq_mask_cur;
+        uint8_t         irq_trig_raise;
+        uint8_t         irq_trig_fall;
+        uint8_t         irq_features;
+#endif
 };
 
-static int max732x_write(struct max732x_chip *chip, int group_a, uint8_t val)
+static int max732x_writeb(struct max732x_chip *chip, int group_a, uint8_t val)
 {
         struct i2c_client *client;
         int ret;
@@ -113,7 +157,7 @@ static int max732x_write(struct max732x_chip *chip, int group_a, uint8_t val)
         return 0;
 }
 
-static int max732x_read(struct max732x_chip *chip, int group_a, uint8_t *val)
+static int max732x_readb(struct max732x_chip *chip, int group_a, uint8_t *val)
 {
         struct i2c_client *client;
         int ret;
@@ -142,7 +186,7 @@ static int max732x_gpio_get_value(struct gpio_chip *gc, unsigned off)
 
         chip = container_of(gc, struct max732x_chip, gpio_chip);
 
-        ret = max732x_read(chip, is_group_a(chip, off), &reg_val);
+        ret = max732x_readb(chip, is_group_a(chip, off), &reg_val);
         if (ret < 0)
                 return 0;
 
@@ -162,7 +206,7 @@ static void max732x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
         reg_out = (off > 7) ? chip->reg_out[1] : chip->reg_out[0];
         reg_out = (val) ? reg_out | mask : reg_out & ~mask;
 
-        ret = max732x_write(chip, is_group_a(chip, off), reg_out);
+        ret = max732x_writeb(chip, is_group_a(chip, off), reg_out);
         if (ret < 0)
                 goto out;
 
@@ -188,6 +232,13 @@ static int max732x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
                 return -EACCES;
         }
 
+        /*
+         * Open-drain pins must be set to high impedance (which is
+         * equivalent to output-high) to be turned into an input.
+         */
+        if ((mask & chip->dir_output))
+                max732x_gpio_set_value(gc, off, 1);
+
         return 0;
 }
 
@@ -209,12 +260,278 @@ static int max732x_gpio_direction_output(struct gpio_chip *gc,
         return 0;
 }
 
+#ifdef CONFIG_GPIO_MAX732X_IRQ
+static int max732x_writew(struct max732x_chip *chip, uint16_t val)
+{
+        int ret;
+
+        val = cpu_to_le16(val);
+
+        ret = i2c_master_send(chip->client_group_a, (char *)&val, 2);
+        if (ret < 0) {
+                dev_err(&chip->client_group_a->dev, "failed writing\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static int max732x_readw(struct max732x_chip *chip, uint16_t *val)
+{
+        int ret;
+
+        ret = i2c_master_recv(chip->client_group_a, (char *)val, 2);
+        if (ret < 0) {
+                dev_err(&chip->client_group_a->dev, "failed reading\n");
+                return ret;
+        }
+
+        *val = le16_to_cpu(*val);
+        return 0;
+}
+
+static void max732x_irq_update_mask(struct max732x_chip *chip)
+{
+        uint16_t msg;
+
+        if (chip->irq_mask == chip->irq_mask_cur)
+                return;
+
+        chip->irq_mask = chip->irq_mask_cur;
+
+        if (chip->irq_features == INT_NO_MASK)
+                return;
+
+        mutex_lock(&chip->lock);
+
+        switch (chip->irq_features) {
+        case INT_INDEP_MASK:
+                msg = (chip->irq_mask << 8) | chip->reg_out[0];
+                max732x_writew(chip, msg);
+                break;
+
+        case INT_MERGED_MASK:
+                msg = chip->irq_mask | chip->reg_out[0];
+                max732x_writeb(chip, 1, (uint8_t)msg);
+                break;
+        }
+
+        mutex_unlock(&chip->lock);
+}
+
+static int max732x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
+{
+        struct max732x_chip *chip;
+
+        chip = container_of(gc, struct max732x_chip, gpio_chip);
+        return chip->irq_base + off;
+}
+
+static void max732x_irq_mask(unsigned int irq)
+{
+        struct max732x_chip *chip = get_irq_chip_data(irq);
+
+        chip->irq_mask_cur &= ~(1 << (irq - chip->irq_base));
+}
+
+static void max732x_irq_unmask(unsigned int irq)
+{
+        struct max732x_chip *chip = get_irq_chip_data(irq);
+
+        chip->irq_mask_cur |= 1 << (irq - chip->irq_base);
+}
+
+static void max732x_irq_bus_lock(unsigned int irq)
+{
+        struct max732x_chip *chip = get_irq_chip_data(irq);
+
+        mutex_lock(&chip->irq_lock);
+        chip->irq_mask_cur = chip->irq_mask;
+}
+
+static void max732x_irq_bus_sync_unlock(unsigned int irq)
+{
+        struct max732x_chip *chip = get_irq_chip_data(irq);
+
+        max732x_irq_update_mask(chip);
+        mutex_unlock(&chip->irq_lock);
+}
+
+static int max732x_irq_set_type(unsigned int irq, unsigned int type)
+{
+        struct max732x_chip *chip = get_irq_chip_data(irq);
+        uint16_t off = irq - chip->irq_base;
+        uint16_t mask = 1 << off;
+
+        if (!(mask & chip->dir_input)) {
+                dev_dbg(&chip->client->dev, "%s port %d is output only\n",
+                        chip->client->name, off);
+                return -EACCES;
+        }
+
+        if (!(type & IRQ_TYPE_EDGE_BOTH)) {
+                dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
+                        irq, type);
+                return -EINVAL;
+        }
+
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                chip->irq_trig_fall |= mask;
+        else
+                chip->irq_trig_fall &= ~mask;
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                chip->irq_trig_raise |= mask;
+        else
+                chip->irq_trig_raise &= ~mask;
+
+        return max732x_gpio_direction_input(&chip->gpio_chip, off);
+}
+
+static struct irq_chip max732x_irq_chip = {
+        .name                   = "max732x",
+        .mask                   = max732x_irq_mask,
+        .unmask                 = max732x_irq_unmask,
+        .bus_lock               = max732x_irq_bus_lock,
+        .bus_sync_unlock        = max732x_irq_bus_sync_unlock,
+        .set_type               = max732x_irq_set_type,
+};
+
+static uint8_t max732x_irq_pending(struct max732x_chip *chip)
+{
+        uint8_t cur_stat;
+        uint8_t old_stat;
+        uint8_t trigger;
+        uint8_t pending;
+        uint16_t status;
+        int ret;
+
+        ret = max732x_readw(chip, &status);
+        if (ret)
+                return 0;
+
+        trigger = status >> 8;
+        trigger &= chip->irq_mask;
+
+        if (!trigger)
+                return 0;
+
+        cur_stat = status & 0xFF;
+        cur_stat &= chip->irq_mask;
+
+        old_stat = cur_stat ^ trigger;
+
+        pending = (old_stat & chip->irq_trig_fall) |
+                  (cur_stat & chip->irq_trig_raise);
+        pending &= trigger;
+
+        return pending;
+}
+
+static irqreturn_t max732x_irq_handler(int irq, void *devid)
+{
+        struct max732x_chip *chip = devid;
+        uint8_t pending;
+        uint8_t level;
+
+        pending = max732x_irq_pending(chip);
+
+        if (!pending)
+                return IRQ_HANDLED;
+
+        do {
+                level = __ffs(pending);
+                handle_nested_irq(level + chip->irq_base);
+
+                pending &= ~(1 << level);
+        } while (pending);
+
+        return IRQ_HANDLED;
+}
+
+static int max732x_irq_setup(struct max732x_chip *chip,
+                             const struct i2c_device_id *id)
+{
+        struct i2c_client *client = chip->client;
+        struct max732x_platform_data *pdata = client->dev.platform_data;
+        int has_irq = max732x_features[id->driver_data] >> 32;
+        int ret;
+
+        if (pdata->irq_base && has_irq != INT_NONE) {
+                int lvl;
+
+                chip->irq_base = pdata->irq_base;
+                chip->irq_features = has_irq;
+                mutex_init(&chip->irq_lock);
+
+                for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) {
+                        int irq = lvl + chip->irq_base;
+
+                        if (!(chip->dir_input & (1 << lvl)))
+                                continue;
+
+                        set_irq_chip_data(irq, chip);
+                        set_irq_chip_and_handler(irq, &max732x_irq_chip,
+                                                 handle_edge_irq);
+                        set_irq_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+                        set_irq_flags(irq, IRQF_VALID);
+#else
+                        set_irq_noprobe(irq);
+#endif
+                }
+
+                ret = request_threaded_irq(client->irq,
+                                           NULL,
+                                           max732x_irq_handler,
+                                           IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+                                           dev_name(&client->dev), chip);
+                if (ret) {
+                        dev_err(&client->dev, "failed to request irq %d\n",
+                                client->irq);
+                        goto out_failed;
+                }
+
+                chip->gpio_chip.to_irq = max732x_gpio_to_irq;
+        }
+
+        return 0;
+
+out_failed:
+        chip->irq_base = 0;
+        return ret;
+}
+
+static void max732x_irq_teardown(struct max732x_chip *chip)
+{
+        if (chip->irq_base)
+                free_irq(chip->client->irq, chip);
+}
+#else /* CONFIG_GPIO_MAX732X_IRQ */
+static int max732x_irq_setup(struct max732x_chip *chip,
+                             const struct i2c_device_id *id)
+{
+        struct i2c_client *client = chip->client;
+        struct max732x_platform_data *pdata = client->dev.platform_data;
+        int has_irq = max732x_features[id->driver_data] >> 32;
+
+        if (pdata->irq_base && has_irq != INT_NONE)
+                dev_warn(&client->dev, "interrupt support not compiled in\n");
+
+        return 0;
+}
+
+static void max732x_irq_teardown(struct max732x_chip *chip)
+{
+}
+#endif
+
 static int __devinit max732x_setup_gpio(struct max732x_chip *chip,
                                         const struct i2c_device_id *id,
                                         unsigned gpio_start)
 {
         struct gpio_chip *gc = &chip->gpio_chip;
-        uint32_t id_data = id->driver_data;
+        uint32_t id_data = (uint32_t)max732x_features[id->driver_data];
         int i, port = 0;
 
         for (i = 0; i < 16; i++, id_data >>= 2) {
@@ -285,14 +602,14 @@ static int __devinit max732x_probe(struct i2c_client *client,
         switch (client->addr & 0x70) {
         case 0x60:
                 chip->client_group_a = client;
-                if (nr_port > 7) {
+                if (nr_port > 8) {
                         c = i2c_new_dummy(client->adapter, addr_b);
                         chip->client_group_b = chip->client_dummy = c;
                 }
                 break;
         case 0x50:
                 chip->client_group_b = client;
-                if (nr_port > 7) {
+                if (nr_port > 8) {
                         c = i2c_new_dummy(client->adapter, addr_a);
                         chip->client_group_a = chip->client_dummy = c;
                 }
@@ -306,9 +623,13 @@ static int __devinit max732x_probe(struct i2c_client *client,
 
         mutex_init(&chip->lock);
 
-        max732x_read(chip, is_group_a(chip, 0), &chip->reg_out[0]);
-        if (nr_port > 7)
-                max732x_read(chip, is_group_a(chip, 8), &chip->reg_out[1]);
+        max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]);
+        if (nr_port > 8)
+                max732x_readb(chip, is_group_a(chip, 8), &chip->reg_out[1]);
+
+        ret = max732x_irq_setup(chip, id);
+        if (ret)
+                goto out_failed;
 
         ret = gpiochip_add(&chip->gpio_chip);
         if (ret)
@@ -325,6 +646,7 @@ static int __devinit max732x_probe(struct i2c_client *client,
         return 0;
 
 out_failed:
+        max732x_irq_teardown(chip);
         kfree(chip);
         return ret;
 }
@@ -352,6 +674,8 @@ static int __devexit max732x_remove(struct i2c_client *client)
                 return ret;
         }
 
+        max732x_irq_teardown(chip);
+
         /* unregister any dummy i2c_client */
         if (chip->client_dummy)
                 i2c_unregister_device(chip->client_dummy);
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index f156ab3bb6ed..a2b12aa1f2b9 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -73,7 +73,7 @@ struct pca953x_chip {
         struct i2c_client *client;
         struct pca953x_platform_data *dyn_pdata;
         struct gpio_chip gpio_chip;
-        char **names;
+        const char *const *names;
 };
 
 static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val)
diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index 105701a1f05b..ee568c8fcbd0 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -164,7 +164,7 @@ static int pl061_irq_type(unsigned irq, unsigned trigger)
         unsigned long flags;
         u8 gpiois, gpioibe, gpioiev;
 
-        if (offset < 0 || offset > PL061_GPIO_NR)
+        if (offset < 0 || offset >= PL061_GPIO_NR)
                 return -EINVAL;
 
         spin_lock_irqsave(&chip->irq_lock, flags);