1 files changed, 112 insertions, 32 deletions

diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 9ae7aa8ca48a..792a05ad4649 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -1,7 +1,7 @@
 /*
- * Xilinx gpio driver
+ * Xilinx gpio driver for xps/axi_gpio IP.
  *
- * Copyright 2008 Xilinx, Inc.
+ * Copyright 2008 - 2013 Xilinx, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2
@@ -12,6 +12,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/bitops.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/module.h>
@@ -26,11 +27,31 @@
 #define XGPIO_DATA_OFFSET   (0x0)       /* Data register  */
 #define XGPIO_TRI_OFFSET    (0x4)       /* I/O direction register  */
 
+#define XGPIO_CHANNEL_OFFSET    0x8
+
+/* Read/Write access to the GPIO registers */
+#ifdef CONFIG_ARCH_ZYNQ
+# define xgpio_readreg(offset)          readl(offset)
+# define xgpio_writereg(offset, val)    writel(val, offset)
+#else
+# define xgpio_readreg(offset)          __raw_readl(offset)
+# define xgpio_writereg(offset, val)    __raw_writel(val, offset)
+#endif
+
+/**
+ * struct xgpio_instance - Stores information about GPIO device
+ * struct of_mm_gpio_chip mmchip: OF GPIO chip for memory mapped banks
+ * gpio_state: GPIO state shadow register
+ * gpio_dir: GPIO direction shadow register
+ * offset: GPIO channel offset
+ * gpio_lock: Lock used for synchronization
+ */
 struct xgpio_instance {
         struct of_mm_gpio_chip mmchip;
-        u32 gpio_state;         /* GPIO state shadow register */
-        u32 gpio_dir;           /* GPIO direction shadow register */
-        spinlock_t gpio_lock;   /* Lock used for synchronization */
+        u32 gpio_state;
+        u32 gpio_dir;
+        u32 offset;
+        spinlock_t gpio_lock;
 };
 
 /**
@@ -44,8 +65,12 @@ struct xgpio_instance {
 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
 {
         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct xgpio_instance *chip =
+            container_of(mm_gc, struct xgpio_instance, mmchip);
 
-        return (in_be32(mm_gc->regs + XGPIO_DATA_OFFSET) >> gpio) & 1;
+        void __iomem *regs = mm_gc->regs + chip->offset;
+
+        return !!(xgpio_readreg(regs + XGPIO_DATA_OFFSET) & BIT(gpio));
 }
 
 /**
@@ -63,15 +88,18 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
         struct xgpio_instance *chip =
             container_of(mm_gc, struct xgpio_instance, mmchip);
+        void __iomem *regs = mm_gc->regs;
 
         spin_lock_irqsave(&chip->gpio_lock, flags);
 
         /* Write to GPIO signal and set its direction to output */
         if (val)
-                chip->gpio_state |= 1 << gpio;
+                chip->gpio_state |= BIT(gpio);
         else
-                chip->gpio_state &= ~(1 << gpio);
-        out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state);
+                chip->gpio_state &= ~BIT(gpio);
+
+        xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
+                                                         chip->gpio_state);
 
         spin_unlock_irqrestore(&chip->gpio_lock, flags);
 }
@@ -91,12 +119,13 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
         struct xgpio_instance *chip =
             container_of(mm_gc, struct xgpio_instance, mmchip);
+        void __iomem *regs = mm_gc->regs;
 
         spin_lock_irqsave(&chip->gpio_lock, flags);
 
         /* Set the GPIO bit in shadow register and set direction as input */
-        chip->gpio_dir |= (1 << gpio);
-        out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir);
+        chip->gpio_dir |= BIT(gpio);
+        xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir);
 
         spin_unlock_irqrestore(&chip->gpio_lock, flags);
 
@@ -119,19 +148,21 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
         struct xgpio_instance *chip =
             container_of(mm_gc, struct xgpio_instance, mmchip);
+        void __iomem *regs = mm_gc->regs;
 
         spin_lock_irqsave(&chip->gpio_lock, flags);
 
         /* Write state of GPIO signal */
         if (val)
-                chip->gpio_state |= 1 << gpio;
+                chip->gpio_state |= BIT(gpio);
         else
-                chip->gpio_state &= ~(1 << gpio);
-        out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state);
+                chip->gpio_state &= ~BIT(gpio);
+        xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
+                       chip->gpio_state);
 
         /* Clear the GPIO bit in shadow register and set direction as output */
-        chip->gpio_dir &= (~(1 << gpio));
-        out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir);
+        chip->gpio_dir &= ~BIT(gpio);
+        xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir);
 
         spin_unlock_irqrestore(&chip->gpio_lock, flags);
 
@@ -147,8 +178,10 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
         struct xgpio_instance *chip =
             container_of(mm_gc, struct xgpio_instance, mmchip);
 
-        out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state);
-        out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir);
+        xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_DATA_OFFSET,
+                                                        chip->gpio_state);
+        xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_TRI_OFFSET,
+                                                         chip->gpio_dir);
 }
 
 /**
@@ -170,24 +203,20 @@ static int xgpio_of_probe(struct device_node *np)
                 return -ENOMEM;
 
         /* Update GPIO state shadow register with default value */
-        tree_info = of_get_property(np, "xlnx,dout-default", NULL);
-        if (tree_info)
-                chip->gpio_state = be32_to_cpup(tree_info);
+        of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state);
+
+        /* By default, all pins are inputs */
+        chip->gpio_dir = 0xFFFFFFFF;
 
         /* Update GPIO direction shadow register with default value */
-        chip->gpio_dir = 0xFFFFFFFF; /* By default, all pins are inputs */
-        tree_info = of_get_property(np, "xlnx,tri-default", NULL);
-        if (tree_info)
-                chip->gpio_dir = be32_to_cpup(tree_info);
+        of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir);
+
+        /* By default assume full GPIO controller */
+        chip->mmchip.gc.ngpio = 32;
 
         /* Check device node and parent device node for device width */
-        chip->mmchip.gc.ngpio = 32; /* By default assume full GPIO controller */
-        tree_info = of_get_property(np, "xlnx,gpio-width", NULL);
-        if (!tree_info)
-                tree_info = of_get_property(np->parent,
-                                            "xlnx,gpio-width", NULL);
-        if (tree_info)
-                chip->mmchip.gc.ngpio = be32_to_cpup(tree_info);
+        of_property_read_u32(np, "xlnx,gpio-width",
+                              (u32 *)&chip->mmchip.gc.ngpio);
 
         spin_lock_init(&chip->gpio_lock);
 
@@ -206,6 +235,57 @@ static int xgpio_of_probe(struct device_node *np)
                        np->full_name, status);
                 return status;
         }
+
+        pr_info("XGpio: %s: registered, base is %d\n", np->full_name,
+                                                        chip->mmchip.gc.base);
+
+        tree_info = of_get_property(np, "xlnx,is-dual", NULL);
+        if (tree_info && be32_to_cpup(tree_info)) {
+                chip = kzalloc(sizeof(*chip), GFP_KERNEL);
+                if (!chip)
+                        return -ENOMEM;
+
+                /* Add dual channel offset */
+                chip->offset = XGPIO_CHANNEL_OFFSET;
+
+                /* Update GPIO state shadow register with default value */
+                of_property_read_u32(np, "xlnx,dout-default-2",
+                                     &chip->gpio_state);
+
+                /* By default, all pins are inputs */
+                chip->gpio_dir = 0xFFFFFFFF;
+
+                /* Update GPIO direction shadow register with default value */
+                of_property_read_u32(np, "xlnx,tri-default-2", &chip->gpio_dir);
+
+                /* By default assume full GPIO controller */
+                chip->mmchip.gc.ngpio = 32;
+
+                /* Check device node and parent device node for device width */
+                of_property_read_u32(np, "xlnx,gpio2-width",
+                                     (u32 *)&chip->mmchip.gc.ngpio);
+
+                spin_lock_init(&chip->gpio_lock);
+
+                chip->mmchip.gc.direction_input = xgpio_dir_in;
+                chip->mmchip.gc.direction_output = xgpio_dir_out;
+                chip->mmchip.gc.get = xgpio_get;
+                chip->mmchip.gc.set = xgpio_set;
+
+                chip->mmchip.save_regs = xgpio_save_regs;
+
+                /* Call the OF gpio helper to setup and register the GPIO dev */
+                status = of_mm_gpiochip_add(np, &chip->mmchip);
+                if (status) {
+                        kfree(chip);
+                        pr_err("%s: error in probe function with status %d\n",
+                        np->full_name, status);
+                        return status;
+                }
+                pr_info("XGpio: %s: dual channel registered, base is %d\n",
+                                        np->full_name, chip->mmchip.gc.base);
+        }
+
         return 0;
 }