diff options
Diffstat (limited to 'drivers/gpio/gpio-tz1090.c')
-rw-r--r-- | drivers/gpio/gpio-tz1090.c | 123 |
1 files changed, 48 insertions, 75 deletions
diff --git a/drivers/gpio/gpio-tz1090.c b/drivers/gpio/gpio-tz1090.c index b725a6bef3e1..23e061392411 100644 --- a/drivers/gpio/gpio-tz1090.c +++ b/drivers/gpio/gpio-tz1090.c | |||
@@ -270,30 +270,12 @@ static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data) | |||
270 | return (struct tz1090_gpio_bank *)data->domain->host_data; | 270 | return (struct tz1090_gpio_bank *)data->domain->host_data; |
271 | } | 271 | } |
272 | 272 | ||
273 | static void tz1090_gpio_irq_clear(struct tz1090_gpio_bank *bank, | ||
274 | unsigned int offset) | ||
275 | { | ||
276 | tz1090_gpio_clear_bit(bank, REG_GPIO_IRQ_STS, offset); | ||
277 | } | ||
278 | |||
279 | static void tz1090_gpio_irq_enable(struct tz1090_gpio_bank *bank, | ||
280 | unsigned int offset, bool enable) | ||
281 | { | ||
282 | tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_EN, offset, enable); | ||
283 | } | ||
284 | |||
285 | static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank, | 273 | static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank, |
286 | unsigned int offset, unsigned int polarity) | 274 | unsigned int offset, unsigned int polarity) |
287 | { | 275 | { |
288 | tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity); | 276 | tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity); |
289 | } | 277 | } |
290 | 278 | ||
291 | static int tz1090_gpio_valid_handler(struct irq_desc *desc) | ||
292 | { | ||
293 | return desc->handle_irq == handle_level_irq || | ||
294 | desc->handle_irq == handle_edge_irq; | ||
295 | } | ||
296 | |||
297 | static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank, | 279 | static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank, |
298 | unsigned int offset, unsigned int type) | 280 | unsigned int offset, unsigned int type) |
299 | { | 281 | { |
@@ -320,43 +302,18 @@ static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank, | |||
320 | __global_unlock2(lstat); | 302 | __global_unlock2(lstat); |
321 | } | 303 | } |
322 | 304 | ||
323 | static void gpio_ack_irq(struct irq_data *data) | ||
324 | { | ||
325 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | ||
326 | |||
327 | tz1090_gpio_irq_clear(bank, data->hwirq); | ||
328 | } | ||
329 | |||
330 | static void gpio_mask_irq(struct irq_data *data) | ||
331 | { | ||
332 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | ||
333 | |||
334 | tz1090_gpio_irq_enable(bank, data->hwirq, false); | ||
335 | } | ||
336 | |||
337 | static void gpio_unmask_irq(struct irq_data *data) | ||
338 | { | ||
339 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | ||
340 | |||
341 | tz1090_gpio_irq_enable(bank, data->hwirq, true); | ||
342 | } | ||
343 | |||
344 | static unsigned int gpio_startup_irq(struct irq_data *data) | 305 | static unsigned int gpio_startup_irq(struct irq_data *data) |
345 | { | 306 | { |
346 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | ||
347 | irq_hw_number_t hw = data->hwirq; | ||
348 | struct irq_desc *desc = irq_to_desc(data->irq); | ||
349 | |||
350 | /* | 307 | /* |
351 | * This warning indicates that the type of the irq hasn't been set | 308 | * This warning indicates that the type of the irq hasn't been set |
352 | * before enabling the irq. This would normally be done by passing some | 309 | * before enabling the irq. This would normally be done by passing some |
353 | * trigger flags to request_irq(). | 310 | * trigger flags to request_irq(). |
354 | */ | 311 | */ |
355 | WARN(!tz1090_gpio_valid_handler(desc), | 312 | WARN(irqd_get_trigger_type(data) == IRQ_TYPE_NONE, |
356 | "irq type not set before enabling gpio irq %d", data->irq); | 313 | "irq type not set before enabling gpio irq %d", data->irq); |
357 | 314 | ||
358 | tz1090_gpio_irq_clear(bank, hw); | 315 | irq_gc_ack_clr_bit(data); |
359 | tz1090_gpio_irq_enable(bank, hw, true); | 316 | irq_gc_mask_set_bit(data); |
360 | return 0; | 317 | return 0; |
361 | } | 318 | } |
362 | 319 | ||
@@ -392,10 +349,7 @@ static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type) | |||
392 | } | 349 | } |
393 | 350 | ||
394 | tz1090_gpio_irq_type(bank, data->hwirq, type); | 351 | tz1090_gpio_irq_type(bank, data->hwirq, type); |
395 | if (type == REG_GPIO_IRQ_TYPE_LEVEL) | 352 | irq_setup_alt_chip(data, flow_type); |
396 | __irq_set_handler_locked(data->irq, handle_level_irq); | ||
397 | else | ||
398 | __irq_set_handler_locked(data->irq, handle_edge_irq); | ||
399 | 353 | ||
400 | if (flow_type == IRQ_TYPE_EDGE_BOTH) | 354 | if (flow_type == IRQ_TYPE_EDGE_BOTH) |
401 | tz1090_gpio_irq_next_edge(bank, data->hwirq); | 355 | tz1090_gpio_irq_next_edge(bank, data->hwirq); |
@@ -421,17 +375,6 @@ static int gpio_set_irq_wake(struct irq_data *data, unsigned int on) | |||
421 | #define gpio_set_irq_wake NULL | 375 | #define gpio_set_irq_wake NULL |
422 | #endif | 376 | #endif |
423 | 377 | ||
424 | /* gpio virtual interrupt functions */ | ||
425 | static struct irq_chip gpio_irq_chip = { | ||
426 | .irq_startup = gpio_startup_irq, | ||
427 | .irq_ack = gpio_ack_irq, | ||
428 | .irq_mask = gpio_mask_irq, | ||
429 | .irq_unmask = gpio_unmask_irq, | ||
430 | .irq_set_type = gpio_set_irq_type, | ||
431 | .irq_set_wake = gpio_set_irq_wake, | ||
432 | .flags = IRQCHIP_MASK_ON_SUSPEND, | ||
433 | }; | ||
434 | |||
435 | static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 378 | static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
436 | { | 379 | { |
437 | irq_hw_number_t hw; | 380 | irq_hw_number_t hw; |
@@ -457,28 +400,17 @@ static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
457 | == IRQ_TYPE_EDGE_BOTH) | 400 | == IRQ_TYPE_EDGE_BOTH) |
458 | tz1090_gpio_irq_next_edge(bank, hw); | 401 | tz1090_gpio_irq_next_edge(bank, hw); |
459 | 402 | ||
460 | BUG_ON(!tz1090_gpio_valid_handler(child_desc)); | ||
461 | generic_handle_irq_desc(irq_no, child_desc); | 403 | generic_handle_irq_desc(irq_no, child_desc); |
462 | } | 404 | } |
463 | } | 405 | } |
464 | 406 | ||
465 | static int tz1090_gpio_irq_map(struct irq_domain *d, unsigned int irq, | ||
466 | irq_hw_number_t hw) | ||
467 | { | ||
468 | irq_set_chip(irq, &gpio_irq_chip); | ||
469 | return 0; | ||
470 | } | ||
471 | |||
472 | static const struct irq_domain_ops tz1090_gpio_irq_domain_ops = { | ||
473 | .map = tz1090_gpio_irq_map, | ||
474 | .xlate = irq_domain_xlate_twocell, | ||
475 | }; | ||
476 | |||
477 | static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info) | 407 | static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info) |
478 | { | 408 | { |
479 | struct device_node *np = info->node; | 409 | struct device_node *np = info->node; |
480 | struct device *dev = info->priv->dev; | 410 | struct device *dev = info->priv->dev; |
481 | struct tz1090_gpio_bank *bank; | 411 | struct tz1090_gpio_bank *bank; |
412 | struct irq_chip_generic *gc; | ||
413 | int err; | ||
482 | 414 | ||
483 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | 415 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); |
484 | if (!bank) { | 416 | if (!bank) { |
@@ -533,9 +465,50 @@ static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info) | |||
533 | /* Add a virtual IRQ for each GPIO */ | 465 | /* Add a virtual IRQ for each GPIO */ |
534 | bank->domain = irq_domain_add_linear(np, | 466 | bank->domain = irq_domain_add_linear(np, |
535 | bank->chip.ngpio, | 467 | bank->chip.ngpio, |
536 | &tz1090_gpio_irq_domain_ops, | 468 | &irq_generic_chip_ops, |
537 | bank); | 469 | bank); |
538 | 470 | ||
471 | /* Set up a generic irq chip with 2 chip types (level and edge) */ | ||
472 | err = irq_alloc_domain_generic_chips(bank->domain, bank->chip.ngpio, 2, | ||
473 | bank->label, handle_bad_irq, 0, 0, | ||
474 | IRQ_GC_INIT_NESTED_LOCK); | ||
475 | if (err) { | ||
476 | dev_info(dev, | ||
477 | "irq_alloc_domain_generic_chips failed for bank %u, IRQs disabled\n", | ||
478 | info->index); | ||
479 | irq_domain_remove(bank->domain); | ||
480 | return 0; | ||
481 | } | ||
482 | |||
483 | gc = irq_get_domain_generic_chip(bank->domain, 0); | ||
484 | gc->reg_base = bank->reg; | ||
485 | |||
486 | /* level chip type */ | ||
487 | gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; | ||
488 | gc->chip_types[0].handler = handle_level_irq; | ||
489 | gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS; | ||
490 | gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN; | ||
491 | gc->chip_types[0].chip.irq_startup = gpio_startup_irq, | ||
492 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit, | ||
493 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit, | ||
494 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit, | ||
495 | gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type, | ||
496 | gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake, | ||
497 | gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND, | ||
498 | |||
499 | /* edge chip type */ | ||
500 | gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; | ||
501 | gc->chip_types[1].handler = handle_edge_irq; | ||
502 | gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS; | ||
503 | gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN; | ||
504 | gc->chip_types[1].chip.irq_startup = gpio_startup_irq, | ||
505 | gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit, | ||
506 | gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit, | ||
507 | gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit, | ||
508 | gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type, | ||
509 | gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake, | ||
510 | gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND, | ||
511 | |||
539 | /* Setup chained handler for this GPIO bank */ | 512 | /* Setup chained handler for this GPIO bank */ |
540 | irq_set_handler_data(bank->irq, bank); | 513 | irq_set_handler_data(bank->irq, bank); |
541 | irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler); | 514 | irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler); |