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path: root/drivers/gpio/gpio-s5p64x0.c
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Diffstat (limited to 'drivers/gpio/gpio-s5p64x0.c')
-rw-r--r--drivers/gpio/gpio-s5p64x0.c510
1 files changed, 0 insertions, 510 deletions
diff --git a/drivers/gpio/gpio-s5p64x0.c b/drivers/gpio/gpio-s5p64x0.c
deleted file mode 100644
index 96e816f5cc95..000000000000
--- a/drivers/gpio/gpio-s5p64x0.c
+++ /dev/null
@@ -1,510 +0,0 @@
1/*
2 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * S5P64X0 - GPIOlib support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/irq.h>
14#include <linux/io.h>
15#include <linux/gpio.h>
16
17#include <mach/map.h>
18#include <mach/regs-gpio.h>
19#include <mach/regs-clock.h>
20
21#include <plat/gpio-core.h>
22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h>
24
25/*
26 * S5P6440 GPIO bank summary:
27 *
28 * Bank GPIOs Style SlpCon ExtInt Group
29 * A 6 4Bit Yes 1
30 * B 7 4Bit Yes 1
31 * C 8 4Bit Yes 2
32 * F 2 2Bit Yes 4 [1]
33 * G 7 4Bit Yes 5
34 * H 10 4Bit[2] Yes 6
35 * I 16 2Bit Yes None
36 * J 12 2Bit Yes None
37 * N 16 2Bit No IRQ_EINT
38 * P 8 2Bit Yes 8
39 * R 15 4Bit[2] Yes 8
40 *
41 * S5P6450 GPIO bank summary:
42 *
43 * Bank GPIOs Style SlpCon ExtInt Group
44 * A 6 4Bit Yes 1
45 * B 7 4Bit Yes 1
46 * C 8 4Bit Yes 2
47 * D 8 4Bit Yes None
48 * F 2 2Bit Yes None
49 * G 14 4Bit[2] Yes 5
50 * H 10 4Bit[2] Yes 6
51 * I 16 2Bit Yes None
52 * J 12 2Bit Yes None
53 * K 5 4Bit Yes None
54 * N 16 2Bit No IRQ_EINT
55 * P 11 2Bit Yes 8
56 * Q 14 2Bit Yes None
57 * R 15 4Bit[2] Yes None
58 * S 8 2Bit Yes None
59 *
60 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
61 * [2] BANK has two control registers, GPxCON0 and GPxCON1
62 */
63
64static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
65 unsigned int offset)
66{
67 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
68 void __iomem *base = ourchip->base;
69 void __iomem *regcon = base;
70 unsigned long con;
71 unsigned long flags;
72
73 switch (offset) {
74 case 6:
75 offset += 1;
76 case 0:
77 case 1:
78 case 2:
79 case 3:
80 case 4:
81 case 5:
82 regcon -= 4;
83 break;
84 default:
85 offset -= 7;
86 break;
87 }
88
89 s3c_gpio_lock(ourchip, flags);
90
91 con = __raw_readl(regcon);
92 con &= ~(0xf << con_4bit_shift(offset));
93 __raw_writel(con, regcon);
94
95 s3c_gpio_unlock(ourchip, flags);
96
97 return 0;
98}
99
100static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
101 unsigned int offset, int value)
102{
103 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
104 void __iomem *base = ourchip->base;
105 void __iomem *regcon = base;
106 unsigned long con;
107 unsigned long dat;
108 unsigned long flags;
109 unsigned con_offset = offset;
110
111 switch (con_offset) {
112 case 6:
113 con_offset += 1;
114 case 0:
115 case 1:
116 case 2:
117 case 3:
118 case 4:
119 case 5:
120 regcon -= 4;
121 break;
122 default:
123 con_offset -= 7;
124 break;
125 }
126
127 s3c_gpio_lock(ourchip, flags);
128
129 con = __raw_readl(regcon);
130 con &= ~(0xf << con_4bit_shift(con_offset));
131 con |= 0x1 << con_4bit_shift(con_offset);
132
133 dat = __raw_readl(base + GPIODAT_OFF);
134 if (value)
135 dat |= 1 << offset;
136 else
137 dat &= ~(1 << offset);
138
139 __raw_writel(con, regcon);
140 __raw_writel(dat, base + GPIODAT_OFF);
141
142 s3c_gpio_unlock(ourchip, flags);
143
144 return 0;
145}
146
147int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
148 unsigned int off, unsigned int cfg)
149{
150 void __iomem *reg = chip->base;
151 unsigned int shift;
152 u32 con;
153
154 switch (off) {
155 case 0:
156 case 1:
157 case 2:
158 case 3:
159 case 4:
160 case 5:
161 shift = (off & 7) * 4;
162 reg -= 4;
163 break;
164 case 6:
165 shift = ((off + 1) & 7) * 4;
166 reg -= 4;
167 default:
168 shift = ((off + 1) & 7) * 4;
169 break;
170 }
171
172 if (s3c_gpio_is_cfg_special(cfg)) {
173 cfg &= 0xf;
174 cfg <<= shift;
175 }
176
177 con = __raw_readl(reg);
178 con &= ~(0xf << shift);
179 con |= cfg;
180 __raw_writel(con, reg);
181
182 return 0;
183}
184
185static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
186 {
187 .cfg_eint = 0,
188 }, {
189 .cfg_eint = 7,
190 }, {
191 .cfg_eint = 3,
192 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
193 }, {
194 .cfg_eint = 0,
195 .set_config = s3c_gpio_setcfg_s3c24xx,
196 .get_config = s3c_gpio_getcfg_s3c24xx,
197 }, {
198 .cfg_eint = 2,
199 .set_config = s3c_gpio_setcfg_s3c24xx,
200 .get_config = s3c_gpio_getcfg_s3c24xx,
201 }, {
202 .cfg_eint = 3,
203 .set_config = s3c_gpio_setcfg_s3c24xx,
204 .get_config = s3c_gpio_getcfg_s3c24xx,
205 },
206};
207
208static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
209 {
210 .base = S5P64X0_GPA_BASE,
211 .config = &s5p64x0_gpio_cfgs[1],
212 .chip = {
213 .base = S5P6440_GPA(0),
214 .ngpio = S5P6440_GPIO_A_NR,
215 .label = "GPA",
216 },
217 }, {
218 .base = S5P64X0_GPB_BASE,
219 .config = &s5p64x0_gpio_cfgs[1],
220 .chip = {
221 .base = S5P6440_GPB(0),
222 .ngpio = S5P6440_GPIO_B_NR,
223 .label = "GPB",
224 },
225 }, {
226 .base = S5P64X0_GPC_BASE,
227 .config = &s5p64x0_gpio_cfgs[1],
228 .chip = {
229 .base = S5P6440_GPC(0),
230 .ngpio = S5P6440_GPIO_C_NR,
231 .label = "GPC",
232 },
233 }, {
234 .base = S5P64X0_GPG_BASE,
235 .config = &s5p64x0_gpio_cfgs[1],
236 .chip = {
237 .base = S5P6440_GPG(0),
238 .ngpio = S5P6440_GPIO_G_NR,
239 .label = "GPG",
240 },
241 },
242};
243
244static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
245 {
246 .base = S5P64X0_GPH_BASE + 0x4,
247 .config = &s5p64x0_gpio_cfgs[1],
248 .chip = {
249 .base = S5P6440_GPH(0),
250 .ngpio = S5P6440_GPIO_H_NR,
251 .label = "GPH",
252 },
253 },
254};
255
256static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
257 {
258 .base = S5P64X0_GPR_BASE + 0x4,
259 .config = &s5p64x0_gpio_cfgs[2],
260 .chip = {
261 .base = S5P6440_GPR(0),
262 .ngpio = S5P6440_GPIO_R_NR,
263 .label = "GPR",
264 },
265 },
266};
267
268static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
269 {
270 .base = S5P64X0_GPF_BASE,
271 .config = &s5p64x0_gpio_cfgs[5],
272 .chip = {
273 .base = S5P6440_GPF(0),
274 .ngpio = S5P6440_GPIO_F_NR,
275 .label = "GPF",
276 },
277 }, {
278 .base = S5P64X0_GPI_BASE,
279 .config = &s5p64x0_gpio_cfgs[3],
280 .chip = {
281 .base = S5P6440_GPI(0),
282 .ngpio = S5P6440_GPIO_I_NR,
283 .label = "GPI",
284 },
285 }, {
286 .base = S5P64X0_GPJ_BASE,
287 .config = &s5p64x0_gpio_cfgs[3],
288 .chip = {
289 .base = S5P6440_GPJ(0),
290 .ngpio = S5P6440_GPIO_J_NR,
291 .label = "GPJ",
292 },
293 }, {
294 .base = S5P64X0_GPN_BASE,
295 .config = &s5p64x0_gpio_cfgs[4],
296 .chip = {
297 .base = S5P6440_GPN(0),
298 .ngpio = S5P6440_GPIO_N_NR,
299 .label = "GPN",
300 },
301 }, {
302 .base = S5P64X0_GPP_BASE,
303 .config = &s5p64x0_gpio_cfgs[5],
304 .chip = {
305 .base = S5P6440_GPP(0),
306 .ngpio = S5P6440_GPIO_P_NR,
307 .label = "GPP",
308 },
309 },
310};
311
312static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
313 {
314 .base = S5P64X0_GPA_BASE,
315 .config = &s5p64x0_gpio_cfgs[1],
316 .chip = {
317 .base = S5P6450_GPA(0),
318 .ngpio = S5P6450_GPIO_A_NR,
319 .label = "GPA",
320 },
321 }, {
322 .base = S5P64X0_GPB_BASE,
323 .config = &s5p64x0_gpio_cfgs[1],
324 .chip = {
325 .base = S5P6450_GPB(0),
326 .ngpio = S5P6450_GPIO_B_NR,
327 .label = "GPB",
328 },
329 }, {
330 .base = S5P64X0_GPC_BASE,
331 .config = &s5p64x0_gpio_cfgs[1],
332 .chip = {
333 .base = S5P6450_GPC(0),
334 .ngpio = S5P6450_GPIO_C_NR,
335 .label = "GPC",
336 },
337 }, {
338 .base = S5P6450_GPD_BASE,
339 .config = &s5p64x0_gpio_cfgs[1],
340 .chip = {
341 .base = S5P6450_GPD(0),
342 .ngpio = S5P6450_GPIO_D_NR,
343 .label = "GPD",
344 },
345 }, {
346 .base = S5P6450_GPK_BASE,
347 .config = &s5p64x0_gpio_cfgs[1],
348 .chip = {
349 .base = S5P6450_GPK(0),
350 .ngpio = S5P6450_GPIO_K_NR,
351 .label = "GPK",
352 },
353 },
354};
355
356static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
357 {
358 .base = S5P64X0_GPG_BASE + 0x4,
359 .config = &s5p64x0_gpio_cfgs[1],
360 .chip = {
361 .base = S5P6450_GPG(0),
362 .ngpio = S5P6450_GPIO_G_NR,
363 .label = "GPG",
364 },
365 }, {
366 .base = S5P64X0_GPH_BASE + 0x4,
367 .config = &s5p64x0_gpio_cfgs[1],
368 .chip = {
369 .base = S5P6450_GPH(0),
370 .ngpio = S5P6450_GPIO_H_NR,
371 .label = "GPH",
372 },
373 },
374};
375
376static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
377 {
378 .base = S5P64X0_GPR_BASE + 0x4,
379 .config = &s5p64x0_gpio_cfgs[2],
380 .chip = {
381 .base = S5P6450_GPR(0),
382 .ngpio = S5P6450_GPIO_R_NR,
383 .label = "GPR",
384 },
385 },
386};
387
388static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
389 {
390 .base = S5P64X0_GPF_BASE,
391 .config = &s5p64x0_gpio_cfgs[5],
392 .chip = {
393 .base = S5P6450_GPF(0),
394 .ngpio = S5P6450_GPIO_F_NR,
395 .label = "GPF",
396 },
397 }, {
398 .base = S5P64X0_GPI_BASE,
399 .config = &s5p64x0_gpio_cfgs[3],
400 .chip = {
401 .base = S5P6450_GPI(0),
402 .ngpio = S5P6450_GPIO_I_NR,
403 .label = "GPI",
404 },
405 }, {
406 .base = S5P64X0_GPJ_BASE,
407 .config = &s5p64x0_gpio_cfgs[3],
408 .chip = {
409 .base = S5P6450_GPJ(0),
410 .ngpio = S5P6450_GPIO_J_NR,
411 .label = "GPJ",
412 },
413 }, {
414 .base = S5P64X0_GPN_BASE,
415 .config = &s5p64x0_gpio_cfgs[4],
416 .chip = {
417 .base = S5P6450_GPN(0),
418 .ngpio = S5P6450_GPIO_N_NR,
419 .label = "GPN",
420 },
421 }, {
422 .base = S5P64X0_GPP_BASE,
423 .config = &s5p64x0_gpio_cfgs[5],
424 .chip = {
425 .base = S5P6450_GPP(0),
426 .ngpio = S5P6450_GPIO_P_NR,
427 .label = "GPP",
428 },
429 }, {
430 .base = S5P6450_GPQ_BASE,
431 .config = &s5p64x0_gpio_cfgs[4],
432 .chip = {
433 .base = S5P6450_GPQ(0),
434 .ngpio = S5P6450_GPIO_Q_NR,
435 .label = "GPQ",
436 },
437 }, {
438 .base = S5P6450_GPS_BASE,
439 .config = &s5p64x0_gpio_cfgs[5],
440 .chip = {
441 .base = S5P6450_GPS(0),
442 .ngpio = S5P6450_GPIO_S_NR,
443 .label = "GPS",
444 },
445 },
446};
447
448void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
449{
450 for (; nr_chips > 0; nr_chips--, chipcfg++) {
451 if (!chipcfg->set_config)
452 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
453 if (!chipcfg->get_config)
454 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
455 if (!chipcfg->set_pull)
456 chipcfg->set_pull = s3c_gpio_setpull_updown;
457 if (!chipcfg->get_pull)
458 chipcfg->get_pull = s3c_gpio_getpull_updown;
459 }
460}
461
462static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
463 int nr_chips)
464{
465 for (; nr_chips > 0; nr_chips--, chip++) {
466 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
467 chip->chip.direction_output =
468 s5p64x0_gpiolib_rbank_4bit2_output;
469 s3c_gpiolib_add(chip);
470 }
471}
472
473static int __init s5p64x0_gpiolib_init(void)
474{
475 unsigned int chipid;
476
477 chipid = __raw_readl(S5P64X0_SYS_ID);
478
479 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
480 ARRAY_SIZE(s5p64x0_gpio_cfgs));
481
482 if ((chipid & 0xff000) == 0x50000) {
483 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
484 ARRAY_SIZE(s5p6450_gpio_2bit));
485
486 samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
487 ARRAY_SIZE(s5p6450_gpio_4bit));
488
489 samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
490 ARRAY_SIZE(s5p6450_gpio_4bit2));
491
492 s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
493 ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
494 } else {
495 samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
496 ARRAY_SIZE(s5p6440_gpio_2bit));
497
498 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
499 ARRAY_SIZE(s5p6440_gpio_4bit));
500
501 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
502 ARRAY_SIZE(s5p6440_gpio_4bit2));
503
504 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
505 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
506 }
507
508 return 0;
509}
510core_initcall(s5p64x0_gpiolib_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 14:13:47 -0500