1 files changed, 246 insertions, 8 deletions
diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c
index a9016f56ed7e..3aa6beec8c1e 100644
--- a/drivers/gpio/gpio-ml-ioh.c
+++ b/drivers/gpio/gpio-ml-ioh.c
@@ -18,6 +18,17 @@
 #include <linux/slab.h>
 #include <linux/pci.h>
 #include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#define IOH_EDGE_FALLING        0
+#define IOH_EDGE_RISING         BIT(0)
+#define IOH_LEVEL_L             BIT(1)
+#define IOH_LEVEL_H             (BIT(0) | BIT(1))
+#define IOH_EDGE_BOTH           BIT(2)
+#define IOH_IM_MASK             (BIT(0) | BIT(1) | BIT(2))
+#define IOH_IRQ_BASE            0
 #define PCI_VENDOR_ID_ROHM             0x10DB
@@ -46,12 +57,22 @@ struct ioh_regs {
 /**
 * struct ioh_gpio_reg_data - The register store data.
+ * @ien_reg     To store contents of interrupt enable register.
+ * @imask_reg:  To store contents of interrupt mask regist
 * @po_reg:     To store contents of PO register.
 * @pm_reg:     To store contents of PM register.
+ * @im0_reg:    To store contents of interrupt mode regist0
+ * @im1_reg:    To store contents of interrupt mode regist1
+ * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
 */
 struct ioh_gpio_reg_data {
+        u32 ien_reg;
+        u32 imask_reg;
        u32 po_reg;
        u32 pm_reg;
+        u32 im0_reg;
+        u32 im1_reg;
+        u32 use_sel_reg;
 };
 /**
@@ -62,7 +83,11 @@ struct ioh_gpio_reg_data {
 * @gpio:                       Data for GPIO infrastructure.
 * @ioh_gpio_reg:               Memory mapped Register data is saved here
 *                              when suspend.
+ * @gpio_use_sel:               Save GPIO_USE_SEL1~4 register for PM
 * @ch:                         Indicate GPIO channel
+ * @irq_base:           Save base of IRQ number for interrupt
+ * @spinlock:           Used for register access protection in
+ *                              interrupt context ioh_irq_type and PM;
 */
 struct ioh_gpio {
        void __iomem *base;
@@ -70,8 +95,11 @@ struct ioh_gpio {
        struct device *dev;
        struct gpio_chip gpio;
        struct ioh_gpio_reg_data ioh_gpio_reg;
+        u32 gpio_use_sel;
        struct mutex lock;
        int ch;
+        int irq_base;
+        spinlock_t spinlock;
 };
 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
@@ -145,8 +173,25 @@ static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 */
 static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
 {
-        chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
+        int i;
-        chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
+        for (i = 0; i < 8; i ++, chip++) {
+                chip->ioh_gpio_reg.po_reg =
+                                        ioread32(&chip->reg->regs[chip->ch].po);
+                chip->ioh_gpio_reg.pm_reg =
+                                        ioread32(&chip->reg->regs[chip->ch].pm);
+                chip->ioh_gpio_reg.ien_reg =
+                                       ioread32(&chip->reg->regs[chip->ch].ien);
+                chip->ioh_gpio_reg.imask_reg =
+                                     ioread32(&chip->reg->regs[chip->ch].imask);
+                chip->ioh_gpio_reg.im0_reg =
+                                      ioread32(&chip->reg->regs[chip->ch].im_0);
+                chip->ioh_gpio_reg.im1_reg =
+                                      ioread32(&chip->reg->regs[chip->ch].im_1);
+                if (i < 4)
+                        chip->ioh_gpio_reg.use_sel_reg =
+                                           ioread32(&chip->reg->ioh_sel_reg[i]);
+        }
 }
 /*
@@ -154,13 +199,34 @@ static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
 */
 static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
 {
-        /* to store contents of PO register */
+        int i;
-        iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
-        /* to store contents of PM register */
+        for (i = 0; i < 8; i ++, chip++) {
-        iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
+                iowrite32(chip->ioh_gpio_reg.po_reg,
+                          &chip->reg->regs[chip->ch].po);
+                iowrite32(chip->ioh_gpio_reg.pm_reg,
+                          &chip->reg->regs[chip->ch].pm);
+                iowrite32(chip->ioh_gpio_reg.ien_reg,
+                          &chip->reg->regs[chip->ch].ien);
+                iowrite32(chip->ioh_gpio_reg.imask_reg,
+                          &chip->reg->regs[chip->ch].imask);
+                iowrite32(chip->ioh_gpio_reg.im0_reg,
+                          &chip->reg->regs[chip->ch].im_0);
+                iowrite32(chip->ioh_gpio_reg.im1_reg,
+                          &chip->reg->regs[chip->ch].im_1);
+                if (i < 4)
+                        iowrite32(chip->ioh_gpio_reg.use_sel_reg,
+                                  &chip->reg->ioh_sel_reg[i]);
+        }
 }
 #endif
+static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
+{
+        struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
+        return chip->irq_base + offset;
+}
 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
 {
        struct gpio_chip *gpio = &chip->gpio;
@@ -175,16 +241,148 @@ static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
        gpio->base = -1;
        gpio->ngpio = num_port;
        gpio->can_sleep = 0;
+        gpio->to_irq = ioh_gpio_to_irq;
+}
+static int ioh_irq_type(struct irq_data *d, unsigned int type)
+{
+        u32 im;
+        u32 *im_reg;
+        u32 ien;
+        u32 im_pos;
+        int ch;
+        unsigned long flags;
+        u32 val;
+        int irq = d->irq;
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct ioh_gpio *chip = gc->private;
+        ch = irq - chip->irq_base;
+        if (irq <= chip->irq_base + 7) {
+                im_reg = &chip->reg->regs[chip->ch].im_0;
+                im_pos = ch;
+        } else {
+                im_reg = &chip->reg->regs[chip->ch].im_1;
+                im_pos = ch - 8;
+        }
+        dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
+                __func__, irq, type, ch, im_pos, type);
+        spin_lock_irqsave(&chip->spinlock, flags);
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                val = IOH_EDGE_RISING;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                val = IOH_EDGE_FALLING;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                val = IOH_EDGE_BOTH;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                val = IOH_LEVEL_H;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                val = IOH_LEVEL_L;
+                break;
+        case IRQ_TYPE_PROBE:
+                goto end;
+        default:
+                dev_warn(chip->dev, "%s: unknown type(%dd)",
+                        __func__, type);
+                goto end;
+        }
+        /* Set interrupt mode */
+        im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
+        iowrite32(im | (val << (im_pos * 4)), im_reg);
+        /* iclr */
+        iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
+        /* IMASKCLR */
+        iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
+        /* Enable interrupt */
+        ien = ioread32(&chip->reg->regs[chip->ch].ien);
+        iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
+end:
+        spin_unlock_irqrestore(&chip->spinlock, flags);
+        return 0;
+}
+static void ioh_irq_unmask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct ioh_gpio *chip = gc->private;
+        iowrite32(1 << (d->irq - chip->irq_base),
+                  &chip->reg->regs[chip->ch].imaskclr);
+}
+static void ioh_irq_mask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct ioh_gpio *chip = gc->private;
+        iowrite32(1 << (d->irq - chip->irq_base),
+                  &chip->reg->regs[chip->ch].imask);
+}
+static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
+{
+        struct ioh_gpio *chip = dev_id;
+        u32 reg_val;
+        int i, j;
+        int ret = IRQ_NONE;
+        for (i = 0; i < 8; i++) {
+                reg_val = ioread32(&chip->reg->regs[i].istatus);
+                for (j = 0; j < num_ports[i]; j++) {
+                        if (reg_val & BIT(j)) {
+                                dev_dbg(chip->dev,
+                                        "%s:[%d]:irq=%d status=0x%x\n",
+                                        __func__, j, irq, reg_val);
+                                iowrite32(BIT(j),
+                                          &chip->reg->regs[chip->ch].iclr);
+                                generic_handle_irq(chip->irq_base + j);
+                                ret = IRQ_HANDLED;
+                        }
+                }
+        }
+        return ret;
+}
+static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
+                                unsigned int irq_start, unsigned int num)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
+                                    handle_simple_irq);
+        gc->private = chip;
+        ct = gc->chip_types;
+        ct->chip.irq_mask = ioh_irq_mask;
+        ct->chip.irq_unmask = ioh_irq_unmask;
+        ct->chip.irq_set_type = ioh_irq_type;
+        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
                                    const struct pci_device_id *id)
 {
        int ret;
-        int i;
+        int i, j;
        struct ioh_gpio *chip;
        void __iomem *base;
        void __iomem *chip_save;
+        int irq_base;
        ret = pci_enable_device(pdev);
        if (ret) {
@@ -228,10 +426,41 @@ static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
        }
        chip = chip_save;
+        for (j = 0; j < 8; j++, chip++) {
+                irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
+                                           NUMA_NO_NODE);
+                if (irq_base < 0) {
+                        dev_warn(&pdev->dev,
+                                "ml_ioh_gpio: Failed to get IRQ base num\n");
+                        chip->irq_base = -1;
+                        goto err_irq_alloc_descs;
+                }
+                chip->irq_base = irq_base;
+                ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
+        }
+        chip = chip_save;
+        ret = request_irq(pdev->irq, ioh_gpio_handler,
+                             IRQF_SHARED, KBUILD_MODNAME, chip);
+        if (ret != 0) {
+                dev_err(&pdev->dev,
+                        "%s request_irq failed\n", __func__);
+                goto err_request_irq;
+        }
        pci_set_drvdata(pdev, chip);
        return 0;
+err_request_irq:
+        chip = chip_save;
+err_irq_alloc_descs:
+        while (--j >= 0) {
+                chip--;
+                irq_free_descs(chip->irq_base, num_ports[j]);
+        }
+        chip = chip_save;
 err_gpiochip_add:
        while (--i >= 0) {
                chip--;
@@ -264,7 +493,11 @@ static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
        void __iomem *chip_save;
        chip_save = chip;
+        free_irq(pdev->irq, chip);
        for (i = 0; i < 8; i++, chip++) {
+                irq_free_descs(chip->irq_base, num_ports[i]);
                err = gpiochip_remove(&chip->gpio);
                if (err)
                        dev_err(&pdev->dev, "Failed gpiochip_remove\n");
@@ -282,9 +515,11 @@ static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
 {
        s32 ret;
        struct ioh_gpio *chip = pci_get_drvdata(pdev);
+        unsigned long flags;
+        spin_lock_irqsave(&chip->spinlock, flags);
        ioh_gpio_save_reg_conf(chip);
-        ioh_gpio_restore_reg_conf(chip);
+        spin_unlock_irqrestore(&chip->spinlock, flags);
        ret = pci_save_state(pdev);
        if (ret) {
@@ -304,6 +539,7 @@ static int ioh_gpio_resume(struct pci_dev *pdev)
 {
        s32 ret;
        struct ioh_gpio *chip = pci_get_drvdata(pdev);
+        unsigned long flags;
        ret = pci_enable_wake(pdev, PCI_D0, 0);
@@ -315,9 +551,11 @@ static int ioh_gpio_resume(struct pci_dev *pdev)
        }
        pci_restore_state(pdev);
+        spin_lock_irqsave(&chip->spinlock, flags);
        iowrite32(0x01, &chip->reg->srst);
        iowrite32(0x00, &chip->reg->srst);
        ioh_gpio_restore_reg_conf(chip);
+        spin_unlock_irqrestore(&chip->spinlock, flags);
        return 0;
 }

diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c index a9016f56ed7e..3aa6beec8c1e 100644 --- a/drivers/gpio/gpio-ml-ioh.c +++ b/drivers/gpio/gpio-ml-ioh.c
@@ -18,6 +18,17 @@
18	#include <linux/slab.h>	18	#include <linux/slab.h>
19	#include <linux/pci.h>	19	#include <linux/pci.h>
20	#include <linux/gpio.h>	20	#include <linux/gpio.h>
		21	#include <linux/interrupt.h>
		22	#include <linux/irq.h>
		23
		24	#define IOH_EDGE_FALLING 0
		25	#define IOH_EDGE_RISING BIT(0)
		26	#define IOH_LEVEL_L BIT(1)
		27	#define IOH_LEVEL_H (BIT(0) \| BIT(1))
		28	#define IOH_EDGE_BOTH BIT(2)
		29	#define IOH_IM_MASK (BIT(0) \| BIT(1) \| BIT(2))
		30
		31	#define IOH_IRQ_BASE 0
21		32
22	#define PCI_VENDOR_ID_ROHM 0x10DB	33	#define PCI_VENDOR_ID_ROHM 0x10DB
23		34
@@ -46,12 +57,22 @@ struct ioh_regs {
46		57
47	/**	58	/**
48	* struct ioh_gpio_reg_data - The register store data.	59	* struct ioh_gpio_reg_data - The register store data.
		60	* @ien_reg To store contents of interrupt enable register.
		61	* @imask_reg: To store contents of interrupt mask regist
49	* @po_reg: To store contents of PO register.	62	* @po_reg: To store contents of PO register.
50	* @pm_reg: To store contents of PM register.	63	* @pm_reg: To store contents of PM register.
		64	* @im0_reg: To store contents of interrupt mode regist0
		65	* @im1_reg: To store contents of interrupt mode regist1
		66	* @use_sel_reg: To store contents of GPIO_USE_SEL0~3
51	*/	67	*/
52	struct ioh_gpio_reg_data {	68	struct ioh_gpio_reg_data {
		69	u32 ien_reg;
		70	u32 imask_reg;
53	u32 po_reg;	71	u32 po_reg;
54	u32 pm_reg;	72	u32 pm_reg;
		73	u32 im0_reg;
		74	u32 im1_reg;
		75	u32 use_sel_reg;
55	};	76	};
56		77
57	/**	78	/**
@@ -62,7 +83,11 @@ struct ioh_gpio_reg_data {
62	* @gpio: Data for GPIO infrastructure.	83	* @gpio: Data for GPIO infrastructure.
63	* @ioh_gpio_reg: Memory mapped Register data is saved here	84	* @ioh_gpio_reg: Memory mapped Register data is saved here
64	* when suspend.	85	* when suspend.
		86	* @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
65	* @ch: Indicate GPIO channel	87	* @ch: Indicate GPIO channel
		88	* @irq_base: Save base of IRQ number for interrupt
		89	* @spinlock: Used for register access protection in
		90	* interrupt context ioh_irq_type and PM;
66	*/	91	*/
67	struct ioh_gpio {	92	struct ioh_gpio {
68	void __iomem *base;	93	void __iomem *base;
@@ -70,8 +95,11 @@ struct ioh_gpio {
70	struct device *dev;	95	struct device *dev;
71	struct gpio_chip gpio;	96	struct gpio_chip gpio;
72	struct ioh_gpio_reg_data ioh_gpio_reg;	97	struct ioh_gpio_reg_data ioh_gpio_reg;
		98	u32 gpio_use_sel;
73	struct mutex lock;	99	struct mutex lock;
74	int ch;	100	int ch;
		101	int irq_base;
		102	spinlock_t spinlock;
75	};	103	};
76		104
77	static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};	105	static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
@@ -145,8 +173,25 @@ static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
145	*/	173	*/
146	static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)	174	static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
147	{	175	{
148	chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);	176	int i;
149	chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);	177
		178	for (i = 0; i < 8; i ++, chip++) {
		179	chip->ioh_gpio_reg.po_reg =
		180	ioread32(&chip->reg->regs[chip->ch].po);
		181	chip->ioh_gpio_reg.pm_reg =
		182	ioread32(&chip->reg->regs[chip->ch].pm);
		183	chip->ioh_gpio_reg.ien_reg =
		184	ioread32(&chip->reg->regs[chip->ch].ien);
		185	chip->ioh_gpio_reg.imask_reg =
		186	ioread32(&chip->reg->regs[chip->ch].imask);
		187	chip->ioh_gpio_reg.im0_reg =
		188	ioread32(&chip->reg->regs[chip->ch].im_0);
		189	chip->ioh_gpio_reg.im1_reg =
		190	ioread32(&chip->reg->regs[chip->ch].im_1);
		191	if (i < 4)
		192	chip->ioh_gpio_reg.use_sel_reg =
		193	ioread32(&chip->reg->ioh_sel_reg[i]);
		194	}
150	}	195	}
151		196
152	/*	197	/*
@@ -154,13 +199,34 @@ static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
154	*/	199	*/
155	static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)	200	static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
156	{	201	{
157	/* to store contents of PO register */	202	int i;
158	iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);	203
159	/* to store contents of PM register */	204	for (i = 0; i < 8; i ++, chip++) {
160	iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);	205	iowrite32(chip->ioh_gpio_reg.po_reg,
		206	&chip->reg->regs[chip->ch].po);
		207	iowrite32(chip->ioh_gpio_reg.pm_reg,
		208	&chip->reg->regs[chip->ch].pm);
		209	iowrite32(chip->ioh_gpio_reg.ien_reg,
		210	&chip->reg->regs[chip->ch].ien);
		211	iowrite32(chip->ioh_gpio_reg.imask_reg,
		212	&chip->reg->regs[chip->ch].imask);
		213	iowrite32(chip->ioh_gpio_reg.im0_reg,
		214	&chip->reg->regs[chip->ch].im_0);
		215	iowrite32(chip->ioh_gpio_reg.im1_reg,
		216	&chip->reg->regs[chip->ch].im_1);
		217	if (i < 4)
		218	iowrite32(chip->ioh_gpio_reg.use_sel_reg,
		219	&chip->reg->ioh_sel_reg[i]);
		220	}
161	}	221	}
162	#endif	222	#endif
163		223
		224	static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
		225	{
		226	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
		227	return chip->irq_base + offset;
		228	}
		229
164	static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)	230	static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
165	{	231	{
166	struct gpio_chip *gpio = &chip->gpio;	232	struct gpio_chip *gpio = &chip->gpio;
@@ -175,16 +241,148 @@ static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
175	gpio->base = -1;	241	gpio->base = -1;
176	gpio->ngpio = num_port;	242	gpio->ngpio = num_port;
177	gpio->can_sleep = 0;	243	gpio->can_sleep = 0;
		244	gpio->to_irq = ioh_gpio_to_irq;
		245	}
		246
		247	static int ioh_irq_type(struct irq_data *d, unsigned int type)
		248	{
		249	u32 im;
		250	u32 *im_reg;
		251	u32 ien;
		252	u32 im_pos;
		253	int ch;
		254	unsigned long flags;
		255	u32 val;
		256	int irq = d->irq;
		257	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
		258	struct ioh_gpio *chip = gc->private;
		259
		260	ch = irq - chip->irq_base;
		261	if (irq <= chip->irq_base + 7) {
		262	im_reg = &chip->reg->regs[chip->ch].im_0;
		263	im_pos = ch;
		264	} else {
		265	im_reg = &chip->reg->regs[chip->ch].im_1;
		266	im_pos = ch - 8;
		267	}
		268	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
		269	__func__, irq, type, ch, im_pos, type);
		270
		271	spin_lock_irqsave(&chip->spinlock, flags);
		272
		273	switch (type) {
		274	case IRQ_TYPE_EDGE_RISING:
		275	val = IOH_EDGE_RISING;
		276	break;
		277	case IRQ_TYPE_EDGE_FALLING:
		278	val = IOH_EDGE_FALLING;
		279	break;
		280	case IRQ_TYPE_EDGE_BOTH:
		281	val = IOH_EDGE_BOTH;
		282	break;
		283	case IRQ_TYPE_LEVEL_HIGH:
		284	val = IOH_LEVEL_H;
		285	break;
		286	case IRQ_TYPE_LEVEL_LOW:
		287	val = IOH_LEVEL_L;
		288	break;
		289	case IRQ_TYPE_PROBE:
		290	goto end;
		291	default:
		292	dev_warn(chip->dev, "%s: unknown type(%dd)",
		293	__func__, type);
		294	goto end;
		295	}
		296
		297	/* Set interrupt mode */
		298	im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
		299	iowrite32(im \| (val << (im_pos * 4)), im_reg);
		300
		301	/* iclr */
		302	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
		303
		304	/* IMASKCLR */
		305	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
		306
		307	/* Enable interrupt */
		308	ien = ioread32(&chip->reg->regs[chip->ch].ien);
		309	iowrite32(ien \| BIT(ch), &chip->reg->regs[chip->ch].ien);
		310	end:
		311	spin_unlock_irqrestore(&chip->spinlock, flags);
		312
		313	return 0;
		314	}
		315
		316	static void ioh_irq_unmask(struct irq_data *d)
		317	{
		318	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
		319	struct ioh_gpio *chip = gc->private;
		320
		321	iowrite32(1 << (d->irq - chip->irq_base),
		322	&chip->reg->regs[chip->ch].imaskclr);
		323	}
		324
		325	static void ioh_irq_mask(struct irq_data *d)
		326	{
		327	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
		328	struct ioh_gpio *chip = gc->private;
		329
		330	iowrite32(1 << (d->irq - chip->irq_base),
		331	&chip->reg->regs[chip->ch].imask);
		332	}
		333
		334	static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
		335	{
		336	struct ioh_gpio *chip = dev_id;
		337	u32 reg_val;
		338	int i, j;
		339	int ret = IRQ_NONE;
		340
		341	for (i = 0; i < 8; i++) {
		342	reg_val = ioread32(&chip->reg->regs[i].istatus);
		343	for (j = 0; j < num_ports[i]; j++) {
		344	if (reg_val & BIT(j)) {
		345	dev_dbg(chip->dev,
		346	"%s:[%d]:irq=%d status=0x%x\n",
		347	__func__, j, irq, reg_val);
		348	iowrite32(BIT(j),
		349	&chip->reg->regs[chip->ch].iclr);
		350	generic_handle_irq(chip->irq_base + j);
		351	ret = IRQ_HANDLED;
		352	}
		353	}
		354	}
		355	return ret;
		356	}
		357
		358	static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
		359	unsigned int irq_start, unsigned int num)
		360	{
		361	struct irq_chip_generic *gc;
		362	struct irq_chip_type *ct;
		363
		364	gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
		365	handle_simple_irq);
		366	gc->private = chip;
		367	ct = gc->chip_types;
		368
		369	ct->chip.irq_mask = ioh_irq_mask;
		370	ct->chip.irq_unmask = ioh_irq_unmask;
		371	ct->chip.irq_set_type = ioh_irq_type;
		372
		373	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
		374	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
178	}	375	}
179		376
180	static int __devinit ioh_gpio_probe(struct pci_dev *pdev,	377	static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
181	const struct pci_device_id *id)	378	const struct pci_device_id *id)
182	{	379	{
183	int ret;	380	int ret;
184	int i;	381	int i, j;
185	struct ioh_gpio *chip;	382	struct ioh_gpio *chip;
186	void __iomem *base;	383	void __iomem *base;
187	void __iomem *chip_save;	384	void __iomem *chip_save;
		385	int irq_base;
188		386
189	ret = pci_enable_device(pdev);	387	ret = pci_enable_device(pdev);
190	if (ret) {	388	if (ret) {
@@ -228,10 +426,41 @@ static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
228	}	426	}
229		427
230	chip = chip_save;	428	chip = chip_save;
		429	for (j = 0; j < 8; j++, chip++) {
		430	irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
		431	NUMA_NO_NODE);
		432	if (irq_base < 0) {
		433	dev_warn(&pdev->dev,
		434	"ml_ioh_gpio: Failed to get IRQ base num\n");
		435	chip->irq_base = -1;
		436	goto err_irq_alloc_descs;
		437	}
		438	chip->irq_base = irq_base;
		439	ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
		440	}
		441
		442	chip = chip_save;
		443	ret = request_irq(pdev->irq, ioh_gpio_handler,
		444	IRQF_SHARED, KBUILD_MODNAME, chip);
		445	if (ret != 0) {
		446	dev_err(&pdev->dev,
		447	"%s request_irq failed\n", __func__);
		448	goto err_request_irq;
		449	}
		450
231	pci_set_drvdata(pdev, chip);	451	pci_set_drvdata(pdev, chip);
232		452
233	return 0;	453	return 0;
234		454
		455	err_request_irq:
		456	chip = chip_save;
		457	err_irq_alloc_descs:
		458	while (--j >= 0) {
		459	chip--;
		460	irq_free_descs(chip->irq_base, num_ports[j]);
		461	}
		462
		463	chip = chip_save;
235	err_gpiochip_add:	464	err_gpiochip_add:
236	while (--i >= 0) {	465	while (--i >= 0) {
237	chip--;	466	chip--;
@@ -264,7 +493,11 @@ static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
264	void __iomem *chip_save;	493	void __iomem *chip_save;
265		494
266	chip_save = chip;	495	chip_save = chip;
		496
		497	free_irq(pdev->irq, chip);
		498
267	for (i = 0; i < 8; i++, chip++) {	499	for (i = 0; i < 8; i++, chip++) {
		500	irq_free_descs(chip->irq_base, num_ports[i]);
268	err = gpiochip_remove(&chip->gpio);	501	err = gpiochip_remove(&chip->gpio);
269	if (err)	502	if (err)
270	dev_err(&pdev->dev, "Failed gpiochip_remove\n");	503	dev_err(&pdev->dev, "Failed gpiochip_remove\n");
@@ -282,9 +515,11 @@ static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
282	{	515	{
283	s32 ret;	516	s32 ret;
284	struct ioh_gpio *chip = pci_get_drvdata(pdev);	517	struct ioh_gpio *chip = pci_get_drvdata(pdev);
		518	unsigned long flags;
285		519
		520	spin_lock_irqsave(&chip->spinlock, flags);
286	ioh_gpio_save_reg_conf(chip);	521	ioh_gpio_save_reg_conf(chip);
287	ioh_gpio_restore_reg_conf(chip);	522	spin_unlock_irqrestore(&chip->spinlock, flags);
288		523
289	ret = pci_save_state(pdev);	524	ret = pci_save_state(pdev);
290	if (ret) {	525	if (ret) {
@@ -304,6 +539,7 @@ static int ioh_gpio_resume(struct pci_dev *pdev)
304	{	539	{
305	s32 ret;	540	s32 ret;
306	struct ioh_gpio *chip = pci_get_drvdata(pdev);	541	struct ioh_gpio *chip = pci_get_drvdata(pdev);
		542	unsigned long flags;
307		543
308	ret = pci_enable_wake(pdev, PCI_D0, 0);	544	ret = pci_enable_wake(pdev, PCI_D0, 0);
309		545
@@ -315,9 +551,11 @@ static int ioh_gpio_resume(struct pci_dev *pdev)
315	}	551	}
316	pci_restore_state(pdev);	552	pci_restore_state(pdev);
317		553
		554	spin_lock_irqsave(&chip->spinlock, flags);
318	iowrite32(0x01, &chip->reg->srst);	555	iowrite32(0x01, &chip->reg->srst);
319	iowrite32(0x00, &chip->reg->srst);	556	iowrite32(0x00, &chip->reg->srst);
320	ioh_gpio_restore_reg_conf(chip);	557	ioh_gpio_restore_reg_conf(chip);
		558	spin_unlock_irqrestore(&chip->spinlock, flags);
321		559
322	return 0;	560	return 0;
323	}	561	}