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path: root/drivers/gpio/gpio-ml-ioh.c
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Diffstat (limited to 'drivers/gpio/gpio-ml-ioh.c')
-rw-r--r--drivers/gpio/gpio-ml-ioh.c32
1 files changed, 31 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c
index ea8e73869250..461958fc2264 100644
--- a/drivers/gpio/gpio-ml-ioh.c
+++ b/drivers/gpio/gpio-ml-ioh.c
@@ -332,6 +332,34 @@ static void ioh_irq_mask(struct irq_data *d)
332 &chip->reg->regs[chip->ch].imask); 332 &chip->reg->regs[chip->ch].imask);
333} 333}
334 334
335static void ioh_irq_disable(struct irq_data *d)
336{
337 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
338 struct ioh_gpio *chip = gc->private;
339 unsigned long flags;
340 u32 ien;
341
342 spin_lock_irqsave(&chip->spinlock, flags);
343 ien = ioread32(&chip->reg->regs[chip->ch].ien);
344 ien &= ~(1 << (d->irq - chip->irq_base));
345 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
346 spin_unlock_irqrestore(&chip->spinlock, flags);
347}
348
349static void ioh_irq_enable(struct irq_data *d)
350{
351 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
352 struct ioh_gpio *chip = gc->private;
353 unsigned long flags;
354 u32 ien;
355
356 spin_lock_irqsave(&chip->spinlock, flags);
357 ien = ioread32(&chip->reg->regs[chip->ch].ien);
358 ien |= 1 << (d->irq - chip->irq_base);
359 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
360 spin_unlock_irqrestore(&chip->spinlock, flags);
361}
362
335static irqreturn_t ioh_gpio_handler(int irq, void *dev_id) 363static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
336{ 364{
337 struct ioh_gpio *chip = dev_id; 365 struct ioh_gpio *chip = dev_id;
@@ -339,7 +367,7 @@ static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
339 int i, j; 367 int i, j;
340 int ret = IRQ_NONE; 368 int ret = IRQ_NONE;
341 369
342 for (i = 0; i < 8; i++) { 370 for (i = 0; i < 8; i++, chip++) {
343 reg_val = ioread32(&chip->reg->regs[i].istatus); 371 reg_val = ioread32(&chip->reg->regs[i].istatus);
344 for (j = 0; j < num_ports[i]; j++) { 372 for (j = 0; j < num_ports[i]; j++) {
345 if (reg_val & BIT(j)) { 373 if (reg_val & BIT(j)) {
@@ -370,6 +398,8 @@ static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
370 ct->chip.irq_mask = ioh_irq_mask; 398 ct->chip.irq_mask = ioh_irq_mask;
371 ct->chip.irq_unmask = ioh_irq_unmask; 399 ct->chip.irq_unmask = ioh_irq_unmask;
372 ct->chip.irq_set_type = ioh_irq_type; 400 ct->chip.irq_set_type = ioh_irq_type;
401 ct->chip.irq_disable = ioh_irq_disable;
402 ct->chip.irq_enable = ioh_irq_enable;
373 403
374 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 404 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
375 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 405 IRQ_NOREQUEST | IRQ_NOPROBE, 0);