diff options
Diffstat (limited to 'drivers/firewire/ohci.c')
-rw-r--r-- | drivers/firewire/ohci.c | 350 |
1 files changed, 209 insertions, 141 deletions
diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c index 7f5f0da726da..187b3f2e797e 100644 --- a/drivers/firewire/ohci.c +++ b/drivers/firewire/ohci.c | |||
@@ -170,10 +170,12 @@ struct context { | |||
170 | struct iso_context { | 170 | struct iso_context { |
171 | struct fw_iso_context base; | 171 | struct fw_iso_context base; |
172 | struct context context; | 172 | struct context context; |
173 | int excess_bytes; | ||
174 | void *header; | 173 | void *header; |
175 | size_t header_length; | 174 | size_t header_length; |
176 | 175 | unsigned long flushing_completions; | |
176 | u32 mc_buffer_bus; | ||
177 | u16 mc_completed; | ||
178 | u16 last_timestamp; | ||
177 | u8 sync; | 179 | u8 sync; |
178 | u8 tags; | 180 | u8 tags; |
179 | }; | 181 | }; |
@@ -338,8 +340,6 @@ MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" | |||
338 | #define OHCI_PARAM_DEBUG_IRQS 4 | 340 | #define OHCI_PARAM_DEBUG_IRQS 4 |
339 | #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ | 341 | #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ |
340 | 342 | ||
341 | #ifdef CONFIG_FIREWIRE_OHCI_DEBUG | ||
342 | |||
343 | static int param_debug; | 343 | static int param_debug; |
344 | module_param_named(debug, param_debug, int, 0644); | 344 | module_param_named(debug, param_debug, int, 0644); |
345 | MODULE_PARM_DESC(debug, "Verbose logging (default = 0" | 345 | MODULE_PARM_DESC(debug, "Verbose logging (default = 0" |
@@ -349,7 +349,7 @@ MODULE_PARM_DESC(debug, "Verbose logging (default = 0" | |||
349 | ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) | 349 | ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) |
350 | ", or a combination, or all = -1)"); | 350 | ", or a combination, or all = -1)"); |
351 | 351 | ||
352 | static void log_irqs(u32 evt) | 352 | static void log_irqs(struct fw_ohci *ohci, u32 evt) |
353 | { | 353 | { |
354 | if (likely(!(param_debug & | 354 | if (likely(!(param_debug & |
355 | (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) | 355 | (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) |
@@ -359,7 +359,8 @@ static void log_irqs(u32 evt) | |||
359 | !(evt & OHCI1394_busReset)) | 359 | !(evt & OHCI1394_busReset)) |
360 | return; | 360 | return; |
361 | 361 | ||
362 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, | 362 | dev_notice(ohci->card.device, |
363 | "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, | ||
363 | evt & OHCI1394_selfIDComplete ? " selfID" : "", | 364 | evt & OHCI1394_selfIDComplete ? " selfID" : "", |
364 | evt & OHCI1394_RQPkt ? " AR_req" : "", | 365 | evt & OHCI1394_RQPkt ? " AR_req" : "", |
365 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | 366 | evt & OHCI1394_RSPkt ? " AR_resp" : "", |
@@ -398,24 +399,29 @@ static char _p(u32 *s, int shift) | |||
398 | return port[*s >> shift & 3]; | 399 | return port[*s >> shift & 3]; |
399 | } | 400 | } |
400 | 401 | ||
401 | static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) | 402 | static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) |
402 | { | 403 | { |
404 | u32 *s; | ||
405 | |||
403 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) | 406 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) |
404 | return; | 407 | return; |
405 | 408 | ||
406 | fw_notify("%d selfIDs, generation %d, local node ID %04x\n", | 409 | dev_notice(ohci->card.device, |
407 | self_id_count, generation, node_id); | 410 | "%d selfIDs, generation %d, local node ID %04x\n", |
411 | self_id_count, generation, ohci->node_id); | ||
408 | 412 | ||
409 | for (; self_id_count--; ++s) | 413 | for (s = ohci->self_id_buffer; self_id_count--; ++s) |
410 | if ((*s & 1 << 23) == 0) | 414 | if ((*s & 1 << 23) == 0) |
411 | fw_notify("selfID 0: %08x, phy %d [%c%c%c] " | 415 | dev_notice(ohci->card.device, |
416 | "selfID 0: %08x, phy %d [%c%c%c] " | ||
412 | "%s gc=%d %s %s%s%s\n", | 417 | "%s gc=%d %s %s%s%s\n", |
413 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), | 418 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), |
414 | speed[*s >> 14 & 3], *s >> 16 & 63, | 419 | speed[*s >> 14 & 3], *s >> 16 & 63, |
415 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", | 420 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", |
416 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); | 421 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); |
417 | else | 422 | else |
418 | fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", | 423 | dev_notice(ohci->card.device, |
424 | "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", | ||
419 | *s, *s >> 24 & 63, | 425 | *s, *s >> 24 & 63, |
420 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), | 426 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), |
421 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); | 427 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); |
@@ -451,7 +457,8 @@ static const char *tcodes[] = { | |||
451 | [0xe] = "link internal", [0xf] = "-reserved-", | 457 | [0xe] = "link internal", [0xf] = "-reserved-", |
452 | }; | 458 | }; |
453 | 459 | ||
454 | static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | 460 | static void log_ar_at_event(struct fw_ohci *ohci, |
461 | char dir, int speed, u32 *header, int evt) | ||
455 | { | 462 | { |
456 | int tcode = header[0] >> 4 & 0xf; | 463 | int tcode = header[0] >> 4 & 0xf; |
457 | char specific[12]; | 464 | char specific[12]; |
@@ -463,8 +470,9 @@ static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |||
463 | evt = 0x1f; | 470 | evt = 0x1f; |
464 | 471 | ||
465 | if (evt == OHCI1394_evt_bus_reset) { | 472 | if (evt == OHCI1394_evt_bus_reset) { |
466 | fw_notify("A%c evt_bus_reset, generation %d\n", | 473 | dev_notice(ohci->card.device, |
467 | dir, (header[2] >> 16) & 0xff); | 474 | "A%c evt_bus_reset, generation %d\n", |
475 | dir, (header[2] >> 16) & 0xff); | ||
468 | return; | 476 | return; |
469 | } | 477 | } |
470 | 478 | ||
@@ -483,39 +491,35 @@ static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |||
483 | 491 | ||
484 | switch (tcode) { | 492 | switch (tcode) { |
485 | case 0xa: | 493 | case 0xa: |
486 | fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); | 494 | dev_notice(ohci->card.device, |
495 | "A%c %s, %s\n", | ||
496 | dir, evts[evt], tcodes[tcode]); | ||
487 | break; | 497 | break; |
488 | case 0xe: | 498 | case 0xe: |
489 | fw_notify("A%c %s, PHY %08x %08x\n", | 499 | dev_notice(ohci->card.device, |
490 | dir, evts[evt], header[1], header[2]); | 500 | "A%c %s, PHY %08x %08x\n", |
501 | dir, evts[evt], header[1], header[2]); | ||
491 | break; | 502 | break; |
492 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: | 503 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: |
493 | fw_notify("A%c spd %x tl %02x, " | 504 | dev_notice(ohci->card.device, |
494 | "%04x -> %04x, %s, " | 505 | "A%c spd %x tl %02x, " |
495 | "%s, %04x%08x%s\n", | 506 | "%04x -> %04x, %s, " |
496 | dir, speed, header[0] >> 10 & 0x3f, | 507 | "%s, %04x%08x%s\n", |
497 | header[1] >> 16, header[0] >> 16, evts[evt], | 508 | dir, speed, header[0] >> 10 & 0x3f, |
498 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | 509 | header[1] >> 16, header[0] >> 16, evts[evt], |
510 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | ||
499 | break; | 511 | break; |
500 | default: | 512 | default: |
501 | fw_notify("A%c spd %x tl %02x, " | 513 | dev_notice(ohci->card.device, |
502 | "%04x -> %04x, %s, " | 514 | "A%c spd %x tl %02x, " |
503 | "%s%s\n", | 515 | "%04x -> %04x, %s, " |
504 | dir, speed, header[0] >> 10 & 0x3f, | 516 | "%s%s\n", |
505 | header[1] >> 16, header[0] >> 16, evts[evt], | 517 | dir, speed, header[0] >> 10 & 0x3f, |
506 | tcodes[tcode], specific); | 518 | header[1] >> 16, header[0] >> 16, evts[evt], |
519 | tcodes[tcode], specific); | ||
507 | } | 520 | } |
508 | } | 521 | } |
509 | 522 | ||
510 | #else | ||
511 | |||
512 | #define param_debug 0 | ||
513 | static inline void log_irqs(u32 evt) {} | ||
514 | static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {} | ||
515 | static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {} | ||
516 | |||
517 | #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ | ||
518 | |||
519 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) | 523 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
520 | { | 524 | { |
521 | writel(data, ohci->registers + offset); | 525 | writel(data, ohci->registers + offset); |
@@ -559,7 +563,7 @@ static int read_phy_reg(struct fw_ohci *ohci, int addr) | |||
559 | if (i >= 3) | 563 | if (i >= 3) |
560 | msleep(1); | 564 | msleep(1); |
561 | } | 565 | } |
562 | fw_error("failed to read phy reg\n"); | 566 | dev_err(ohci->card.device, "failed to read phy reg\n"); |
563 | 567 | ||
564 | return -EBUSY; | 568 | return -EBUSY; |
565 | } | 569 | } |
@@ -581,7 +585,7 @@ static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) | |||
581 | if (i >= 3) | 585 | if (i >= 3) |
582 | msleep(1); | 586 | msleep(1); |
583 | } | 587 | } |
584 | fw_error("failed to write phy reg\n"); | 588 | dev_err(ohci->card.device, "failed to write phy reg\n"); |
585 | 589 | ||
586 | return -EBUSY; | 590 | return -EBUSY; |
587 | } | 591 | } |
@@ -680,11 +684,14 @@ static void ar_context_release(struct ar_context *ctx) | |||
680 | 684 | ||
681 | static void ar_context_abort(struct ar_context *ctx, const char *error_msg) | 685 | static void ar_context_abort(struct ar_context *ctx, const char *error_msg) |
682 | { | 686 | { |
683 | if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { | 687 | struct fw_ohci *ohci = ctx->ohci; |
684 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); | 688 | |
685 | flush_writes(ctx->ohci); | 689 | if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { |
690 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); | ||
691 | flush_writes(ohci); | ||
686 | 692 | ||
687 | fw_error("AR error: %s; DMA stopped\n", error_msg); | 693 | dev_err(ohci->card.device, "AR error: %s; DMA stopped\n", |
694 | error_msg); | ||
688 | } | 695 | } |
689 | /* FIXME: restart? */ | 696 | /* FIXME: restart? */ |
690 | } | 697 | } |
@@ -854,7 +861,7 @@ static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) | |||
854 | p.timestamp = status & 0xffff; | 861 | p.timestamp = status & 0xffff; |
855 | p.generation = ohci->request_generation; | 862 | p.generation = ohci->request_generation; |
856 | 863 | ||
857 | log_ar_at_event('R', p.speed, p.header, evt); | 864 | log_ar_at_event(ohci, 'R', p.speed, p.header, evt); |
858 | 865 | ||
859 | /* | 866 | /* |
860 | * Several controllers, notably from NEC and VIA, forget to | 867 | * Several controllers, notably from NEC and VIA, forget to |
@@ -1226,21 +1233,22 @@ static void context_append(struct context *ctx, | |||
1226 | 1233 | ||
1227 | static void context_stop(struct context *ctx) | 1234 | static void context_stop(struct context *ctx) |
1228 | { | 1235 | { |
1236 | struct fw_ohci *ohci = ctx->ohci; | ||
1229 | u32 reg; | 1237 | u32 reg; |
1230 | int i; | 1238 | int i; |
1231 | 1239 | ||
1232 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); | 1240 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
1233 | ctx->running = false; | 1241 | ctx->running = false; |
1234 | 1242 | ||
1235 | for (i = 0; i < 1000; i++) { | 1243 | for (i = 0; i < 1000; i++) { |
1236 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); | 1244 | reg = reg_read(ohci, CONTROL_SET(ctx->regs)); |
1237 | if ((reg & CONTEXT_ACTIVE) == 0) | 1245 | if ((reg & CONTEXT_ACTIVE) == 0) |
1238 | return; | 1246 | return; |
1239 | 1247 | ||
1240 | if (i) | 1248 | if (i) |
1241 | udelay(10); | 1249 | udelay(10); |
1242 | } | 1250 | } |
1243 | fw_error("Error: DMA context still active (0x%08x)\n", reg); | 1251 | dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg); |
1244 | } | 1252 | } |
1245 | 1253 | ||
1246 | struct driver_data { | 1254 | struct driver_data { |
@@ -1420,7 +1428,7 @@ static int handle_at_packet(struct context *context, | |||
1420 | evt = le16_to_cpu(last->transfer_status) & 0x1f; | 1428 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
1421 | packet->timestamp = le16_to_cpu(last->res_count); | 1429 | packet->timestamp = le16_to_cpu(last->res_count); |
1422 | 1430 | ||
1423 | log_ar_at_event('T', packet->speed, packet->header, evt); | 1431 | log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); |
1424 | 1432 | ||
1425 | switch (evt) { | 1433 | switch (evt) { |
1426 | case OHCI1394_evt_timeout: | 1434 | case OHCI1394_evt_timeout: |
@@ -1549,7 +1557,7 @@ static void handle_local_lock(struct fw_ohci *ohci, | |||
1549 | goto out; | 1557 | goto out; |
1550 | } | 1558 | } |
1551 | 1559 | ||
1552 | fw_error("swap not done (CSR lock timeout)\n"); | 1560 | dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n"); |
1553 | fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); | 1561 | fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); |
1554 | 1562 | ||
1555 | out: | 1563 | out: |
@@ -1623,15 +1631,10 @@ static void detect_dead_context(struct fw_ohci *ohci, | |||
1623 | u32 ctl; | 1631 | u32 ctl; |
1624 | 1632 | ||
1625 | ctl = reg_read(ohci, CONTROL_SET(regs)); | 1633 | ctl = reg_read(ohci, CONTROL_SET(regs)); |
1626 | if (ctl & CONTEXT_DEAD) { | 1634 | if (ctl & CONTEXT_DEAD) |
1627 | #ifdef CONFIG_FIREWIRE_OHCI_DEBUG | 1635 | dev_err(ohci->card.device, |
1628 | fw_error("DMA context %s has stopped, error code: %s\n", | 1636 | "DMA context %s has stopped, error code: %s\n", |
1629 | name, evts[ctl & 0x1f]); | 1637 | name, evts[ctl & 0x1f]); |
1630 | #else | ||
1631 | fw_error("DMA context %s has stopped, error code: %#x\n", | ||
1632 | name, ctl & 0x1f); | ||
1633 | #endif | ||
1634 | } | ||
1635 | } | 1638 | } |
1636 | 1639 | ||
1637 | static void handle_dead_contexts(struct fw_ohci *ohci) | 1640 | static void handle_dead_contexts(struct fw_ohci *ohci) |
@@ -1781,7 +1784,8 @@ static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) | |||
1781 | 1784 | ||
1782 | reg = reg_read(ohci, OHCI1394_NodeID); | 1785 | reg = reg_read(ohci, OHCI1394_NodeID); |
1783 | if (!(reg & OHCI1394_NodeID_idValid)) { | 1786 | if (!(reg & OHCI1394_NodeID_idValid)) { |
1784 | fw_notify("node ID not valid, new bus reset in progress\n"); | 1787 | dev_notice(ohci->card.device, |
1788 | "node ID not valid, new bus reset in progress\n"); | ||
1785 | return -EBUSY; | 1789 | return -EBUSY; |
1786 | } | 1790 | } |
1787 | self_id |= ((reg & 0x3f) << 24); /* phy ID */ | 1791 | self_id |= ((reg & 0x3f) << 24); /* phy ID */ |
@@ -1827,11 +1831,12 @@ static void bus_reset_work(struct work_struct *work) | |||
1827 | 1831 | ||
1828 | reg = reg_read(ohci, OHCI1394_NodeID); | 1832 | reg = reg_read(ohci, OHCI1394_NodeID); |
1829 | if (!(reg & OHCI1394_NodeID_idValid)) { | 1833 | if (!(reg & OHCI1394_NodeID_idValid)) { |
1830 | fw_notify("node ID not valid, new bus reset in progress\n"); | 1834 | dev_notice(ohci->card.device, |
1835 | "node ID not valid, new bus reset in progress\n"); | ||
1831 | return; | 1836 | return; |
1832 | } | 1837 | } |
1833 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { | 1838 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
1834 | fw_notify("malconfigured bus\n"); | 1839 | dev_notice(ohci->card.device, "malconfigured bus\n"); |
1835 | return; | 1840 | return; |
1836 | } | 1841 | } |
1837 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | 1842 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | |
@@ -1845,7 +1850,7 @@ static void bus_reset_work(struct work_struct *work) | |||
1845 | 1850 | ||
1846 | reg = reg_read(ohci, OHCI1394_SelfIDCount); | 1851 | reg = reg_read(ohci, OHCI1394_SelfIDCount); |
1847 | if (reg & OHCI1394_SelfIDCount_selfIDError) { | 1852 | if (reg & OHCI1394_SelfIDCount_selfIDError) { |
1848 | fw_notify("inconsistent self IDs\n"); | 1853 | dev_notice(ohci->card.device, "inconsistent self IDs\n"); |
1849 | return; | 1854 | return; |
1850 | } | 1855 | } |
1851 | /* | 1856 | /* |
@@ -1857,7 +1862,7 @@ static void bus_reset_work(struct work_struct *work) | |||
1857 | self_id_count = (reg >> 3) & 0xff; | 1862 | self_id_count = (reg >> 3) & 0xff; |
1858 | 1863 | ||
1859 | if (self_id_count > 252) { | 1864 | if (self_id_count > 252) { |
1860 | fw_notify("inconsistent self IDs\n"); | 1865 | dev_notice(ohci->card.device, "inconsistent self IDs\n"); |
1861 | return; | 1866 | return; |
1862 | } | 1867 | } |
1863 | 1868 | ||
@@ -1875,11 +1880,13 @@ static void bus_reset_work(struct work_struct *work) | |||
1875 | */ | 1880 | */ |
1876 | if (cond_le32_to_cpu(ohci->self_id_cpu[i]) | 1881 | if (cond_le32_to_cpu(ohci->self_id_cpu[i]) |
1877 | == 0xffff008f) { | 1882 | == 0xffff008f) { |
1878 | fw_notify("ignoring spurious self IDs\n"); | 1883 | dev_notice(ohci->card.device, |
1884 | "ignoring spurious self IDs\n"); | ||
1879 | self_id_count = j; | 1885 | self_id_count = j; |
1880 | break; | 1886 | break; |
1881 | } else { | 1887 | } else { |
1882 | fw_notify("inconsistent self IDs\n"); | 1888 | dev_notice(ohci->card.device, |
1889 | "inconsistent self IDs\n"); | ||
1883 | return; | 1890 | return; |
1884 | } | 1891 | } |
1885 | } | 1892 | } |
@@ -1890,13 +1897,14 @@ static void bus_reset_work(struct work_struct *work) | |||
1890 | if (ohci->quirks & QUIRK_TI_SLLZ059) { | 1897 | if (ohci->quirks & QUIRK_TI_SLLZ059) { |
1891 | self_id_count = find_and_insert_self_id(ohci, self_id_count); | 1898 | self_id_count = find_and_insert_self_id(ohci, self_id_count); |
1892 | if (self_id_count < 0) { | 1899 | if (self_id_count < 0) { |
1893 | fw_notify("could not construct local self ID\n"); | 1900 | dev_notice(ohci->card.device, |
1901 | "could not construct local self ID\n"); | ||
1894 | return; | 1902 | return; |
1895 | } | 1903 | } |
1896 | } | 1904 | } |
1897 | 1905 | ||
1898 | if (self_id_count == 0) { | 1906 | if (self_id_count == 0) { |
1899 | fw_notify("inconsistent self IDs\n"); | 1907 | dev_notice(ohci->card.device, "inconsistent self IDs\n"); |
1900 | return; | 1908 | return; |
1901 | } | 1909 | } |
1902 | rmb(); | 1910 | rmb(); |
@@ -1917,8 +1925,8 @@ static void bus_reset_work(struct work_struct *work) | |||
1917 | 1925 | ||
1918 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | 1926 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; |
1919 | if (new_generation != generation) { | 1927 | if (new_generation != generation) { |
1920 | fw_notify("recursive bus reset detected, " | 1928 | dev_notice(ohci->card.device, |
1921 | "discarding self ids\n"); | 1929 | "new bus reset, discarding self ids\n"); |
1922 | return; | 1930 | return; |
1923 | } | 1931 | } |
1924 | 1932 | ||
@@ -1989,8 +1997,7 @@ static void bus_reset_work(struct work_struct *work) | |||
1989 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | 1997 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, |
1990 | free_rom, free_rom_bus); | 1998 | free_rom, free_rom_bus); |
1991 | 1999 | ||
1992 | log_selfids(ohci->node_id, generation, | 2000 | log_selfids(ohci, generation, self_id_count); |
1993 | self_id_count, ohci->self_id_buffer); | ||
1994 | 2001 | ||
1995 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, | 2002 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
1996 | self_id_count, ohci->self_id_buffer, | 2003 | self_id_count, ohci->self_id_buffer, |
@@ -2015,7 +2022,7 @@ static irqreturn_t irq_handler(int irq, void *data) | |||
2015 | */ | 2022 | */ |
2016 | reg_write(ohci, OHCI1394_IntEventClear, | 2023 | reg_write(ohci, OHCI1394_IntEventClear, |
2017 | event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); | 2024 | event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); |
2018 | log_irqs(event); | 2025 | log_irqs(ohci, event); |
2019 | 2026 | ||
2020 | if (event & OHCI1394_selfIDComplete) | 2027 | if (event & OHCI1394_selfIDComplete) |
2021 | queue_work(fw_workqueue, &ohci->bus_reset_work); | 2028 | queue_work(fw_workqueue, &ohci->bus_reset_work); |
@@ -2057,8 +2064,7 @@ static irqreturn_t irq_handler(int irq, void *data) | |||
2057 | } | 2064 | } |
2058 | 2065 | ||
2059 | if (unlikely(event & OHCI1394_regAccessFail)) | 2066 | if (unlikely(event & OHCI1394_regAccessFail)) |
2060 | fw_error("Register access failure - " | 2067 | dev_err(ohci->card.device, "register access failure\n"); |
2061 | "please notify linux1394-devel@lists.sf.net\n"); | ||
2062 | 2068 | ||
2063 | if (unlikely(event & OHCI1394_postedWriteErr)) { | 2069 | if (unlikely(event & OHCI1394_postedWriteErr)) { |
2064 | reg_read(ohci, OHCI1394_PostedWriteAddressHi); | 2070 | reg_read(ohci, OHCI1394_PostedWriteAddressHi); |
@@ -2066,12 +2072,13 @@ static irqreturn_t irq_handler(int irq, void *data) | |||
2066 | reg_write(ohci, OHCI1394_IntEventClear, | 2072 | reg_write(ohci, OHCI1394_IntEventClear, |
2067 | OHCI1394_postedWriteErr); | 2073 | OHCI1394_postedWriteErr); |
2068 | if (printk_ratelimit()) | 2074 | if (printk_ratelimit()) |
2069 | fw_error("PCI posted write error\n"); | 2075 | dev_err(ohci->card.device, "PCI posted write error\n"); |
2070 | } | 2076 | } |
2071 | 2077 | ||
2072 | if (unlikely(event & OHCI1394_cycleTooLong)) { | 2078 | if (unlikely(event & OHCI1394_cycleTooLong)) { |
2073 | if (printk_ratelimit()) | 2079 | if (printk_ratelimit()) |
2074 | fw_notify("isochronous cycle too long\n"); | 2080 | dev_notice(ohci->card.device, |
2081 | "isochronous cycle too long\n"); | ||
2075 | reg_write(ohci, OHCI1394_LinkControlSet, | 2082 | reg_write(ohci, OHCI1394_LinkControlSet, |
2076 | OHCI1394_LinkControl_cycleMaster); | 2083 | OHCI1394_LinkControl_cycleMaster); |
2077 | } | 2084 | } |
@@ -2084,7 +2091,8 @@ static irqreturn_t irq_handler(int irq, void *data) | |||
2084 | * them at least two cycles later. (FIXME?) | 2091 | * them at least two cycles later. (FIXME?) |
2085 | */ | 2092 | */ |
2086 | if (printk_ratelimit()) | 2093 | if (printk_ratelimit()) |
2087 | fw_notify("isochronous cycle inconsistent\n"); | 2094 | dev_notice(ohci->card.device, |
2095 | "isochronous cycle inconsistent\n"); | ||
2088 | } | 2096 | } |
2089 | 2097 | ||
2090 | if (unlikely(event & OHCI1394_unrecoverableError)) | 2098 | if (unlikely(event & OHCI1394_unrecoverableError)) |
@@ -2211,7 +2219,7 @@ static int ohci_enable(struct fw_card *card, | |||
2211 | int i, ret; | 2219 | int i, ret; |
2212 | 2220 | ||
2213 | if (software_reset(ohci)) { | 2221 | if (software_reset(ohci)) { |
2214 | fw_error("Failed to reset ohci card.\n"); | 2222 | dev_err(card->device, "failed to reset ohci card\n"); |
2215 | return -EBUSY; | 2223 | return -EBUSY; |
2216 | } | 2224 | } |
2217 | 2225 | ||
@@ -2235,7 +2243,7 @@ static int ohci_enable(struct fw_card *card, | |||
2235 | } | 2243 | } |
2236 | 2244 | ||
2237 | if (!lps) { | 2245 | if (!lps) { |
2238 | fw_error("Failed to set Link Power Status\n"); | 2246 | dev_err(card->device, "failed to set Link Power Status\n"); |
2239 | return -EIO; | 2247 | return -EIO; |
2240 | } | 2248 | } |
2241 | 2249 | ||
@@ -2244,7 +2252,7 @@ static int ohci_enable(struct fw_card *card, | |||
2244 | if (ret < 0) | 2252 | if (ret < 0) |
2245 | return ret; | 2253 | return ret; |
2246 | if (ret) | 2254 | if (ret) |
2247 | fw_notify("local TSB41BA3D phy\n"); | 2255 | dev_notice(card->device, "local TSB41BA3D phy\n"); |
2248 | else | 2256 | else |
2249 | ohci->quirks &= ~QUIRK_TI_SLLZ059; | 2257 | ohci->quirks &= ~QUIRK_TI_SLLZ059; |
2250 | } | 2258 | } |
@@ -2344,7 +2352,8 @@ static int ohci_enable(struct fw_card *card, | |||
2344 | if (request_irq(dev->irq, irq_handler, | 2352 | if (request_irq(dev->irq, irq_handler, |
2345 | pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, | 2353 | pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, |
2346 | ohci_driver_name, ohci)) { | 2354 | ohci_driver_name, ohci)) { |
2347 | fw_error("Failed to allocate interrupt %d.\n", dev->irq); | 2355 | dev_err(card->device, "failed to allocate interrupt %d\n", |
2356 | dev->irq); | ||
2348 | pci_disable_msi(dev); | 2357 | pci_disable_msi(dev); |
2349 | 2358 | ||
2350 | if (config_rom) { | 2359 | if (config_rom) { |
@@ -2509,7 +2518,7 @@ static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) | |||
2509 | dma_unmap_single(ohci->card.device, packet->payload_bus, | 2518 | dma_unmap_single(ohci->card.device, packet->payload_bus, |
2510 | packet->payload_length, DMA_TO_DEVICE); | 2519 | packet->payload_length, DMA_TO_DEVICE); |
2511 | 2520 | ||
2512 | log_ar_at_event('T', packet->speed, packet->header, 0x20); | 2521 | log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); |
2513 | driver_data->packet = NULL; | 2522 | driver_data->packet = NULL; |
2514 | packet->ack = RCODE_CANCELLED; | 2523 | packet->ack = RCODE_CANCELLED; |
2515 | packet->callback(packet, &ohci->card, packet->ack); | 2524 | packet->callback(packet, &ohci->card, packet->ack); |
@@ -2674,25 +2683,35 @@ static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) | |||
2674 | } | 2683 | } |
2675 | } | 2684 | } |
2676 | 2685 | ||
2677 | static void copy_iso_headers(struct iso_context *ctx, void *p) | 2686 | static void flush_iso_completions(struct iso_context *ctx) |
2678 | { | 2687 | { |
2679 | int i = ctx->header_length; | 2688 | ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, |
2689 | ctx->header_length, ctx->header, | ||
2690 | ctx->base.callback_data); | ||
2691 | ctx->header_length = 0; | ||
2692 | } | ||
2680 | 2693 | ||
2681 | if (i + ctx->base.header_size > PAGE_SIZE) | 2694 | static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) |
2682 | return; | 2695 | { |
2696 | u32 *ctx_hdr; | ||
2697 | |||
2698 | if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) | ||
2699 | flush_iso_completions(ctx); | ||
2700 | |||
2701 | ctx_hdr = ctx->header + ctx->header_length; | ||
2702 | ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); | ||
2683 | 2703 | ||
2684 | /* | 2704 | /* |
2685 | * The iso header is byteswapped to little endian by | 2705 | * The two iso header quadlets are byteswapped to little |
2686 | * the controller, but the remaining header quadlets | 2706 | * endian by the controller, but we want to present them |
2687 | * are big endian. We want to present all the headers | 2707 | * as big endian for consistency with the bus endianness. |
2688 | * as big endian, so we have to swap the first quadlet. | ||
2689 | */ | 2708 | */ |
2690 | if (ctx->base.header_size > 0) | 2709 | if (ctx->base.header_size > 0) |
2691 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | 2710 | ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ |
2692 | if (ctx->base.header_size > 4) | 2711 | if (ctx->base.header_size > 4) |
2693 | *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); | 2712 | ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ |
2694 | if (ctx->base.header_size > 8) | 2713 | if (ctx->base.header_size > 8) |
2695 | memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); | 2714 | memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); |
2696 | ctx->header_length += ctx->base.header_size; | 2715 | ctx->header_length += ctx->base.header_size; |
2697 | } | 2716 | } |
2698 | 2717 | ||
@@ -2704,8 +2723,6 @@ static int handle_ir_packet_per_buffer(struct context *context, | |||
2704 | container_of(context, struct iso_context, context); | 2723 | container_of(context, struct iso_context, context); |
2705 | struct descriptor *pd; | 2724 | struct descriptor *pd; |
2706 | u32 buffer_dma; | 2725 | u32 buffer_dma; |
2707 | __le32 *ir_header; | ||
2708 | void *p; | ||
2709 | 2726 | ||
2710 | for (pd = d; pd <= last; pd++) | 2727 | for (pd = d; pd <= last; pd++) |
2711 | if (pd->transfer_status) | 2728 | if (pd->transfer_status) |
@@ -2724,17 +2741,10 @@ static int handle_ir_packet_per_buffer(struct context *context, | |||
2724 | DMA_FROM_DEVICE); | 2741 | DMA_FROM_DEVICE); |
2725 | } | 2742 | } |
2726 | 2743 | ||
2727 | p = last + 1; | 2744 | copy_iso_headers(ctx, (u32 *) (last + 1)); |
2728 | copy_iso_headers(ctx, p); | ||
2729 | 2745 | ||
2730 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { | 2746 | if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) |
2731 | ir_header = (__le32 *) p; | 2747 | flush_iso_completions(ctx); |
2732 | ctx->base.callback.sc(&ctx->base, | ||
2733 | le32_to_cpu(ir_header[0]) & 0xffff, | ||
2734 | ctx->header_length, ctx->header, | ||
2735 | ctx->base.callback_data); | ||
2736 | ctx->header_length = 0; | ||
2737 | } | ||
2738 | 2748 | ||
2739 | return 1; | 2749 | return 1; |
2740 | } | 2750 | } |
@@ -2746,29 +2756,51 @@ static int handle_ir_buffer_fill(struct context *context, | |||
2746 | { | 2756 | { |
2747 | struct iso_context *ctx = | 2757 | struct iso_context *ctx = |
2748 | container_of(context, struct iso_context, context); | 2758 | container_of(context, struct iso_context, context); |
2759 | unsigned int req_count, res_count, completed; | ||
2749 | u32 buffer_dma; | 2760 | u32 buffer_dma; |
2750 | 2761 | ||
2751 | if (!last->transfer_status) | 2762 | req_count = le16_to_cpu(last->req_count); |
2763 | res_count = le16_to_cpu(ACCESS_ONCE(last->res_count)); | ||
2764 | completed = req_count - res_count; | ||
2765 | buffer_dma = le32_to_cpu(last->data_address); | ||
2766 | |||
2767 | if (completed > 0) { | ||
2768 | ctx->mc_buffer_bus = buffer_dma; | ||
2769 | ctx->mc_completed = completed; | ||
2770 | } | ||
2771 | |||
2772 | if (res_count != 0) | ||
2752 | /* Descriptor(s) not done yet, stop iteration */ | 2773 | /* Descriptor(s) not done yet, stop iteration */ |
2753 | return 0; | 2774 | return 0; |
2754 | 2775 | ||
2755 | buffer_dma = le32_to_cpu(last->data_address); | ||
2756 | dma_sync_single_range_for_cpu(context->ohci->card.device, | 2776 | dma_sync_single_range_for_cpu(context->ohci->card.device, |
2757 | buffer_dma & PAGE_MASK, | 2777 | buffer_dma & PAGE_MASK, |
2758 | buffer_dma & ~PAGE_MASK, | 2778 | buffer_dma & ~PAGE_MASK, |
2759 | le16_to_cpu(last->req_count), | 2779 | completed, DMA_FROM_DEVICE); |
2760 | DMA_FROM_DEVICE); | ||
2761 | 2780 | ||
2762 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) | 2781 | if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { |
2763 | ctx->base.callback.mc(&ctx->base, | 2782 | ctx->base.callback.mc(&ctx->base, |
2764 | le32_to_cpu(last->data_address) + | 2783 | buffer_dma + completed, |
2765 | le16_to_cpu(last->req_count) - | ||
2766 | le16_to_cpu(last->res_count), | ||
2767 | ctx->base.callback_data); | 2784 | ctx->base.callback_data); |
2785 | ctx->mc_completed = 0; | ||
2786 | } | ||
2768 | 2787 | ||
2769 | return 1; | 2788 | return 1; |
2770 | } | 2789 | } |
2771 | 2790 | ||
2791 | static void flush_ir_buffer_fill(struct iso_context *ctx) | ||
2792 | { | ||
2793 | dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, | ||
2794 | ctx->mc_buffer_bus & PAGE_MASK, | ||
2795 | ctx->mc_buffer_bus & ~PAGE_MASK, | ||
2796 | ctx->mc_completed, DMA_FROM_DEVICE); | ||
2797 | |||
2798 | ctx->base.callback.mc(&ctx->base, | ||
2799 | ctx->mc_buffer_bus + ctx->mc_completed, | ||
2800 | ctx->base.callback_data); | ||
2801 | ctx->mc_completed = 0; | ||
2802 | } | ||
2803 | |||
2772 | static inline void sync_it_packet_for_cpu(struct context *context, | 2804 | static inline void sync_it_packet_for_cpu(struct context *context, |
2773 | struct descriptor *pd) | 2805 | struct descriptor *pd) |
2774 | { | 2806 | { |
@@ -2812,8 +2844,8 @@ static int handle_it_packet(struct context *context, | |||
2812 | { | 2844 | { |
2813 | struct iso_context *ctx = | 2845 | struct iso_context *ctx = |
2814 | container_of(context, struct iso_context, context); | 2846 | container_of(context, struct iso_context, context); |
2815 | int i; | ||
2816 | struct descriptor *pd; | 2847 | struct descriptor *pd; |
2848 | __be32 *ctx_hdr; | ||
2817 | 2849 | ||
2818 | for (pd = d; pd <= last; pd++) | 2850 | for (pd = d; pd <= last; pd++) |
2819 | if (pd->transfer_status) | 2851 | if (pd->transfer_status) |
@@ -2824,20 +2856,19 @@ static int handle_it_packet(struct context *context, | |||
2824 | 2856 | ||
2825 | sync_it_packet_for_cpu(context, d); | 2857 | sync_it_packet_for_cpu(context, d); |
2826 | 2858 | ||
2827 | i = ctx->header_length; | 2859 | if (ctx->header_length + 4 > PAGE_SIZE) |
2828 | if (i + 4 < PAGE_SIZE) { | 2860 | flush_iso_completions(ctx); |
2829 | /* Present this value as big-endian to match the receive code */ | 2861 | |
2830 | *(__be32 *)(ctx->header + i) = cpu_to_be32( | 2862 | ctx_hdr = ctx->header + ctx->header_length; |
2831 | ((u32)le16_to_cpu(pd->transfer_status) << 16) | | 2863 | ctx->last_timestamp = le16_to_cpu(last->res_count); |
2832 | le16_to_cpu(pd->res_count)); | 2864 | /* Present this value as big-endian to match the receive code */ |
2833 | ctx->header_length += 4; | 2865 | *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | |
2834 | } | 2866 | le16_to_cpu(pd->res_count)); |
2835 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { | 2867 | ctx->header_length += 4; |
2836 | ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count), | 2868 | |
2837 | ctx->header_length, ctx->header, | 2869 | if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) |
2838 | ctx->base.callback_data); | 2870 | flush_iso_completions(ctx); |
2839 | ctx->header_length = 0; | 2871 | |
2840 | } | ||
2841 | return 1; | 2872 | return 1; |
2842 | } | 2873 | } |
2843 | 2874 | ||
@@ -2924,8 +2955,10 @@ static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, | |||
2924 | if (ret < 0) | 2955 | if (ret < 0) |
2925 | goto out_with_header; | 2956 | goto out_with_header; |
2926 | 2957 | ||
2927 | if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) | 2958 | if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { |
2928 | set_multichannel_mask(ohci, 0); | 2959 | set_multichannel_mask(ohci, 0); |
2960 | ctx->mc_completed = 0; | ||
2961 | } | ||
2929 | 2962 | ||
2930 | return &ctx->base; | 2963 | return &ctx->base; |
2931 | 2964 | ||
@@ -3387,6 +3420,39 @@ static void ohci_flush_queue_iso(struct fw_iso_context *base) | |||
3387 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); | 3420 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
3388 | } | 3421 | } |
3389 | 3422 | ||
3423 | static int ohci_flush_iso_completions(struct fw_iso_context *base) | ||
3424 | { | ||
3425 | struct iso_context *ctx = container_of(base, struct iso_context, base); | ||
3426 | int ret = 0; | ||
3427 | |||
3428 | tasklet_disable(&ctx->context.tasklet); | ||
3429 | |||
3430 | if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { | ||
3431 | context_tasklet((unsigned long)&ctx->context); | ||
3432 | |||
3433 | switch (base->type) { | ||
3434 | case FW_ISO_CONTEXT_TRANSMIT: | ||
3435 | case FW_ISO_CONTEXT_RECEIVE: | ||
3436 | if (ctx->header_length != 0) | ||
3437 | flush_iso_completions(ctx); | ||
3438 | break; | ||
3439 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: | ||
3440 | if (ctx->mc_completed != 0) | ||
3441 | flush_ir_buffer_fill(ctx); | ||
3442 | break; | ||
3443 | default: | ||
3444 | ret = -ENOSYS; | ||
3445 | } | ||
3446 | |||
3447 | clear_bit_unlock(0, &ctx->flushing_completions); | ||
3448 | smp_mb__after_clear_bit(); | ||
3449 | } | ||
3450 | |||
3451 | tasklet_enable(&ctx->context.tasklet); | ||
3452 | |||
3453 | return ret; | ||
3454 | } | ||
3455 | |||
3390 | static const struct fw_card_driver ohci_driver = { | 3456 | static const struct fw_card_driver ohci_driver = { |
3391 | .enable = ohci_enable, | 3457 | .enable = ohci_enable, |
3392 | .read_phy_reg = ohci_read_phy_reg, | 3458 | .read_phy_reg = ohci_read_phy_reg, |
@@ -3404,6 +3470,7 @@ static const struct fw_card_driver ohci_driver = { | |||
3404 | .set_iso_channels = ohci_set_iso_channels, | 3470 | .set_iso_channels = ohci_set_iso_channels, |
3405 | .queue_iso = ohci_queue_iso, | 3471 | .queue_iso = ohci_queue_iso, |
3406 | .flush_queue_iso = ohci_flush_queue_iso, | 3472 | .flush_queue_iso = ohci_flush_queue_iso, |
3473 | .flush_iso_completions = ohci_flush_iso_completions, | ||
3407 | .start_iso = ohci_start_iso, | 3474 | .start_iso = ohci_start_iso, |
3408 | .stop_iso = ohci_stop_iso, | 3475 | .stop_iso = ohci_stop_iso, |
3409 | }; | 3476 | }; |
@@ -3463,7 +3530,7 @@ static int __devinit pci_probe(struct pci_dev *dev, | |||
3463 | 3530 | ||
3464 | err = pci_enable_device(dev); | 3531 | err = pci_enable_device(dev); |
3465 | if (err) { | 3532 | if (err) { |
3466 | fw_error("Failed to enable OHCI hardware\n"); | 3533 | dev_err(&dev->dev, "failed to enable OHCI hardware\n"); |
3467 | goto fail_free; | 3534 | goto fail_free; |
3468 | } | 3535 | } |
3469 | 3536 | ||
@@ -3478,13 +3545,13 @@ static int __devinit pci_probe(struct pci_dev *dev, | |||
3478 | 3545 | ||
3479 | err = pci_request_region(dev, 0, ohci_driver_name); | 3546 | err = pci_request_region(dev, 0, ohci_driver_name); |
3480 | if (err) { | 3547 | if (err) { |
3481 | fw_error("MMIO resource unavailable\n"); | 3548 | dev_err(&dev->dev, "MMIO resource unavailable\n"); |
3482 | goto fail_disable; | 3549 | goto fail_disable; |
3483 | } | 3550 | } |
3484 | 3551 | ||
3485 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | 3552 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); |
3486 | if (ohci->registers == NULL) { | 3553 | if (ohci->registers == NULL) { |
3487 | fw_error("Failed to remap registers\n"); | 3554 | dev_err(&dev->dev, "failed to remap registers\n"); |
3488 | err = -ENXIO; | 3555 | err = -ENXIO; |
3489 | goto fail_iomem; | 3556 | goto fail_iomem; |
3490 | } | 3557 | } |
@@ -3573,9 +3640,10 @@ static int __devinit pci_probe(struct pci_dev *dev, | |||
3573 | goto fail_contexts; | 3640 | goto fail_contexts; |
3574 | 3641 | ||
3575 | version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; | 3642 | version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
3576 | fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " | 3643 | dev_notice(&dev->dev, |
3644 | "added OHCI v%x.%x device as card %d, " | ||
3577 | "%d IR + %d IT contexts, quirks 0x%x\n", | 3645 | "%d IR + %d IT contexts, quirks 0x%x\n", |
3578 | dev_name(&dev->dev), version >> 16, version & 0xff, | 3646 | version >> 16, version & 0xff, ohci->card.index, |
3579 | ohci->n_ir, ohci->n_it, ohci->quirks); | 3647 | ohci->n_ir, ohci->n_it, ohci->quirks); |
3580 | 3648 | ||
3581 | return 0; | 3649 | return 0; |
@@ -3604,7 +3672,7 @@ static int __devinit pci_probe(struct pci_dev *dev, | |||
3604 | pmac_ohci_off(dev); | 3672 | pmac_ohci_off(dev); |
3605 | fail: | 3673 | fail: |
3606 | if (err == -ENOMEM) | 3674 | if (err == -ENOMEM) |
3607 | fw_error("Out of memory\n"); | 3675 | dev_err(&dev->dev, "out of memory\n"); |
3608 | 3676 | ||
3609 | return err; | 3677 | return err; |
3610 | } | 3678 | } |
@@ -3648,7 +3716,7 @@ static void pci_remove(struct pci_dev *dev) | |||
3648 | kfree(ohci); | 3716 | kfree(ohci); |
3649 | pmac_ohci_off(dev); | 3717 | pmac_ohci_off(dev); |
3650 | 3718 | ||
3651 | fw_notify("Removed fw-ohci device.\n"); | 3719 | dev_notice(&dev->dev, "removed fw-ohci device\n"); |
3652 | } | 3720 | } |
3653 | 3721 | ||
3654 | #ifdef CONFIG_PM | 3722 | #ifdef CONFIG_PM |
@@ -3662,12 +3730,12 @@ static int pci_suspend(struct pci_dev *dev, pm_message_t state) | |||
3662 | pci_disable_msi(dev); | 3730 | pci_disable_msi(dev); |
3663 | err = pci_save_state(dev); | 3731 | err = pci_save_state(dev); |
3664 | if (err) { | 3732 | if (err) { |
3665 | fw_error("pci_save_state failed\n"); | 3733 | dev_err(&dev->dev, "pci_save_state failed\n"); |
3666 | return err; | 3734 | return err; |
3667 | } | 3735 | } |
3668 | err = pci_set_power_state(dev, pci_choose_state(dev, state)); | 3736 | err = pci_set_power_state(dev, pci_choose_state(dev, state)); |
3669 | if (err) | 3737 | if (err) |
3670 | fw_error("pci_set_power_state failed with %d\n", err); | 3738 | dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err); |
3671 | pmac_ohci_off(dev); | 3739 | pmac_ohci_off(dev); |
3672 | 3740 | ||
3673 | return 0; | 3741 | return 0; |
@@ -3683,7 +3751,7 @@ static int pci_resume(struct pci_dev *dev) | |||
3683 | pci_restore_state(dev); | 3751 | pci_restore_state(dev); |
3684 | err = pci_enable_device(dev); | 3752 | err = pci_enable_device(dev); |
3685 | if (err) { | 3753 | if (err) { |
3686 | fw_error("pci_enable_device failed\n"); | 3754 | dev_err(&dev->dev, "pci_enable_device failed\n"); |
3687 | return err; | 3755 | return err; |
3688 | } | 3756 | } |
3689 | 3757 | ||