1 files changed, 123 insertions, 241 deletions

diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 43ebf337b131..75dc6988cffd 100644
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
@@ -38,7 +38,6 @@
 #include <linux/spinlock.h>
 #include <linux/string.h>
 
-#include <asm/atomic.h>
 #include <asm/byteorder.h>
 #include <asm/page.h>
 #include <asm/system.h>
@@ -73,20 +72,6 @@ struct descriptor {
         __le16 transfer_status;
 } __attribute__((aligned(16)));
 
-struct db_descriptor {
-        __le16 first_size;
-        __le16 control;
-        __le16 second_req_count;
-        __le16 first_req_count;
-        __le32 branch_address;
-        __le16 second_res_count;
-        __le16 first_res_count;
-        __le32 reserved0;
-        __le32 first_buffer;
-        __le32 second_buffer;
-        __le32 reserved1;
-} __attribute__((aligned(16)));
-
 #define CONTROL_SET(regs)       (regs)
 #define CONTROL_CLEAR(regs)     ((regs) + 4)
 #define COMMAND_PTR(regs)       ((regs) + 12)
@@ -181,31 +166,16 @@ struct fw_ohci {
         struct fw_card card;
 
         __iomem char *registers;
-        dma_addr_t self_id_bus;
-        __le32 *self_id_cpu;
-        struct tasklet_struct bus_reset_tasklet;
         int node_id;
         int generation;
         int request_generation; /* for timestamping incoming requests */
-        atomic_t bus_seconds;
-
-        bool use_dualbuffer;
-        bool old_uninorth;
-        bool bus_reset_packet_quirk;
+        unsigned quirks;
 
         /*
          * Spinlock for accessing fw_ohci data.  Never call out of
          * this driver with this lock held.
          */
         spinlock_t lock;
-        u32 self_id_buffer[512];
-
-        /* Config rom buffers */
-        __be32 *config_rom;
-        dma_addr_t config_rom_bus;
-        __be32 *next_config_rom;
-        dma_addr_t next_config_rom_bus;
-        __be32 next_header;
 
         struct ar_context ar_request_ctx;
         struct ar_context ar_response_ctx;
@@ -217,6 +187,18 @@ struct fw_ohci {
         u64 ir_context_channels;
         u32 ir_context_mask;
         struct iso_context *ir_context_list;
+
+        __be32    *config_rom;
+        dma_addr_t config_rom_bus;
+        __be32    *next_config_rom;
+        dma_addr_t next_config_rom_bus;
+        __be32     next_header;
+
+        __le32    *self_id_cpu;
+        dma_addr_t self_id_bus;
+        struct tasklet_struct bus_reset_tasklet;
+
+        u32 self_id_buffer[512];
 };
 
 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
@@ -249,6 +231,30 @@ static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 
 static char ohci_driver_name[] = KBUILD_MODNAME;
 
+#define QUIRK_CYCLE_TIMER               1
+#define QUIRK_RESET_PACKET              2
+#define QUIRK_BE_HEADERS                4
+
+/* In case of multiple matches in ohci_quirks[], only the first one is used. */
+static const struct {
+        unsigned short vendor, device, flags;
+} ohci_quirks[] = {
+        {PCI_VENDOR_ID_TI,      PCI_ANY_ID,     QUIRK_RESET_PACKET},
+        {PCI_VENDOR_ID_AL,      PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
+        {PCI_VENDOR_ID_NEC,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
+        {PCI_VENDOR_ID_VIA,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
+        {PCI_VENDOR_ID_APPLE,   PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
+};
+
+/* This overrides anything that was found in ohci_quirks[]. */
+static int param_quirks;
+module_param_named(quirks, param_quirks, int, 0644);
+MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
+        ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
+        ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
+        ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
+        ")");
+
 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 
 #define OHCI_PARAM_DEBUG_AT_AR          1
@@ -275,7 +281,7 @@ static void log_irqs(u32 evt)
             !(evt & OHCI1394_busReset))
                 return;
 
-        fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
+        fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
@@ -285,7 +291,6 @@ static void log_irqs(u32 evt)
             evt & OHCI1394_isochTx              ? " IT"                 : "",
             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
-            evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
             evt & OHCI1394_busReset             ? " busReset"           : "",
@@ -293,8 +298,7 @@ static void log_irqs(u32 evt)
                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
                     OHCI1394_respTxComplete | OHCI1394_isochRx |
                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
-                    OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
-                    OHCI1394_cycleInconsistent |
+                    OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
                     OHCI1394_regAccessFail | OHCI1394_busReset)
                                                 ? " ?"                  : "");
 }
@@ -524,7 +528,7 @@ static void ar_context_release(struct ar_context *ctx)
 
 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 #define cond_le32_to_cpu(v) \
-        (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
+        (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 #else
 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 #endif
@@ -605,7 +609,7 @@ static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
          * at a slightly incorrect time (in bus_reset_tasklet).
          */
         if (evt == OHCI1394_evt_bus_reset) {
-                if (!ohci->bus_reset_packet_quirk)
+                if (!(ohci->quirks & QUIRK_RESET_PACKET))
                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
         } else if (ctx == &ohci->ar_request_ctx) {
                 fw_core_handle_request(&ohci->card, &p);
@@ -1329,7 +1333,7 @@ static void bus_reset_tasklet(unsigned long data)
         context_stop(&ohci->at_response_ctx);
         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
 
-        if (ohci->bus_reset_packet_quirk)
+        if (ohci->quirks & QUIRK_RESET_PACKET)
                 ohci->request_generation = generation;
 
         /*
@@ -1384,7 +1388,7 @@ static void bus_reset_tasklet(unsigned long data)
 static irqreturn_t irq_handler(int irq, void *data)
 {
         struct fw_ohci *ohci = data;
-        u32 event, iso_event, cycle_time;
+        u32 event, iso_event;
         int i;
 
         event = reg_read(ohci, OHCI1394_IntEventClear);
@@ -1454,12 +1458,6 @@ static irqreturn_t irq_handler(int irq, void *data)
                         fw_notify("isochronous cycle inconsistent\n");
         }
 
-        if (event & OHCI1394_cycle64Seconds) {
-                cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
-                if ((cycle_time & 0x80000000) == 0)
-                        atomic_inc(&ohci->bus_seconds);
-        }
-
         return IRQ_HANDLED;
 }
 
@@ -1553,8 +1551,7 @@ static int ohci_enable(struct fw_card *card,
                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
                   OHCI1394_isochRx | OHCI1394_isochTx |
                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
-                  OHCI1394_cycleInconsistent |
-                  OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
+                  OHCI1394_cycleInconsistent | OHCI1394_regAccessFail |
                   OHCI1394_masterIntEnable);
         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
@@ -1794,16 +1791,61 @@ static int ohci_enable_phys_dma(struct fw_card *card,
 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
 }
 
-static u64 ohci_get_bus_time(struct fw_card *card)
+static u32 cycle_timer_ticks(u32 cycle_timer)
 {
-        struct fw_ohci *ohci = fw_ohci(card);
-        u32 cycle_time;
-        u64 bus_time;
+        u32 ticks;
 
-        cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
-        bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
+        ticks = cycle_timer & 0xfff;
+        ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
+        ticks += (3072 * 8000) * (cycle_timer >> 25);
+
+        return ticks;
+}
+
+/*
+ * Some controllers exhibit one or more of the following bugs when updating the
+ * iso cycle timer register:
+ *  - When the lowest six bits are wrapping around to zero, a read that happens
+ *    at the same time will return garbage in the lowest ten bits.
+ *  - When the cycleOffset field wraps around to zero, the cycleCount field is
+ *    not incremented for about 60 ns.
+ *  - Occasionally, the entire register reads zero.
+ *
+ * To catch these, we read the register three times and ensure that the
+ * difference between each two consecutive reads is approximately the same, i.e.
+ * less than twice the other.  Furthermore, any negative difference indicates an
+ * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
+ * execute, so we have enough precision to compute the ratio of the differences.)
+ */
+static u32 ohci_get_cycle_time(struct fw_card *card)
+{
+        struct fw_ohci *ohci = fw_ohci(card);
+        u32 c0, c1, c2;
+        u32 t0, t1, t2;
+        s32 diff01, diff12;
+        int i;
 
-        return bus_time;
+        c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
+
+        if (ohci->quirks & QUIRK_CYCLE_TIMER) {
+                i = 0;
+                c1 = c2;
+                c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
+                do {
+                        c0 = c1;
+                        c1 = c2;
+                        c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
+                        t0 = cycle_timer_ticks(c0);
+                        t1 = cycle_timer_ticks(c1);
+                        t2 = cycle_timer_ticks(c2);
+                        diff01 = t1 - t0;
+                        diff12 = t2 - t1;
+                } while ((diff01 <= 0 || diff12 <= 0 ||
+                          diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
+                         && i++ < 20);
+        }
+
+        return c2;
 }
 
 static void copy_iso_headers(struct iso_context *ctx, void *p)
@@ -1828,52 +1870,6 @@ static void copy_iso_headers(struct iso_context *ctx, void *p)
         ctx->header_length += ctx->base.header_size;
 }
 
-static int handle_ir_dualbuffer_packet(struct context *context,
-                                       struct descriptor *d,
-                                       struct descriptor *last)
-{
-        struct iso_context *ctx =
-                container_of(context, struct iso_context, context);
-        struct db_descriptor *db = (struct db_descriptor *) d;
-        __le32 *ir_header;
-        size_t header_length;
-        void *p, *end;
-
-        if (db->first_res_count != 0 && db->second_res_count != 0) {
-                if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
-                        /* This descriptor isn't done yet, stop iteration. */
-                        return 0;
-                }
-                ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
-        }
-
-        header_length = le16_to_cpu(db->first_req_count) -
-                le16_to_cpu(db->first_res_count);
-
-        p = db + 1;
-        end = p + header_length;
-        while (p < end) {
-                copy_iso_headers(ctx, p);
-                ctx->excess_bytes +=
-                        (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
-                p += max(ctx->base.header_size, (size_t)8);
-        }
-
-        ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
-                le16_to_cpu(db->second_res_count);
-
-        if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
-                ir_header = (__le32 *) (db + 1);
-                ctx->base.callback(&ctx->base,
-                                   le32_to_cpu(ir_header[0]) & 0xffff,
-                                   ctx->header_length, ctx->header,
-                                   ctx->base.callback_data);
-                ctx->header_length = 0;
-        }
-
-        return 1;
-}
-
 static int handle_ir_packet_per_buffer(struct context *context,
                                        struct descriptor *d,
                                        struct descriptor *last)
@@ -1960,10 +1956,7 @@ static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
                 channels = &ohci->ir_context_channels;
                 mask = &ohci->ir_context_mask;
                 list = ohci->ir_context_list;
-                if (ohci->use_dualbuffer)
-                        callback = handle_ir_dualbuffer_packet;
-                else
-                        callback = handle_ir_packet_per_buffer;
+                callback = handle_ir_packet_per_buffer;
         }
 
         spin_lock_irqsave(&ohci->lock, flags);
@@ -2026,8 +2019,6 @@ static int ohci_start_iso(struct fw_iso_context *base,
         } else {
                 index = ctx - ohci->ir_context_list;
                 control = IR_CONTEXT_ISOCH_HEADER;
-                if (ohci->use_dualbuffer)
-                        control |= IR_CONTEXT_DUAL_BUFFER_MODE;
                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
                 if (cycle >= 0) {
                         match |= (cycle & 0x07fff) << 12;
@@ -2188,92 +2179,6 @@ static int ohci_queue_iso_transmit(struct fw_iso_context *base,
         return 0;
 }
 
-static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
-                                             struct fw_iso_packet *packet,
-                                             struct fw_iso_buffer *buffer,
-                                             unsigned long payload)
-{
-        struct iso_context *ctx = container_of(base, struct iso_context, base);
-        struct db_descriptor *db = NULL;
-        struct descriptor *d;
-        struct fw_iso_packet *p;
-        dma_addr_t d_bus, page_bus;
-        u32 z, header_z, length, rest;
-        int page, offset, packet_count, header_size;
-
-        /*
-         * FIXME: Cycle lost behavior should be configurable: lose
-         * packet, retransmit or terminate..
-         */
-
-        p = packet;
-        z = 2;
-
-        /*
-         * The OHCI controller puts the isochronous header and trailer in the
-         * buffer, so we need at least 8 bytes.
-         */
-        packet_count = p->header_length / ctx->base.header_size;
-        header_size = packet_count * max(ctx->base.header_size, (size_t)8);
-
-        /* Get header size in number of descriptors. */
-        header_z = DIV_ROUND_UP(header_size, sizeof(*d));
-        page     = payload >> PAGE_SHIFT;
-        offset   = payload & ~PAGE_MASK;
-        rest     = p->payload_length;
-        /*
-         * The controllers I've tested have not worked correctly when
-         * second_req_count is zero.  Rather than do something we know won't
-         * work, return an error
-         */
-        if (rest == 0)
-                return -EINVAL;
-
-        while (rest > 0) {
-                d = context_get_descriptors(&ctx->context,
-                                            z + header_z, &d_bus);
-                if (d == NULL)
-                        return -ENOMEM;
-
-                db = (struct db_descriptor *) d;
-                db->control = cpu_to_le16(DESCRIPTOR_STATUS |
-                                          DESCRIPTOR_BRANCH_ALWAYS);
-                db->first_size =
-                    cpu_to_le16(max(ctx->base.header_size, (size_t)8));
-                if (p->skip && rest == p->payload_length) {
-                        db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
-                        db->first_req_count = db->first_size;
-                } else {
-                        db->first_req_count = cpu_to_le16(header_size);
-                }
-                db->first_res_count = db->first_req_count;
-                db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
-
-                if (p->skip && rest == p->payload_length)
-                        length = 4;
-                else if (offset + rest < PAGE_SIZE)
-                        length = rest;
-                else
-                        length = PAGE_SIZE - offset;
-
-                db->second_req_count = cpu_to_le16(length);
-                db->second_res_count = db->second_req_count;
-                page_bus = page_private(buffer->pages[page]);
-                db->second_buffer = cpu_to_le32(page_bus + offset);
-
-                if (p->interrupt && length == rest)
-                        db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
-
-                context_append(&ctx->context, d, z, header_z);
-                offset = (offset + length) & ~PAGE_MASK;
-                rest -= length;
-                if (offset == 0)
-                        page++;
-        }
-
-        return 0;
-}
-
 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
                                         struct fw_iso_packet *packet,
                                         struct fw_iso_buffer *buffer,
@@ -2364,9 +2269,6 @@ static int ohci_queue_iso(struct fw_iso_context *base,
         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
                 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
-        else if (ctx->context.ohci->use_dualbuffer)
-                ret = ohci_queue_iso_receive_dualbuffer(base, packet,
-                                                        buffer, payload);
         else
                 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
                                                         buffer, payload);
@@ -2383,7 +2285,7 @@ static const struct fw_card_driver ohci_driver = {
         .send_response          = ohci_send_response,
         .cancel_packet          = ohci_cancel_packet,
         .enable_phys_dma        = ohci_enable_phys_dma,
-        .get_bus_time           = ohci_get_bus_time,
+        .get_cycle_time         = ohci_get_cycle_time,
 
         .allocate_iso_context   = ohci_allocate_iso_context,
         .free_iso_context       = ohci_free_iso_context,
@@ -2421,17 +2323,13 @@ static void ohci_pmac_off(struct pci_dev *dev)
 #define ohci_pmac_off(dev)
 #endif /* CONFIG_PPC_PMAC */
 
-#define PCI_VENDOR_ID_AGERE             PCI_VENDOR_ID_ATT
-#define PCI_DEVICE_ID_AGERE_FW643       0x5901
-#define PCI_DEVICE_ID_TI_TSB43AB23      0x8024
-
 static int __devinit pci_probe(struct pci_dev *dev,
                                const struct pci_device_id *ent)
 {
         struct fw_ohci *ohci;
         u32 bus_options, max_receive, link_speed, version;
         u64 guid;
-        int err;
+        int i, err, n_ir, n_it;
         size_t size;
 
         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
@@ -2472,36 +2370,15 @@ static int __devinit pci_probe(struct pci_dev *dev,
                 goto fail_iomem;
         }
 
-        version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
-#if 0
-        /* FIXME: make it a context option or remove dual-buffer mode */
-        ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
-#endif
-
-        /* dual-buffer mode is broken if more than one IR context is active */
-        if (dev->vendor == PCI_VENDOR_ID_AGERE &&
-            dev->device == PCI_DEVICE_ID_AGERE_FW643)
-                ohci->use_dualbuffer = false;
-
-        /* dual-buffer mode is broken */
-        if (dev->vendor == PCI_VENDOR_ID_RICOH &&
-            dev->device == PCI_DEVICE_ID_RICOH_R5C832)
-                ohci->use_dualbuffer = false;
-
-/* x86-32 currently doesn't use highmem for dma_alloc_coherent */
-#if !defined(CONFIG_X86_32)
-        /* dual-buffer mode is broken with descriptor addresses above 2G */
-        if (dev->vendor == PCI_VENDOR_ID_TI &&
-            (dev->device == PCI_DEVICE_ID_TI_TSB43AB22 ||
-             dev->device == PCI_DEVICE_ID_TI_TSB43AB23))
-                ohci->use_dualbuffer = false;
-#endif
-
-#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
-        ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
-                             dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
-#endif
-        ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
+        for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
+                if (ohci_quirks[i].vendor == dev->vendor &&
+                    (ohci_quirks[i].device == dev->device ||
+                     ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
+                        ohci->quirks = ohci_quirks[i].flags;
+                        break;
+                }
+        if (param_quirks)
+                ohci->quirks = param_quirks;
 
         ar_context_init(&ohci->ar_request_ctx, ohci,
                         OHCI1394_AsReqRcvContextControlSet);
@@ -2516,17 +2393,19 @@ static int __devinit pci_probe(struct pci_dev *dev,
                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
 
         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
-        ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
+        ohci->ir_context_channels = ~0ULL;
+        ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
-        size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
-        ohci->it_context_list = kzalloc(size, GFP_KERNEL);
+        n_ir = hweight32(ohci->ir_context_mask);
+        size = sizeof(struct iso_context) * n_ir;
+        ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
 
         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
-        ohci->ir_context_channels = ~0ULL;
-        ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
+        ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
-        size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
-        ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
+        n_it = hweight32(ohci->it_context_mask);
+        size = sizeof(struct iso_context) * n_it;
+        ohci->it_context_list = kzalloc(size, GFP_KERNEL);
 
         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
                 err = -ENOMEM;
@@ -2553,8 +2432,11 @@ static int __devinit pci_probe(struct pci_dev *dev,
         if (err)
                 goto fail_self_id;
 
-        fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
-                  dev_name(&dev->dev), version >> 16, version & 0xff);
+        version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
+        fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
+                  "%d IR + %d IT contexts, quirks 0x%x\n",
+                  dev_name(&dev->dev), version >> 16, version & 0xff,
+                  n_ir, n_it, ohci->quirks);
 
         return 0;
 
@@ -2662,7 +2544,7 @@ static int pci_resume(struct pci_dev *dev)
 }
 #endif
 
-static struct pci_device_id pci_table[] = {
+static const struct pci_device_id pci_table[] = {
         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
         { }
 };