diff options
Diffstat (limited to 'drivers/edac')
-rw-r--r-- | drivers/edac/amd64_edac.c | 25 | ||||
-rw-r--r-- | drivers/edac/amd64_edac.h | 2 | ||||
-rw-r--r-- | drivers/edac/edac_core.h | 4 | ||||
-rw-r--r-- | drivers/edac/edac_mc_sysfs.c | 4 | ||||
-rw-r--r-- | drivers/edac/mpc85xx_edac.c | 6 | ||||
-rw-r--r-- | drivers/edac/mpc85xx_edac.h | 1 |
6 files changed, 30 insertions, 12 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index c36bf40568cf..858fe6037223 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c | |||
@@ -754,13 +754,13 @@ static void amd64_cpu_display_info(struct amd64_pvt *pvt) | |||
754 | static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) | 754 | static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) |
755 | { | 755 | { |
756 | int bit; | 756 | int bit; |
757 | enum dev_type edac_cap = EDAC_NONE; | 757 | enum dev_type edac_cap = EDAC_FLAG_NONE; |
758 | 758 | ||
759 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F) | 759 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F) |
760 | ? 19 | 760 | ? 19 |
761 | : 17; | 761 | : 17; |
762 | 762 | ||
763 | if (pvt->dclr0 >> BIT(bit)) | 763 | if (pvt->dclr0 & BIT(bit)) |
764 | edac_cap = EDAC_FLAG_SECDED; | 764 | edac_cap = EDAC_FLAG_SECDED; |
765 | 765 | ||
766 | return edac_cap; | 766 | return edac_cap; |
@@ -1269,7 +1269,7 @@ static int f10_early_channel_count(struct amd64_pvt *pvt) | |||
1269 | if (channels == 0) | 1269 | if (channels == 0) |
1270 | channels = 1; | 1270 | channels = 1; |
1271 | 1271 | ||
1272 | debugf0("DIMM count= %d\n", channels); | 1272 | debugf0("MCT channel count: %d\n", channels); |
1273 | 1273 | ||
1274 | return channels; | 1274 | return channels; |
1275 | 1275 | ||
@@ -2966,7 +2966,12 @@ static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) | |||
2966 | " Use of the override can cause " | 2966 | " Use of the override can cause " |
2967 | "unknown side effects.\n"); | 2967 | "unknown side effects.\n"); |
2968 | ret = -ENODEV; | 2968 | ret = -ENODEV; |
2969 | } | 2969 | } else |
2970 | /* | ||
2971 | * enable further driver loading if ECC enable is | ||
2972 | * overridden. | ||
2973 | */ | ||
2974 | ret = 0; | ||
2970 | } else { | 2975 | } else { |
2971 | amd64_printk(KERN_INFO, | 2976 | amd64_printk(KERN_INFO, |
2972 | "ECC is enabled by BIOS, Proceeding " | 2977 | "ECC is enabled by BIOS, Proceeding " |
@@ -3006,7 +3011,6 @@ static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci) | |||
3006 | 3011 | ||
3007 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; | 3012 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; |
3008 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | 3013 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
3009 | mci->edac_cap = EDAC_FLAG_NONE; | ||
3010 | 3014 | ||
3011 | if (pvt->nbcap & K8_NBCAP_SECDED) | 3015 | if (pvt->nbcap & K8_NBCAP_SECDED) |
3012 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; | 3016 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; |
@@ -3052,7 +3056,7 @@ static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl, | |||
3052 | if (!pvt) | 3056 | if (!pvt) |
3053 | goto err_exit; | 3057 | goto err_exit; |
3054 | 3058 | ||
3055 | pvt->mc_node_id = get_mc_node_id_from_pdev(dram_f2_ctl); | 3059 | pvt->mc_node_id = get_node_id(dram_f2_ctl); |
3056 | 3060 | ||
3057 | pvt->dram_f2_ctl = dram_f2_ctl; | 3061 | pvt->dram_f2_ctl = dram_f2_ctl; |
3058 | pvt->ext_model = boot_cpu_data.x86_model >> 4; | 3062 | pvt->ext_model = boot_cpu_data.x86_model >> 4; |
@@ -3179,8 +3183,7 @@ static int __devinit amd64_init_one_instance(struct pci_dev *pdev, | |||
3179 | { | 3183 | { |
3180 | int ret = 0; | 3184 | int ret = 0; |
3181 | 3185 | ||
3182 | debugf0("(MC node=%d,mc_type='%s')\n", | 3186 | debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev), |
3183 | get_mc_node_id_from_pdev(pdev), | ||
3184 | get_amd_family_name(mc_type->driver_data)); | 3187 | get_amd_family_name(mc_type->driver_data)); |
3185 | 3188 | ||
3186 | ret = pci_enable_device(pdev); | 3189 | ret = pci_enable_device(pdev); |
@@ -3319,15 +3322,17 @@ static int __init amd64_edac_init(void) | |||
3319 | 3322 | ||
3320 | err = amd64_init_2nd_stage(pvt_lookup[nb]); | 3323 | err = amd64_init_2nd_stage(pvt_lookup[nb]); |
3321 | if (err) | 3324 | if (err) |
3322 | goto err_exit; | 3325 | goto err_2nd_stage; |
3323 | } | 3326 | } |
3324 | 3327 | ||
3325 | amd64_setup_pci_device(); | 3328 | amd64_setup_pci_device(); |
3326 | 3329 | ||
3327 | return 0; | 3330 | return 0; |
3328 | 3331 | ||
3332 | err_2nd_stage: | ||
3333 | debugf0("2nd stage failed\n"); | ||
3334 | |||
3329 | err_exit: | 3335 | err_exit: |
3330 | debugf0("'finish_setup' stage failed\n"); | ||
3331 | pci_unregister_driver(&amd64_pci_driver); | 3336 | pci_unregister_driver(&amd64_pci_driver); |
3332 | 3337 | ||
3333 | return err; | 3338 | return err; |
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index a159957e167b..ba73015af8e4 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h | |||
@@ -444,7 +444,7 @@ enum { | |||
444 | #define K8_MSR_MC4ADDR 0x0412 | 444 | #define K8_MSR_MC4ADDR 0x0412 |
445 | 445 | ||
446 | /* AMD sets the first MC device at device ID 0x18. */ | 446 | /* AMD sets the first MC device at device ID 0x18. */ |
447 | static inline int get_mc_node_id_from_pdev(struct pci_dev *pdev) | 447 | static inline int get_node_id(struct pci_dev *pdev) |
448 | { | 448 | { |
449 | return PCI_SLOT(pdev->devfn) - 0x18; | 449 | return PCI_SLOT(pdev->devfn) - 0x18; |
450 | } | 450 | } |
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h index 3493c6bdb820..871c13b4c148 100644 --- a/drivers/edac/edac_core.h +++ b/drivers/edac/edac_core.h | |||
@@ -150,6 +150,8 @@ enum mem_type { | |||
150 | MEM_FB_DDR2, /* fully buffered DDR2 */ | 150 | MEM_FB_DDR2, /* fully buffered DDR2 */ |
151 | MEM_RDDR2, /* Registered DDR2 RAM */ | 151 | MEM_RDDR2, /* Registered DDR2 RAM */ |
152 | MEM_XDR, /* Rambus XDR */ | 152 | MEM_XDR, /* Rambus XDR */ |
153 | MEM_DDR3, /* DDR3 RAM */ | ||
154 | MEM_RDDR3, /* Registered DDR3 RAM */ | ||
153 | }; | 155 | }; |
154 | 156 | ||
155 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) | 157 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) |
@@ -167,6 +169,8 @@ enum mem_type { | |||
167 | #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) | 169 | #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) |
168 | #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) | 170 | #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) |
169 | #define MEM_FLAG_XDR BIT(MEM_XDR) | 171 | #define MEM_FLAG_XDR BIT(MEM_XDR) |
172 | #define MEM_FLAG_DDR3 BIT(MEM_DDR3) | ||
173 | #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) | ||
170 | 174 | ||
171 | /* chipset Error Detection and Correction capabilities and mode */ | 175 | /* chipset Error Detection and Correction capabilities and mode */ |
172 | enum edac_type { | 176 | enum edac_type { |
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index ad218fe4942d..e1d4ce083481 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c | |||
@@ -94,7 +94,9 @@ static const char *mem_types[] = { | |||
94 | [MEM_DDR2] = "Unbuffered-DDR2", | 94 | [MEM_DDR2] = "Unbuffered-DDR2", |
95 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | 95 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", |
96 | [MEM_RDDR2] = "Registered-DDR2", | 96 | [MEM_RDDR2] = "Registered-DDR2", |
97 | [MEM_XDR] = "XDR" | 97 | [MEM_XDR] = "XDR", |
98 | [MEM_DDR3] = "Unbuffered-DDR3", | ||
99 | [MEM_RDDR3] = "Registered-DDR3" | ||
98 | }; | 100 | }; |
99 | 101 | ||
100 | static const char *dev_types[] = { | 102 | static const char *dev_types[] = { |
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c index 7c8c2d72916f..3f2ccfc6407c 100644 --- a/drivers/edac/mpc85xx_edac.c +++ b/drivers/edac/mpc85xx_edac.c | |||
@@ -757,6 +757,9 @@ static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) | |||
757 | case DSC_SDTYPE_DDR2: | 757 | case DSC_SDTYPE_DDR2: |
758 | mtype = MEM_RDDR2; | 758 | mtype = MEM_RDDR2; |
759 | break; | 759 | break; |
760 | case DSC_SDTYPE_DDR3: | ||
761 | mtype = MEM_RDDR3; | ||
762 | break; | ||
760 | default: | 763 | default: |
761 | mtype = MEM_UNKNOWN; | 764 | mtype = MEM_UNKNOWN; |
762 | break; | 765 | break; |
@@ -769,6 +772,9 @@ static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) | |||
769 | case DSC_SDTYPE_DDR2: | 772 | case DSC_SDTYPE_DDR2: |
770 | mtype = MEM_DDR2; | 773 | mtype = MEM_DDR2; |
771 | break; | 774 | break; |
775 | case DSC_SDTYPE_DDR3: | ||
776 | mtype = MEM_DDR3; | ||
777 | break; | ||
772 | default: | 778 | default: |
773 | mtype = MEM_UNKNOWN; | 779 | mtype = MEM_UNKNOWN; |
774 | break; | 780 | break; |
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h index 135b3539a030..52432ee7c4b9 100644 --- a/drivers/edac/mpc85xx_edac.h +++ b/drivers/edac/mpc85xx_edac.h | |||
@@ -53,6 +53,7 @@ | |||
53 | 53 | ||
54 | #define DSC_SDTYPE_DDR 0x02000000 | 54 | #define DSC_SDTYPE_DDR 0x02000000 |
55 | #define DSC_SDTYPE_DDR2 0x03000000 | 55 | #define DSC_SDTYPE_DDR2 0x03000000 |
56 | #define DSC_SDTYPE_DDR3 0x07000000 | ||
56 | #define DSC_X32_EN 0x00000020 | 57 | #define DSC_X32_EN 0x00000020 |
57 | 58 | ||
58 | /* Err_Int_En */ | 59 | /* Err_Int_En */ |