21 files changed, 145 insertions, 51 deletions

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index fac1a2002e67..af1a17d42bd7 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -45,7 +45,7 @@ config EDAC_DECODE_MCE
         default y
         ---help---
           Enable this option if you want to decode Machine Check Exceptions
-          occuring on your machine in human-readable form.
+          occurring on your machine in human-readable form.
 
           You should definitely say Y here in case you want to decode MCEs
           which occur really early upon boot, before the module infrastructure
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 31e71c4fc831..9a8bebcf6b17 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -211,8 +211,6 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
 
         scrubval = scrubval & 0x001F;
 
-        amd64_debug("pci-read, sdram scrub control value: %d\n", scrubval);
-
         for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
                 if (scrubrates[i].scrubval == scrubval) {
                         retval = scrubrates[i].bandwidth;
@@ -933,25 +931,74 @@ static int k8_early_channel_count(struct amd64_pvt *pvt)
 /* On F10h and later ErrAddr is MC4_ADDR[47:1] */
 static u64 get_error_address(struct mce *m)
 {
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+        u64 addr;
         u8 start_bit = 1;
         u8 end_bit   = 47;
 
-        if (boot_cpu_data.x86 == 0xf) {
+        if (c->x86 == 0xf) {
                 start_bit = 3;
                 end_bit   = 39;
         }
 
-        return m->addr & GENMASK(start_bit, end_bit);
+        addr = m->addr & GENMASK(start_bit, end_bit);
+
+        /*
+         * Erratum 637 workaround
+         */
+        if (c->x86 == 0x15) {
+                struct amd64_pvt *pvt;
+                u64 cc6_base, tmp_addr;
+                u32 tmp;
+                u8 mce_nid, intlv_en;
+
+                if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
+                        return addr;
+
+                mce_nid = amd_get_nb_id(m->extcpu);
+                pvt     = mcis[mce_nid]->pvt_info;
+
+                amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
+                intlv_en = tmp >> 21 & 0x7;
+
+                /* add [47:27] + 3 trailing bits */
+                cc6_base  = (tmp & GENMASK(0, 20)) << 3;
+
+                /* reverse and add DramIntlvEn */
+                cc6_base |= intlv_en ^ 0x7;
+
+                /* pin at [47:24] */
+                cc6_base <<= 24;
+
+                if (!intlv_en)
+                        return cc6_base | (addr & GENMASK(0, 23));
+
+                amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
+
+                                                        /* faster log2 */
+                tmp_addr  = (addr & GENMASK(12, 23)) << __fls(intlv_en + 1);
+
+                /* OR DramIntlvSel into bits [14:12] */
+                tmp_addr |= (tmp & GENMASK(21, 23)) >> 9;
+
+                /* add remaining [11:0] bits from original MC4_ADDR */
+                tmp_addr |= addr & GENMASK(0, 11);
+
+                return cc6_base | tmp_addr;
+        }
+
+        return addr;
 }
 
 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
 {
+        struct cpuinfo_x86 *c = &boot_cpu_data;
         int off = range << 3;
 
         amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off,  &pvt->ranges[range].base.lo);
         amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
 
-        if (boot_cpu_data.x86 == 0xf)
+        if (c->x86 == 0xf)
                 return;
 
         if (!dram_rw(pvt, range))
@@ -959,6 +1006,31 @@ static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
 
         amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off,  &pvt->ranges[range].base.hi);
         amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
+
+        /* Factor in CC6 save area by reading dst node's limit reg */
+        if (c->x86 == 0x15) {
+                struct pci_dev *f1 = NULL;
+                u8 nid = dram_dst_node(pvt, range);
+                u32 llim;
+
+                f1 = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x18 + nid, 1));
+                if (WARN_ON(!f1))
+                        return;
+
+                amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
+
+                pvt->ranges[range].lim.lo &= GENMASK(0, 15);
+
+                                            /* {[39:27],111b} */
+                pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
+
+                pvt->ranges[range].lim.hi &= GENMASK(0, 7);
+
+                                            /* [47:40] */
+                pvt->ranges[range].lim.hi |= llim >> 13;
+
+                pci_dev_put(f1);
+        }
 }
 
 static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
@@ -1403,12 +1475,8 @@ static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
                 return -EINVAL;
         }
 
-        if (intlv_en &&
-            (intlv_sel != ((sys_addr >> 12) & intlv_en))) {
-                amd64_warn("Botched intlv bits, en: 0x%x, sel: 0x%x\n",
-                           intlv_en, intlv_sel);
+        if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
                 return -EINVAL;
-        }
 
         sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
 
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 11be36a311eb..9a666cb985b2 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -196,6 +196,9 @@
 
 #define DCT_CFG_SEL                     0x10C
 
+#define DRAM_LOCAL_NODE_BASE            0x120
+#define DRAM_LOCAL_NODE_LIM             0x124
+
 #define DRAM_BASE_HI                    0x140
 #define DRAM_LIMIT_HI                   0x144
 
diff --git a/drivers/edac/cpc925_edac.c b/drivers/edac/cpc925_edac.c
index 3400ae34795a..a687a0d16962 100644
--- a/drivers/edac/cpc925_edac.c
+++ b/drivers/edac/cpc925_edac.c
@@ -817,7 +817,7 @@ static void cpc925_del_edac_devices(void)
         }
 }
 
-/* Convert current back-ground scrub rate into byte/sec bandwith */
+/* Convert current back-ground scrub rate into byte/sec bandwidth */
 static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
 {
         struct cpc925_mc_pdata *pdata = mci->pvt_info;
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h
index 3d965347a673..eefa3501916b 100644
--- a/drivers/edac/edac_core.h
+++ b/drivers/edac/edac_core.h
@@ -164,7 +164,7 @@ enum mem_type {
 /* chipset Error Detection and Correction capabilities and mode */
 enum edac_type {
         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
-        EDAC_NONE,              /* Doesnt support ECC */
+        EDAC_NONE,              /* Doesn't support ECC */
         EDAC_RESERVED,          /* Reserved ECC type */
         EDAC_PARITY,            /* Detects parity errors */
         EDAC_EC,                /* Error Checking - no correction */
@@ -233,7 +233,7 @@ enum scrub_type {
  *                      of these in parallel provides 64 bits which is common
  *                      for a memory stick.
  *
- * Memory Stick:        A printed circuit board that agregates multiple
+ * Memory Stick:        A printed circuit board that aggregates multiple
  *                      memory devices in parallel.  This is the atomic
  *                      memory component that is purchaseable by Joe consumer
  *                      and loaded into a memory socket.
@@ -385,7 +385,7 @@ struct mem_ctl_info {
 
         /* Get the current sdram memory scrub rate from the internal
            representation and converts it to the closest matching
-           bandwith in bytes/sec.
+           bandwidth in bytes/sec.
          */
         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
 
@@ -823,7 +823,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
  * There are a limited number of error logging registers that can
  * be exausted.  When all registers are exhausted and an additional
  * error occurs then an error overflow register records that an
- * error occured and the type of error, but doesn't have any
+ * error occurred and the type of error, but doesn't have any
  * further information.  The ce/ue versions make for cleaner
  * reporting logic and function interface - reduces conditional
  * statement clutter and extra function arguments.
diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c
index d5e13c94714f..a7408cf86f37 100644
--- a/drivers/edac/edac_device.c
+++ b/drivers/edac/edac_device.c
@@ -672,7 +672,7 @@ void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
                 block->counters.ce_count++;
         }
 
-        /* Propogate the count up the 'totals' tree */
+        /* Propagate the count up the 'totals' tree */
         instance->counters.ce_count++;
         edac_dev->counters.ce_count++;
 
@@ -718,7 +718,7 @@ void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
                 block->counters.ue_count++;
         }
 
-        /* Propogate the count up the 'totals' tree */
+        /* Propagate the count up the 'totals' tree */
         instance->counters.ue_count++;
         edac_dev->counters.ue_count++;
 
diff --git a/drivers/edac/edac_device_sysfs.c b/drivers/edac/edac_device_sysfs.c
index 400de071cabc..86649df00285 100644
--- a/drivers/edac/edac_device_sysfs.c
+++ b/drivers/edac/edac_device_sysfs.c
@@ -533,7 +533,7 @@ static int edac_device_create_block(struct edac_device_ctl_info *edac_dev,
         memset(&block->kobj, 0, sizeof(struct kobject));
 
         /* bump the main kobject's reference count for this controller
-         * and this instance is dependant on the main
+         * and this instance is dependent on the main
          */
         main_kobj = kobject_get(&edac_dev->kobj);
         if (!main_kobj) {
@@ -635,7 +635,7 @@ static int edac_device_create_instance(struct edac_device_ctl_info *edac_dev,
         instance->ctl = edac_dev;
 
         /* bump the main kobject's reference count for this controller
-         * and this instance is dependant on the main
+         * and this instance is dependent on the main
          */
         main_kobj = kobject_get(&edac_dev->kobj);
         if (!main_kobj) {
diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
index a4e9db2d6524..1d8056049072 100644
--- a/drivers/edac/edac_mc.c
+++ b/drivers/edac/edac_mc.c
@@ -724,7 +724,7 @@ void edac_mc_handle_ce(struct mem_ctl_info *mci,
                  * Some MC's can remap memory so that it is still available
                  * at a different address when PCI devices map into memory.
                  * MC's that can't do this lose the memory where PCI devices
-                 * are mapped.  This mapping is MC dependant and so we call
+                 * are mapped.  This mapping is MC dependent and so we call
                  * back into the MC driver for it to map the MC page to
                  * a physical (CPU) page which can then be mapped to a virtual
                  * page - which can then be scrubbed.
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c
index 73196f7b7229..29ffa350bfbe 100644
--- a/drivers/edac/edac_mc_sysfs.c
+++ b/drivers/edac/edac_mc_sysfs.c
@@ -458,13 +458,13 @@ static ssize_t mci_sdram_scrub_rate_store(struct mem_ctl_info *mci,
                 return -EINVAL;
 
         new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
-        if (new_bw >= 0) {
-                edac_printk(KERN_DEBUG, EDAC_MC, "Scrub rate set to %d\n", new_bw);
-                return count;
+        if (new_bw < 0) {
+                edac_printk(KERN_WARNING, EDAC_MC,
+                            "Error setting scrub rate to: %lu\n", bandwidth);
+                return -EINVAL;
         }
 
-        edac_printk(KERN_DEBUG, EDAC_MC, "Error setting scrub rate to: %lu\n", bandwidth);
-        return -EINVAL;
+        return count;
 }
 
 /*
@@ -483,7 +483,6 @@ static ssize_t mci_sdram_scrub_rate_show(struct mem_ctl_info *mci, char *data)
                 return bandwidth;
         }
 
-        edac_printk(KERN_DEBUG, EDAC_MC, "Read scrub rate: %d\n", bandwidth);
         return sprintf(data, "%d\n", bandwidth);
 }
 
@@ -850,7 +849,7 @@ static void edac_remove_mci_instance_attributes(struct mem_ctl_info *mci,
 
         /*
          * loop if there are attributes and until we hit a NULL entry
-         * Remove first all the atributes
+         * Remove first all the attributes
          */
         while (sysfs_attrib) {
                 debugf4("%s() sysfs_attrib = %p\n",__func__, sysfs_attrib);
diff --git a/drivers/edac/edac_pci_sysfs.c b/drivers/edac/edac_pci_sysfs.c
index 023b01cb5175..495198ad059c 100644
--- a/drivers/edac/edac_pci_sysfs.c
+++ b/drivers/edac/edac_pci_sysfs.c
@@ -352,7 +352,7 @@ static int edac_pci_main_kobj_setup(void)
                 return 0;
 
         /* First time, so create the main kobject and its
-         * controls and atributes
+         * controls and attributes
          */
         edac_class = edac_get_sysfs_class();
         if (edac_class == NULL) {
@@ -551,7 +551,7 @@ static void edac_pci_dev_parity_clear(struct pci_dev *dev)
 /*
  *  PCI Parity polling
  *
- *      Fucntion to retrieve the current parity status
+ *      Function to retrieve the current parity status
  *      and decode it
  *
  */
diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c
index d41f9002da45..aa08497a075a 100644
--- a/drivers/edac/i3200_edac.c
+++ b/drivers/edac/i3200_edac.c
@@ -101,6 +101,19 @@ struct i3200_priv {
 
 static int nr_channels;
 
+#ifndef readq
+static inline __u64 readq(const volatile void __iomem *addr)
+{
+        const volatile u32 __iomem *p = addr;
+        u32 low, high;
+
+        low = readl(p);
+        high = readl(p + 1);
+
+        return low + ((u64)high << 32);
+}
+#endif
+
 static int how_many_channels(struct pci_dev *pdev)
 {
         unsigned char capid0_8b; /* 8th byte of CAPID0 */
diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c
index 3d0b726304fe..4dc3ac25a422 100644
--- a/drivers/edac/i5000_edac.c
+++ b/drivers/edac/i5000_edac.c
@@ -1372,7 +1372,7 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
          * actual number of slots/dimms per channel, we thus utilize the
          * resource as specified by the chipset. Thus, we might have
          * have more DIMMs per channel than actually on the mobo, but this
-         * allows the driver to support upto the chipset max, without
+         * allows the driver to support up to the chipset max, without
          * some fancy mobo determination.
          */
         i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index 0448da0af75d..bcbdeeca48b8 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -11,7 +11,7 @@
  *
  * The intel 5100 has two independent channels. EDAC core currently
  * can not reflect this configuration so instead the chip-select
- * rows for each respective channel are layed out one after another,
+ * rows for each respective channel are laid out one after another,
  * the first half belonging to channel 0, the second half belonging
  * to channel 1.
  */
diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c
index fd362b4c2a8e..74d6ec342afb 100644
--- a/drivers/edac/i5400_edac.c
+++ b/drivers/edac/i5400_edac.c
@@ -648,7 +648,7 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
                 return;
         }
 
-        /* Miscelaneous errors */
+        /* Miscellaneous errors */
         errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
 
         branch = extract_fbdchan_indx(info->ferr_nf_fbd);
@@ -1240,7 +1240,7 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
          * actual number of slots/dimms per channel, we thus utilize the
          * resource as specified by the chipset. Thus, we might have
          * have more DIMMs per channel than actually on the mobo, but this
-         * allows the driver to support upto the chipset max, without
+         * allows the driver to support up to the chipset max, without
          * some fancy mobo determination.
          */
         num_dimms_per_channel = MAX_DIMMS_PER_CHANNEL;
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index ff320c0b9cac..a76fe8366b68 100644
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -1065,7 +1065,7 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
          * actual number of slots/dimms per channel, we thus utilize the
          * resource as specified by the chipset. Thus, we might have
          * have more DIMMs per channel than actually on the mobo, but this
-         * allows the driver to support upto the chipset max, without
+         * allows the driver to support up to the chipset max, without
          * some fancy mobo determination.
          */
         num_dimms_per_channel = MAX_SLOTS;
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 3f320ba5445f..04f1e7ce02b1 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -1772,7 +1772,7 @@ static void i7core_check_error(struct mem_ctl_info *mci)
         /*
          * MCE first step: Copy all mce errors into a temporary buffer
          * We use a double buffering here, to reduce the risk of
-         * loosing an error.
+         * losing an error.
          */
         smp_rmb();
         count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c
index 678405ab04e4..4329d39f902c 100644
--- a/drivers/edac/i82443bxgx_edac.c
+++ b/drivers/edac/i82443bxgx_edac.c
@@ -203,7 +203,7 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
                 row_high_limit = ((u32) drbar << 23);
                 /* find the DRAM Chip Select Base address and mask */
                 debugf1("MC%d: %s: %s() Row=%d, "
-                        "Boundry Address=%#0x, Last = %#0x\n",
+                        "Boundary Address=%#0x, Last = %#0x\n",
                         mci->mc_idx, __FILE__, __func__, index, row_high_limit,
                         row_high_limit_last);
 
@@ -305,7 +305,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
         i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
 
         /* Many BIOSes don't clear error flags on boot, so do this
-         * here, or we get "phantom" errors occuring at module-load
+         * here, or we get "phantom" errors occurring at module-load
          * time. */
         pci_write_bits32(pdev, I82443BXGX_EAP,
                         (I82443BXGX_EAP_OFFSET_SBE |
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
index 733a7e7a8d6f..a4987e03f59e 100644
--- a/drivers/edac/mce_amd_inj.c
+++ b/drivers/edac/mce_amd_inj.c
@@ -90,7 +90,7 @@ static ssize_t edac_inject_bank_store(struct kobject *kobj,
 
         if (value > 5)
                 if (boot_cpu_data.x86 != 0x15 || value > 6) {
-                        printk(KERN_ERR "Non-existant MCE bank: %lu\n", value);
+                        printk(KERN_ERR "Non-existent MCE bank: %lu\n", value);
                         return -EINVAL;
                 }
 
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index ffb5ad080bee..38ab8e2cd7f4 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -1147,13 +1147,14 @@ static struct platform_driver mpc85xx_mc_err_driver = {
 static void __init mpc85xx_mc_clear_rfxe(void *data)
 {
         orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
-        mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
+        mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
 }
 #endif
 
 static int __init mpc85xx_mc_init(void)
 {
         int res = 0;
+        u32 pvr = 0;
 
         printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
                "(C) 2006 Montavista Software\n");
@@ -1183,12 +1184,17 @@ static int __init mpc85xx_mc_init(void)
 #endif
 
 #ifdef CONFIG_FSL_SOC_BOOKE
-        /*
-         * need to clear HID1[RFXE] to disable machine check int
-         * so we can catch it
-         */
-        if (edac_op_state == EDAC_OPSTATE_INT)
-                on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
+        pvr = mfspr(SPRN_PVR);
+
+        if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
+            (PVR_VER(pvr) == PVR_VER_E500V2)) {
+                /*
+                 * need to clear HID1[RFXE] to disable machine check int
+                 * so we can catch it
+                 */
+                if (edac_op_state == EDAC_OPSTATE_INT)
+                        on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
+        }
 #endif
 
         return 0;
@@ -1206,7 +1212,12 @@ static void __exit mpc85xx_mc_restore_hid1(void *data)
 static void __exit mpc85xx_mc_exit(void)
 {
 #ifdef CONFIG_FSL_SOC_BOOKE
-        on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
+        u32 pvr = mfspr(SPRN_PVR);
+
+        if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
+            (PVR_VER(pvr) == PVR_VER_E500V2)) {
+                on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
+        }
 #endif
 #ifdef CONFIG_PCI
         platform_driver_unregister(&mpc85xx_pci_err_driver);
diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c
index 208244e4a6f2..0de7d8770891 100644
--- a/drivers/edac/ppc4xx_edac.c
+++ b/drivers/edac/ppc4xx_edac.c
@@ -1019,7 +1019,7 @@ ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
         struct ppc4xx_edac_pdata *pdata = NULL;
         const struct device_node *np = op->dev.of_node;
 
-        if (op->dev.of_match == NULL)
+        if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL)
                 return -EINVAL;
 
         /* Initial driver pointers and private data */
diff --git a/drivers/edac/r82600_edac.c b/drivers/edac/r82600_edac.c
index 387997a3fab5..b153674431f1 100644
--- a/drivers/edac/r82600_edac.c
+++ b/drivers/edac/r82600_edac.c
@@ -120,7 +120,7 @@
                                  *        write 0=NOP
                                  */
 
-#define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundry Address
+#define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundary Address
                                  *  Registers
                                  *
                                  * 7:0  Address lines 30:24 - upper limit of
@@ -217,7 +217,7 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 {
         struct csrow_info *csrow;
         int index;
-        u8 drbar;               /* SDRAM Row Boundry Address Register */
+        u8 drbar;               /* SDRAM Row Boundary Address Register */
         u32 row_high_limit, row_high_limit_last;
         u32 reg_sdram, ecc_on, row_base;
 
@@ -236,7 +236,7 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
                 row_high_limit = ((u32) drbar << 24);
 /*              row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
 
-                debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
+                debugf1("%s() Row=%d, Boundary Address=%#0x, Last = %#0x\n",
                         __func__, index, row_high_limit, row_high_limit_last);
 
                 /* Empty row [p.57] */