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-rw-r--r--drivers/edac/Kconfig36
-rw-r--r--drivers/edac/Makefile2
-rw-r--r--drivers/edac/amd8111_edac.c595
-rw-r--r--drivers/edac/amd8111_edac.h130
-rw-r--r--drivers/edac/amd8131_edac.c379
-rw-r--r--drivers/edac/amd8131_edac.h119
-rw-r--r--drivers/edac/edac_core.h16
-rw-r--r--drivers/edac/edac_pci.c14
-rw-r--r--drivers/edac/ppc4xx_edac.c1448
-rw-r--r--drivers/edac/ppc4xx_edac.h172
10 files changed, 2906 insertions, 5 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index eee47fd16d79..e5f5c5a8ba6c 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -1,13 +1,12 @@
1# 1#
2# EDAC Kconfig 2# EDAC Kconfig
3# Copyright (c) 2003 Linux Networx 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL 4# Licensed and distributed under the GPL
5# 5#
6 6
7menuconfig EDAC 7menuconfig EDAC
8 bool "EDAC - error detection and reporting (EXPERIMENTAL)" 8 bool "EDAC - error detection and reporting"
9 depends on HAS_IOMEM 9 depends on HAS_IOMEM
10 depends on EXPERIMENTAL
11 depends on X86 || PPC 10 depends on X86 || PPC
12 help 11 help
13 EDAC is designed to report errors in the core system. 12 EDAC is designed to report errors in the core system.
@@ -40,6 +39,14 @@ config EDAC_DEBUG
40 there're four debug levels (x=0,1,2,3 from low to high). 39 there're four debug levels (x=0,1,2,3 from low to high).
41 Usually you should select 'N'. 40 Usually you should select 'N'.
42 41
42config EDAC_DEBUG_VERBOSE
43 bool "More verbose debugging"
44 depends on EDAC_DEBUG
45 help
46 This option makes debugging information more verbose.
47 Source file name and line number where debugging message
48 printed will be added to debugging message.
49
43config EDAC_MM_EDAC 50config EDAC_MM_EDAC
44 tristate "Main Memory EDAC (Error Detection And Correction) reporting" 51 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
45 default y 52 default y
@@ -174,4 +181,27 @@ config EDAC_CELL
174 Cell Broadband Engine internal memory controller 181 Cell Broadband Engine internal memory controller
175 on platform without a hypervisor 182 on platform without a hypervisor
176 183
184config EDAC_PPC4XX
185 tristate "PPC4xx IBM DDR2 Memory Controller"
186 depends on EDAC_MM_EDAC && 4xx
187 help
188 This enables support for EDAC on the ECC memory used
189 with the IBM DDR2 memory controller found in various
190 PowerPC 4xx embedded processors such as the 405EX[r],
191 440SP, 440SPe, 460EX, 460GT and 460SX.
192
193config EDAC_AMD8131
194 tristate "AMD8131 HyperTransport PCI-X Tunnel"
195 depends on EDAC_MM_EDAC && PCI
196 help
197 Support for error detection and correction on the
198 AMD8131 HyperTransport PCI-X Tunnel chip.
199
200config EDAC_AMD8111
201 tristate "AMD8111 HyperTransport I/O Hub"
202 depends on EDAC_MM_EDAC && PCI
203 help
204 Support for error detection and correction on the
205 AMD8111 HyperTransport I/O Hub chip.
206
177endif # EDAC 207endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index b75196927de3..a5fdcf02f591 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -34,4 +34,4 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
34obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac.o 34obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac.o
35obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o 35obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
36obj-$(CONFIG_EDAC_CELL) += cell_edac.o 36obj-$(CONFIG_EDAC_CELL) += cell_edac.o
37 37obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
diff --git a/drivers/edac/amd8111_edac.c b/drivers/edac/amd8111_edac.c
new file mode 100644
index 000000000000..614692181120
--- /dev/null
+++ b/drivers/edac/amd8111_edac.c
@@ -0,0 +1,595 @@
1/*
2 * amd8111_edac.c, AMD8111 Hyper Transport chip EDAC kernel module
3 *
4 * Copyright (c) 2008 Wind River Systems, Inc.
5 *
6 * Authors: Cao Qingtao <qingtao.cao@windriver.com>
7 * Benjamin Walsh <benjamin.walsh@windriver.com>
8 * Hu Yongqi <yongqi.hu@windriver.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/bitops.h>
28#include <linux/edac.h>
29#include <linux/pci_ids.h>
30#include <asm/io.h>
31
32#include "edac_core.h"
33#include "edac_module.h"
34#include "amd8111_edac.h"
35
36#define AMD8111_EDAC_REVISION " Ver: 1.0.0 " __DATE__
37#define AMD8111_EDAC_MOD_STR "amd8111_edac"
38
39#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460
40static int edac_dev_idx;
41
42enum amd8111_edac_devs {
43 LPC_BRIDGE = 0,
44};
45
46enum amd8111_edac_pcis {
47 PCI_BRIDGE = 0,
48};
49
50/* Wrapper functions for accessing PCI configuration space */
51static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
52{
53 int ret;
54
55 ret = pci_read_config_dword(dev, reg, val32);
56 if (ret != 0)
57 printk(KERN_ERR AMD8111_EDAC_MOD_STR
58 " PCI Access Read Error at 0x%x\n", reg);
59
60 return ret;
61}
62
63static void edac_pci_read_byte(struct pci_dev *dev, int reg, u8 *val8)
64{
65 int ret;
66
67 ret = pci_read_config_byte(dev, reg, val8);
68 if (ret != 0)
69 printk(KERN_ERR AMD8111_EDAC_MOD_STR
70 " PCI Access Read Error at 0x%x\n", reg);
71}
72
73static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
74{
75 int ret;
76
77 ret = pci_write_config_dword(dev, reg, val32);
78 if (ret != 0)
79 printk(KERN_ERR AMD8111_EDAC_MOD_STR
80 " PCI Access Write Error at 0x%x\n", reg);
81}
82
83static void edac_pci_write_byte(struct pci_dev *dev, int reg, u8 val8)
84{
85 int ret;
86
87 ret = pci_write_config_byte(dev, reg, val8);
88 if (ret != 0)
89 printk(KERN_ERR AMD8111_EDAC_MOD_STR
90 " PCI Access Write Error at 0x%x\n", reg);
91}
92
93/*
94 * device-specific methods for amd8111 PCI Bridge Controller
95 *
96 * Error Reporting and Handling for amd8111 chipset could be found
97 * in its datasheet 3.1.2 section, P37
98 */
99static void amd8111_pci_bridge_init(struct amd8111_pci_info *pci_info)
100{
101 u32 val32;
102 struct pci_dev *dev = pci_info->dev;
103
104 /* First clear error detection flags on the host interface */
105
106 /* Clear SSE/SMA/STA flags in the global status register*/
107 edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
108 if (val32 & PCI_STSCMD_CLEAR_MASK)
109 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
110
111 /* Clear CRC and Link Fail flags in HT Link Control reg */
112 edac_pci_read_dword(dev, REG_HT_LINK, &val32);
113 if (val32 & HT_LINK_CLEAR_MASK)
114 edac_pci_write_dword(dev, REG_HT_LINK, val32);
115
116 /* Second clear all fault on the secondary interface */
117
118 /* Clear error flags in the memory-base limit reg. */
119 edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
120 if (val32 & MEM_LIMIT_CLEAR_MASK)
121 edac_pci_write_dword(dev, REG_MEM_LIM, val32);
122
123 /* Clear Discard Timer Expired flag in Interrupt/Bridge Control reg */
124 edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
125 if (val32 & PCI_INTBRG_CTRL_CLEAR_MASK)
126 edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
127
128 /* Last enable error detections */
129 if (edac_op_state == EDAC_OPSTATE_POLL) {
130 /* Enable System Error reporting in global status register */
131 edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
132 val32 |= PCI_STSCMD_SERREN;
133 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
134
135 /* Enable CRC Sync flood packets to HyperTransport Link */
136 edac_pci_read_dword(dev, REG_HT_LINK, &val32);
137 val32 |= HT_LINK_CRCFEN;
138 edac_pci_write_dword(dev, REG_HT_LINK, val32);
139
140 /* Enable SSE reporting etc in Interrupt control reg */
141 edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
142 val32 |= PCI_INTBRG_CTRL_POLL_MASK;
143 edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
144 }
145}
146
147static void amd8111_pci_bridge_exit(struct amd8111_pci_info *pci_info)
148{
149 u32 val32;
150 struct pci_dev *dev = pci_info->dev;
151
152 if (edac_op_state == EDAC_OPSTATE_POLL) {
153 /* Disable System Error reporting */
154 edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
155 val32 &= ~PCI_STSCMD_SERREN;
156 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
157
158 /* Disable CRC flood packets */
159 edac_pci_read_dword(dev, REG_HT_LINK, &val32);
160 val32 &= ~HT_LINK_CRCFEN;
161 edac_pci_write_dword(dev, REG_HT_LINK, val32);
162
163 /* Disable DTSERREN/MARSP/SERREN in Interrupt Control reg */
164 edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
165 val32 &= ~PCI_INTBRG_CTRL_POLL_MASK;
166 edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
167 }
168}
169
170static void amd8111_pci_bridge_check(struct edac_pci_ctl_info *edac_dev)
171{
172 struct amd8111_pci_info *pci_info = edac_dev->pvt_info;
173 struct pci_dev *dev = pci_info->dev;
174 u32 val32;
175
176 /* Check out PCI Bridge Status and Command Register */
177 edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
178 if (val32 & PCI_STSCMD_CLEAR_MASK) {
179 printk(KERN_INFO "Error(s) in PCI bridge status and command"
180 "register on device %s\n", pci_info->ctl_name);
181 printk(KERN_INFO "SSE: %d, RMA: %d, RTA: %d\n",
182 (val32 & PCI_STSCMD_SSE) != 0,
183 (val32 & PCI_STSCMD_RMA) != 0,
184 (val32 & PCI_STSCMD_RTA) != 0);
185
186 val32 |= PCI_STSCMD_CLEAR_MASK;
187 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
188
189 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
190 }
191
192 /* Check out HyperTransport Link Control Register */
193 edac_pci_read_dword(dev, REG_HT_LINK, &val32);
194 if (val32 & HT_LINK_LKFAIL) {
195 printk(KERN_INFO "Error(s) in hypertransport link control"
196 "register on device %s\n", pci_info->ctl_name);
197 printk(KERN_INFO "LKFAIL: %d\n",
198 (val32 & HT_LINK_LKFAIL) != 0);
199
200 val32 |= HT_LINK_LKFAIL;
201 edac_pci_write_dword(dev, REG_HT_LINK, val32);
202
203 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
204 }
205
206 /* Check out PCI Interrupt and Bridge Control Register */
207 edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
208 if (val32 & PCI_INTBRG_CTRL_DTSTAT) {
209 printk(KERN_INFO "Error(s) in PCI interrupt and bridge control"
210 "register on device %s\n", pci_info->ctl_name);
211 printk(KERN_INFO "DTSTAT: %d\n",
212 (val32 & PCI_INTBRG_CTRL_DTSTAT) != 0);
213
214 val32 |= PCI_INTBRG_CTRL_DTSTAT;
215 edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
216
217 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
218 }
219
220 /* Check out PCI Bridge Memory Base-Limit Register */
221 edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
222 if (val32 & MEM_LIMIT_CLEAR_MASK) {
223 printk(KERN_INFO
224 "Error(s) in mem limit register on %s device\n",
225 pci_info->ctl_name);
226 printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
227 "RTA: %d, STA: %d, MDPE: %d\n",
228 (val32 & MEM_LIMIT_DPE) != 0,
229 (val32 & MEM_LIMIT_RSE) != 0,
230 (val32 & MEM_LIMIT_RMA) != 0,
231 (val32 & MEM_LIMIT_RTA) != 0,
232 (val32 & MEM_LIMIT_STA) != 0,
233 (val32 & MEM_LIMIT_MDPE) != 0);
234
235 val32 |= MEM_LIMIT_CLEAR_MASK;
236 edac_pci_write_dword(dev, REG_MEM_LIM, val32);
237
238 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
239 }
240}
241
242static struct resource *legacy_io_res;
243static int at_compat_reg_broken;
244#define LEGACY_NR_PORTS 1
245
246/* device-specific methods for amd8111 LPC Bridge device */
247static void amd8111_lpc_bridge_init(struct amd8111_dev_info *dev_info)
248{
249 u8 val8;
250 struct pci_dev *dev = dev_info->dev;
251
252 /* First clear REG_AT_COMPAT[SERR, IOCHK] if necessary */
253 legacy_io_res = request_region(REG_AT_COMPAT, LEGACY_NR_PORTS,
254 AMD8111_EDAC_MOD_STR);
255 if (!legacy_io_res)
256 printk(KERN_INFO "%s: failed to request legacy I/O region "
257 "start %d, len %d\n", __func__,
258 REG_AT_COMPAT, LEGACY_NR_PORTS);
259 else {
260 val8 = __do_inb(REG_AT_COMPAT);
261 if (val8 == 0xff) { /* buggy port */
262 printk(KERN_INFO "%s: port %d is buggy, not supported"
263 " by hardware?\n", __func__, REG_AT_COMPAT);
264 at_compat_reg_broken = 1;
265 release_region(REG_AT_COMPAT, LEGACY_NR_PORTS);
266 legacy_io_res = NULL;
267 } else {
268 u8 out8 = 0;
269 if (val8 & AT_COMPAT_SERR)
270 out8 = AT_COMPAT_CLRSERR;
271 if (val8 & AT_COMPAT_IOCHK)
272 out8 |= AT_COMPAT_CLRIOCHK;
273 if (out8 > 0)
274 __do_outb(out8, REG_AT_COMPAT);
275 }
276 }
277
278 /* Second clear error flags on LPC bridge */
279 edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
280 if (val8 & IO_CTRL_1_CLEAR_MASK)
281 edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);
282}
283
284static void amd8111_lpc_bridge_exit(struct amd8111_dev_info *dev_info)
285{
286 if (legacy_io_res)
287 release_region(REG_AT_COMPAT, LEGACY_NR_PORTS);
288}
289
290static void amd8111_lpc_bridge_check(struct edac_device_ctl_info *edac_dev)
291{
292 struct amd8111_dev_info *dev_info = edac_dev->pvt_info;
293 struct pci_dev *dev = dev_info->dev;
294 u8 val8;
295
296 edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
297 if (val8 & IO_CTRL_1_CLEAR_MASK) {
298 printk(KERN_INFO
299 "Error(s) in IO control register on %s device\n",
300 dev_info->ctl_name);
301 printk(KERN_INFO "LPC ERR: %d, PW2LPC: %d\n",
302 (val8 & IO_CTRL_1_LPC_ERR) != 0,
303 (val8 & IO_CTRL_1_PW2LPC) != 0);
304
305 val8 |= IO_CTRL_1_CLEAR_MASK;
306 edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);
307
308 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
309 }
310
311 if (at_compat_reg_broken == 0) {
312 u8 out8 = 0;
313 val8 = __do_inb(REG_AT_COMPAT);
314 if (val8 & AT_COMPAT_SERR)
315 out8 = AT_COMPAT_CLRSERR;
316 if (val8 & AT_COMPAT_IOCHK)
317 out8 |= AT_COMPAT_CLRIOCHK;
318 if (out8 > 0) {
319 __do_outb(out8, REG_AT_COMPAT);
320 edac_device_handle_ue(edac_dev, 0, 0,
321 edac_dev->ctl_name);
322 }
323 }
324}
325
326/* General devices represented by edac_device_ctl_info */
327static struct amd8111_dev_info amd8111_devices[] = {
328 [LPC_BRIDGE] = {
329 .err_dev = PCI_DEVICE_ID_AMD_8111_LPC,
330 .ctl_name = "lpc",
331 .init = amd8111_lpc_bridge_init,
332 .exit = amd8111_lpc_bridge_exit,
333 .check = amd8111_lpc_bridge_check,
334 },
335 {0},
336};
337
338/* PCI controllers represented by edac_pci_ctl_info */
339static struct amd8111_pci_info amd8111_pcis[] = {
340 [PCI_BRIDGE] = {
341 .err_dev = PCI_DEVICE_ID_AMD_8111_PCI,
342 .ctl_name = "AMD8111_PCI_Controller",
343 .init = amd8111_pci_bridge_init,
344 .exit = amd8111_pci_bridge_exit,
345 .check = amd8111_pci_bridge_check,
346 },
347 {0},
348};
349
350static int amd8111_dev_probe(struct pci_dev *dev,
351 const struct pci_device_id *id)
352{
353 struct amd8111_dev_info *dev_info = &amd8111_devices[id->driver_data];
354
355 dev_info->dev = pci_get_device(PCI_VENDOR_ID_AMD,
356 dev_info->err_dev, NULL);
357
358 if (!dev_info->dev) {
359 printk(KERN_ERR "EDAC device not found:"
360 "vendor %x, device %x, name %s\n",
361 PCI_VENDOR_ID_AMD, dev_info->err_dev,
362 dev_info->ctl_name);
363 return -ENODEV;
364 }
365
366 if (pci_enable_device(dev_info->dev)) {
367 pci_dev_put(dev_info->dev);
368 printk(KERN_ERR "failed to enable:"
369 "vendor %x, device %x, name %s\n",
370 PCI_VENDOR_ID_AMD, dev_info->err_dev,
371 dev_info->ctl_name);
372 return -ENODEV;
373 }
374
375 /*
376 * we do not allocate extra private structure for
377 * edac_device_ctl_info, but make use of existing
378 * one instead.
379 */
380 dev_info->edac_idx = edac_dev_idx++;
381 dev_info->edac_dev =
382 edac_device_alloc_ctl_info(0, dev_info->ctl_name, 1,
383 NULL, 0, 0,
384 NULL, 0, dev_info->edac_idx);
385 if (!dev_info->edac_dev)
386 return -ENOMEM;
387
388 dev_info->edac_dev->pvt_info = dev_info;
389 dev_info->edac_dev->dev = &dev_info->dev->dev;
390 dev_info->edac_dev->mod_name = AMD8111_EDAC_MOD_STR;
391 dev_info->edac_dev->ctl_name = dev_info->ctl_name;
392 dev_info->edac_dev->dev_name = dev_info->dev->dev.bus_id;
393
394 if (edac_op_state == EDAC_OPSTATE_POLL)
395 dev_info->edac_dev->edac_check = dev_info->check;
396
397 if (dev_info->init)
398 dev_info->init(dev_info);
399
400 if (edac_device_add_device(dev_info->edac_dev) > 0) {
401 printk(KERN_ERR "failed to add edac_dev for %s\n",
402 dev_info->ctl_name);
403 edac_device_free_ctl_info(dev_info->edac_dev);
404 return -ENODEV;
405 }
406
407 printk(KERN_INFO "added one edac_dev on AMD8111 "
408 "vendor %x, device %x, name %s\n",
409 PCI_VENDOR_ID_AMD, dev_info->err_dev,
410 dev_info->ctl_name);
411
412 return 0;
413}
414
415static void amd8111_dev_remove(struct pci_dev *dev)
416{
417 struct amd8111_dev_info *dev_info;
418
419 for (dev_info = amd8111_devices; dev_info->err_dev; dev_info++)
420 if (dev_info->dev->device == dev->device)
421 break;
422
423 if (!dev_info->err_dev) /* should never happen */
424 return;
425
426 if (dev_info->edac_dev) {
427 edac_device_del_device(dev_info->edac_dev->dev);
428 edac_device_free_ctl_info(dev_info->edac_dev);
429 }
430
431 if (dev_info->exit)
432 dev_info->exit(dev_info);
433
434 pci_dev_put(dev_info->dev);
435}
436
437static int amd8111_pci_probe(struct pci_dev *dev,
438 const struct pci_device_id *id)
439{
440 struct amd8111_pci_info *pci_info = &amd8111_pcis[id->driver_data];
441
442 pci_info->dev = pci_get_device(PCI_VENDOR_ID_AMD,
443 pci_info->err_dev, NULL);
444
445 if (!pci_info->dev) {
446 printk(KERN_ERR "EDAC device not found:"
447 "vendor %x, device %x, name %s\n",
448 PCI_VENDOR_ID_AMD, pci_info->err_dev,
449 pci_info->ctl_name);
450 return -ENODEV;
451 }
452
453 if (pci_enable_device(pci_info->dev)) {
454 pci_dev_put(pci_info->dev);
455 printk(KERN_ERR "failed to enable:"
456 "vendor %x, device %x, name %s\n",
457 PCI_VENDOR_ID_AMD, pci_info->err_dev,
458 pci_info->ctl_name);
459 return -ENODEV;
460 }
461
462 /*
463 * we do not allocate extra private structure for
464 * edac_pci_ctl_info, but make use of existing
465 * one instead.
466 */
467 pci_info->edac_idx = edac_pci_alloc_index();
468 pci_info->edac_dev = edac_pci_alloc_ctl_info(0, pci_info->ctl_name);
469 if (!pci_info->edac_dev)
470 return -ENOMEM;
471
472 pci_info->edac_dev->pvt_info = pci_info;
473 pci_info->edac_dev->dev = &pci_info->dev->dev;
474 pci_info->edac_dev->mod_name = AMD8111_EDAC_MOD_STR;
475 pci_info->edac_dev->ctl_name = pci_info->ctl_name;
476 pci_info->edac_dev->dev_name = pci_info->dev->dev.bus_id;
477
478 if (edac_op_state == EDAC_OPSTATE_POLL)
479 pci_info->edac_dev->edac_check = pci_info->check;
480
481 if (pci_info->init)
482 pci_info->init(pci_info);
483
484 if (edac_pci_add_device(pci_info->edac_dev, pci_info->edac_idx) > 0) {
485 printk(KERN_ERR "failed to add edac_pci for %s\n",
486 pci_info->ctl_name);
487 edac_pci_free_ctl_info(pci_info->edac_dev);
488 return -ENODEV;
489 }
490
491 printk(KERN_INFO "added one edac_pci on AMD8111 "
492 "vendor %x, device %x, name %s\n",
493 PCI_VENDOR_ID_AMD, pci_info->err_dev,
494 pci_info->ctl_name);
495
496 return 0;
497}
498
499static void amd8111_pci_remove(struct pci_dev *dev)
500{
501 struct amd8111_pci_info *pci_info;
502
503 for (pci_info = amd8111_pcis; pci_info->err_dev; pci_info++)
504 if (pci_info->dev->device == dev->device)
505 break;
506
507 if (!pci_info->err_dev) /* should never happen */
508 return;
509
510 if (pci_info->edac_dev) {
511 edac_pci_del_device(pci_info->edac_dev->dev);
512 edac_pci_free_ctl_info(pci_info->edac_dev);
513 }
514
515 if (pci_info->exit)
516 pci_info->exit(pci_info);
517
518 pci_dev_put(pci_info->dev);
519}
520
521/* PCI Device ID talbe for general EDAC device */
522static const struct pci_device_id amd8111_edac_dev_tbl[] = {
523 {
524 PCI_VEND_DEV(AMD, 8111_LPC),
525 .subvendor = PCI_ANY_ID,
526 .subdevice = PCI_ANY_ID,
527 .class = 0,
528 .class_mask = 0,
529 .driver_data = LPC_BRIDGE,
530 },
531 {
532 0,
533 } /* table is NULL-terminated */
534};
535MODULE_DEVICE_TABLE(pci, amd8111_edac_dev_tbl);
536
537static struct pci_driver amd8111_edac_dev_driver = {
538 .name = "AMD8111_EDAC_DEV",
539 .probe = amd8111_dev_probe,
540 .remove = amd8111_dev_remove,
541 .id_table = amd8111_edac_dev_tbl,
542};
543
544/* PCI Device ID table for EDAC PCI controller */
545static const struct pci_device_id amd8111_edac_pci_tbl[] = {
546 {
547 PCI_VEND_DEV(AMD, 8111_PCI),
548 .subvendor = PCI_ANY_ID,
549 .subdevice = PCI_ANY_ID,
550 .class = 0,
551 .class_mask = 0,
552 .driver_data = PCI_BRIDGE,
553 },
554 {
555 0,
556 } /* table is NULL-terminated */
557};
558MODULE_DEVICE_TABLE(pci, amd8111_edac_pci_tbl);
559
560static struct pci_driver amd8111_edac_pci_driver = {
561 .name = "AMD8111_EDAC_PCI",
562 .probe = amd8111_pci_probe,
563 .remove = amd8111_pci_remove,
564 .id_table = amd8111_edac_pci_tbl,
565};
566
567static int __init amd8111_edac_init(void)
568{
569 int val;
570
571 printk(KERN_INFO "AMD8111 EDAC driver " AMD8111_EDAC_REVISION "\n");
572 printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
573
574 /* Only POLL mode supported so far */
575 edac_op_state = EDAC_OPSTATE_POLL;
576
577 val = pci_register_driver(&amd8111_edac_dev_driver);
578 val |= pci_register_driver(&amd8111_edac_pci_driver);
579
580 return val;
581}
582
583static void __exit amd8111_edac_exit(void)
584{
585 pci_unregister_driver(&amd8111_edac_pci_driver);
586 pci_unregister_driver(&amd8111_edac_dev_driver);
587}
588
589
590module_init(amd8111_edac_init);
591module_exit(amd8111_edac_exit);
592
593MODULE_LICENSE("GPL");
594MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
595MODULE_DESCRIPTION("AMD8111 HyperTransport I/O Hub EDAC kernel module");
diff --git a/drivers/edac/amd8111_edac.h b/drivers/edac/amd8111_edac.h
new file mode 100644
index 000000000000..35794331debc
--- /dev/null
+++ b/drivers/edac/amd8111_edac.h
@@ -0,0 +1,130 @@
1/*
2 * amd8111_edac.h, EDAC defs for AMD8111 hypertransport chip
3 *
4 * Copyright (c) 2008 Wind River Systems, Inc.
5 *
6 * Authors: Cao Qingtao <qingtao.cao@windriver.com>
7 * Benjamin Walsh <benjamin.walsh@windriver.com>
8 * Hu Yongqi <yongqi.hu@windriver.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef _AMD8111_EDAC_H_
25#define _AMD8111_EDAC_H_
26
27/************************************************************
28 * PCI Bridge Status and Command Register, DevA:0x04
29 ************************************************************/
30#define REG_PCI_STSCMD 0x04
31enum pci_stscmd_bits {
32 PCI_STSCMD_SSE = BIT(30),
33 PCI_STSCMD_RMA = BIT(29),
34 PCI_STSCMD_RTA = BIT(28),
35 PCI_STSCMD_SERREN = BIT(8),
36 PCI_STSCMD_CLEAR_MASK = (PCI_STSCMD_SSE |
37 PCI_STSCMD_RMA |
38 PCI_STSCMD_RTA)
39};
40
41/************************************************************
42 * PCI Bridge Memory Base-Limit Register, DevA:0x1c
43 ************************************************************/
44#define REG_MEM_LIM 0x1c
45enum mem_limit_bits {
46 MEM_LIMIT_DPE = BIT(31),
47 MEM_LIMIT_RSE = BIT(30),
48 MEM_LIMIT_RMA = BIT(29),
49 MEM_LIMIT_RTA = BIT(28),
50 MEM_LIMIT_STA = BIT(27),
51 MEM_LIMIT_MDPE = BIT(24),
52 MEM_LIMIT_CLEAR_MASK = (MEM_LIMIT_DPE |
53 MEM_LIMIT_RSE |
54 MEM_LIMIT_RMA |
55 MEM_LIMIT_RTA |
56 MEM_LIMIT_STA |
57 MEM_LIMIT_MDPE)
58};
59
60/************************************************************
61 * HyperTransport Link Control Register, DevA:0xc4
62 ************************************************************/
63#define REG_HT_LINK 0xc4
64enum ht_link_bits {
65 HT_LINK_LKFAIL = BIT(4),
66 HT_LINK_CRCFEN = BIT(1),
67 HT_LINK_CLEAR_MASK = (HT_LINK_LKFAIL)
68};
69
70/************************************************************
71 * PCI Bridge Interrupt and Bridge Control, DevA:0x3c
72 ************************************************************/
73#define REG_PCI_INTBRG_CTRL 0x3c
74enum pci_intbrg_ctrl_bits {
75 PCI_INTBRG_CTRL_DTSERREN = BIT(27),
76 PCI_INTBRG_CTRL_DTSTAT = BIT(26),
77 PCI_INTBRG_CTRL_MARSP = BIT(21),
78 PCI_INTBRG_CTRL_SERREN = BIT(17),
79 PCI_INTBRG_CTRL_PEREN = BIT(16),
80 PCI_INTBRG_CTRL_CLEAR_MASK = (PCI_INTBRG_CTRL_DTSTAT),
81 PCI_INTBRG_CTRL_POLL_MASK = (PCI_INTBRG_CTRL_DTSERREN |
82 PCI_INTBRG_CTRL_MARSP |
83 PCI_INTBRG_CTRL_SERREN)
84};
85
86/************************************************************
87 * I/O Control 1 Register, DevB:0x40
88 ************************************************************/
89#define REG_IO_CTRL_1 0x40
90enum io_ctrl_1_bits {
91 IO_CTRL_1_NMIONERR = BIT(7),
92 IO_CTRL_1_LPC_ERR = BIT(6),
93 IO_CTRL_1_PW2LPC = BIT(1),
94 IO_CTRL_1_CLEAR_MASK = (IO_CTRL_1_LPC_ERR | IO_CTRL_1_PW2LPC)
95};
96
97/************************************************************
98 * Legacy I/O Space Registers
99 ************************************************************/
100#define REG_AT_COMPAT 0x61
101enum at_compat_bits {
102 AT_COMPAT_SERR = BIT(7),
103 AT_COMPAT_IOCHK = BIT(6),
104 AT_COMPAT_CLRIOCHK = BIT(3),
105 AT_COMPAT_CLRSERR = BIT(2),
106};
107
108struct amd8111_dev_info {
109 u16 err_dev; /* PCI Device ID */
110 struct pci_dev *dev;
111 int edac_idx; /* device index */
112 char *ctl_name;
113 struct edac_device_ctl_info *edac_dev;
114 void (*init)(struct amd8111_dev_info *dev_info);
115 void (*exit)(struct amd8111_dev_info *dev_info);
116 void (*check)(struct edac_device_ctl_info *edac_dev);
117};
118
119struct amd8111_pci_info {
120 u16 err_dev; /* PCI Device ID */
121 struct pci_dev *dev;
122 int edac_idx; /* pci index */
123 const char *ctl_name;
124 struct edac_pci_ctl_info *edac_dev;
125 void (*init)(struct amd8111_pci_info *dev_info);
126 void (*exit)(struct amd8111_pci_info *dev_info);
127 void (*check)(struct edac_pci_ctl_info *edac_dev);
128};
129
130#endif /* _AMD8111_EDAC_H_ */
diff --git a/drivers/edac/amd8131_edac.c b/drivers/edac/amd8131_edac.c
new file mode 100644
index 000000000000..c083b31cac5a
--- /dev/null
+++ b/drivers/edac/amd8131_edac.c
@@ -0,0 +1,379 @@
1/*
2 * amd8131_edac.c, AMD8131 hypertransport chip EDAC kernel module
3 *
4 * Copyright (c) 2008 Wind River Systems, Inc.
5 *
6 * Authors: Cao Qingtao <qingtao.cao@windriver.com>
7 * Benjamin Walsh <benjamin.walsh@windriver.com>
8 * Hu Yongqi <yongqi.hu@windriver.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/bitops.h>
29#include <linux/edac.h>
30#include <linux/pci_ids.h>
31
32#include "edac_core.h"
33#include "edac_module.h"
34#include "amd8131_edac.h"
35
36#define AMD8131_EDAC_REVISION " Ver: 1.0.0 " __DATE__
37#define AMD8131_EDAC_MOD_STR "amd8131_edac"
38
39/* Wrapper functions for accessing PCI configuration space */
40static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
41{
42 int ret;
43
44 ret = pci_read_config_dword(dev, reg, val32);
45 if (ret != 0)
46 printk(KERN_ERR AMD8131_EDAC_MOD_STR
47 " PCI Access Read Error at 0x%x\n", reg);
48}
49
50static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
51{
52 int ret;
53
54 ret = pci_write_config_dword(dev, reg, val32);
55 if (ret != 0)
56 printk(KERN_ERR AMD8131_EDAC_MOD_STR
57 " PCI Access Write Error at 0x%x\n", reg);
58}
59
60static char * const bridge_str[] = {
61 [NORTH_A] = "NORTH A",
62 [NORTH_B] = "NORTH B",
63 [SOUTH_A] = "SOUTH A",
64 [SOUTH_B] = "SOUTH B",
65 [NO_BRIDGE] = "NO BRIDGE",
66};
67
68/* Support up to two AMD8131 chipsets on a platform */
69static struct amd8131_dev_info amd8131_devices[] = {
70 {
71 .inst = NORTH_A,
72 .devfn = DEVFN_PCIX_BRIDGE_NORTH_A,
73 .ctl_name = "AMD8131_PCIX_NORTH_A",
74 },
75 {
76 .inst = NORTH_B,
77 .devfn = DEVFN_PCIX_BRIDGE_NORTH_B,
78 .ctl_name = "AMD8131_PCIX_NORTH_B",
79 },
80 {
81 .inst = SOUTH_A,
82 .devfn = DEVFN_PCIX_BRIDGE_SOUTH_A,
83 .ctl_name = "AMD8131_PCIX_SOUTH_A",
84 },
85 {
86 .inst = SOUTH_B,
87 .devfn = DEVFN_PCIX_BRIDGE_SOUTH_B,
88 .ctl_name = "AMD8131_PCIX_SOUTH_B",
89 },
90 {.inst = NO_BRIDGE,},
91};
92
93static void amd8131_pcix_init(struct amd8131_dev_info *dev_info)
94{
95 u32 val32;
96 struct pci_dev *dev = dev_info->dev;
97
98 /* First clear error detection flags */
99 edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
100 if (val32 & MEM_LIMIT_MASK)
101 edac_pci_write_dword(dev, REG_MEM_LIM, val32);
102
103 /* Clear Discard Timer Timedout flag */
104 edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
105 if (val32 & INT_CTLR_DTS)
106 edac_pci_write_dword(dev, REG_INT_CTLR, val32);
107
108 /* Clear CRC Error flag on link side A */
109 edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
110 if (val32 & LNK_CTRL_CRCERR_A)
111 edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
112
113 /* Clear CRC Error flag on link side B */
114 edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
115 if (val32 & LNK_CTRL_CRCERR_B)
116 edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
117
118 /*
119 * Then enable all error detections.
120 *
121 * Setup Discard Timer Sync Flood Enable,
122 * System Error Enable and Parity Error Enable.
123 */
124 edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
125 val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE;
126 edac_pci_write_dword(dev, REG_INT_CTLR, val32);
127
128 /* Enable overall SERR Error detection */
129 edac_pci_read_dword(dev, REG_STS_CMD, &val32);
130 val32 |= STS_CMD_SERREN;
131 edac_pci_write_dword(dev, REG_STS_CMD, val32);
132
133 /* Setup CRC Flood Enable for link side A */
134 edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
135 val32 |= LNK_CTRL_CRCFEN;
136 edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
137
138 /* Setup CRC Flood Enable for link side B */
139 edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
140 val32 |= LNK_CTRL_CRCFEN;
141 edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
142}
143
144static void amd8131_pcix_exit(struct amd8131_dev_info *dev_info)
145{
146 u32 val32;
147 struct pci_dev *dev = dev_info->dev;
148
149 /* Disable SERR, PERR and DTSE Error detection */
150 edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
151 val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE);
152 edac_pci_write_dword(dev, REG_INT_CTLR, val32);
153
154 /* Disable overall System Error detection */
155 edac_pci_read_dword(dev, REG_STS_CMD, &val32);
156 val32 &= ~STS_CMD_SERREN;
157 edac_pci_write_dword(dev, REG_STS_CMD, val32);
158
159 /* Disable CRC Sync Flood on link side A */
160 edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
161 val32 &= ~LNK_CTRL_CRCFEN;
162 edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
163
164 /* Disable CRC Sync Flood on link side B */
165 edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
166 val32 &= ~LNK_CTRL_CRCFEN;
167 edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
168}
169
170static void amd8131_pcix_check(struct edac_pci_ctl_info *edac_dev)
171{
172 struct amd8131_dev_info *dev_info = edac_dev->pvt_info;
173 struct pci_dev *dev = dev_info->dev;
174 u32 val32;
175
176 /* Check PCI-X Bridge Memory Base-Limit Register for errors */
177 edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
178 if (val32 & MEM_LIMIT_MASK) {
179 printk(KERN_INFO "Error(s) in mem limit register "
180 "on %s bridge\n", dev_info->ctl_name);
181 printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
182 "RTA: %d, STA: %d, MDPE: %d\n",
183 val32 & MEM_LIMIT_DPE,
184 val32 & MEM_LIMIT_RSE,
185 val32 & MEM_LIMIT_RMA,
186 val32 & MEM_LIMIT_RTA,
187 val32 & MEM_LIMIT_STA,
188 val32 & MEM_LIMIT_MDPE);
189
190 val32 |= MEM_LIMIT_MASK;
191 edac_pci_write_dword(dev, REG_MEM_LIM, val32);
192
193 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
194 }
195
196 /* Check if Discard Timer timed out */
197 edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
198 if (val32 & INT_CTLR_DTS) {
199 printk(KERN_INFO "Error(s) in interrupt and control register "
200 "on %s bridge\n", dev_info->ctl_name);
201 printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS);
202
203 val32 |= INT_CTLR_DTS;
204 edac_pci_write_dword(dev, REG_INT_CTLR, val32);
205
206 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
207 }
208
209 /* Check if CRC error happens on link side A */
210 edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
211 if (val32 & LNK_CTRL_CRCERR_A) {
212 printk(KERN_INFO "Error(s) in link conf and control register "
213 "on %s bridge\n", dev_info->ctl_name);
214 printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A);
215
216 val32 |= LNK_CTRL_CRCERR_A;
217 edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
218
219 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
220 }
221
222 /* Check if CRC error happens on link side B */
223 edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
224 if (val32 & LNK_CTRL_CRCERR_B) {
225 printk(KERN_INFO "Error(s) in link conf and control register "
226 "on %s bridge\n", dev_info->ctl_name);
227 printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B);
228
229 val32 |= LNK_CTRL_CRCERR_B;
230 edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
231
232 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
233 }
234}
235
236static struct amd8131_info amd8131_chipset = {
237 .err_dev = PCI_DEVICE_ID_AMD_8131_APIC,
238 .devices = amd8131_devices,
239 .init = amd8131_pcix_init,
240 .exit = amd8131_pcix_exit,
241 .check = amd8131_pcix_check,
242};
243
244/*
245 * There are 4 PCIX Bridges on ATCA-6101 that share the same PCI Device ID,
246 * so amd8131_probe() would be called by kernel 4 times, with different
247 * address of pci_dev for each of them each time.
248 */
249static int amd8131_probe(struct pci_dev *dev, const struct pci_device_id *id)
250{
251 struct amd8131_dev_info *dev_info;
252
253 for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
254 dev_info++)
255 if (dev_info->devfn == dev->devfn)
256 break;
257
258 if (dev_info->inst == NO_BRIDGE) /* should never happen */
259 return -ENODEV;
260
261 /*
262 * We can't call pci_get_device() as we are used to do because
263 * there are 4 of them but pci_dev_get() instead.
264 */
265 dev_info->dev = pci_dev_get(dev);
266
267 if (pci_enable_device(dev_info->dev)) {
268 pci_dev_put(dev_info->dev);
269 printk(KERN_ERR "failed to enable:"
270 "vendor %x, device %x, devfn %x, name %s\n",
271 PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
272 dev_info->devfn, dev_info->ctl_name);
273 return -ENODEV;
274 }
275
276 /*
277 * we do not allocate extra private structure for
278 * edac_pci_ctl_info, but make use of existing
279 * one instead.
280 */
281 dev_info->edac_idx = edac_pci_alloc_index();
282 dev_info->edac_dev = edac_pci_alloc_ctl_info(0, dev_info->ctl_name);
283 if (!dev_info->edac_dev)
284 return -ENOMEM;
285
286 dev_info->edac_dev->pvt_info = dev_info;
287 dev_info->edac_dev->dev = &dev_info->dev->dev;
288 dev_info->edac_dev->mod_name = AMD8131_EDAC_MOD_STR;
289 dev_info->edac_dev->ctl_name = dev_info->ctl_name;
290 dev_info->edac_dev->dev_name = dev_info->dev->dev.bus_id;
291
292 if (edac_op_state == EDAC_OPSTATE_POLL)
293 dev_info->edac_dev->edac_check = amd8131_chipset.check;
294
295 if (amd8131_chipset.init)
296 amd8131_chipset.init(dev_info);
297
298 if (edac_pci_add_device(dev_info->edac_dev, dev_info->edac_idx) > 0) {
299 printk(KERN_ERR "failed edac_pci_add_device() for %s\n",
300 dev_info->ctl_name);
301 edac_pci_free_ctl_info(dev_info->edac_dev);
302 return -ENODEV;
303 }
304
305 printk(KERN_INFO "added one device on AMD8131 "
306 "vendor %x, device %x, devfn %x, name %s\n",
307 PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
308 dev_info->devfn, dev_info->ctl_name);
309
310 return 0;
311}
312
313static void amd8131_remove(struct pci_dev *dev)
314{
315 struct amd8131_dev_info *dev_info;
316
317 for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
318 dev_info++)
319 if (dev_info->devfn == dev->devfn)
320 break;
321
322 if (dev_info->inst == NO_BRIDGE) /* should never happen */
323 return;
324
325 if (dev_info->edac_dev) {
326 edac_pci_del_device(dev_info->edac_dev->dev);
327 edac_pci_free_ctl_info(dev_info->edac_dev);
328 }
329
330 if (amd8131_chipset.exit)
331 amd8131_chipset.exit(dev_info);
332
333 pci_dev_put(dev_info->dev);
334}
335
336static const struct pci_device_id amd8131_edac_pci_tbl[] = {
337 {
338 PCI_VEND_DEV(AMD, 8131_BRIDGE),
339 .subvendor = PCI_ANY_ID,
340 .subdevice = PCI_ANY_ID,
341 .class = 0,
342 .class_mask = 0,
343 .driver_data = 0,
344 },
345 {
346 0,
347 } /* table is NULL-terminated */
348};
349MODULE_DEVICE_TABLE(pci, amd8131_edac_pci_tbl);
350
351static struct pci_driver amd8131_edac_driver = {
352 .name = AMD8131_EDAC_MOD_STR,
353 .probe = amd8131_probe,
354 .remove = amd8131_remove,
355 .id_table = amd8131_edac_pci_tbl,
356};
357
358static int __init amd8131_edac_init(void)
359{
360 printk(KERN_INFO "AMD8131 EDAC driver " AMD8131_EDAC_REVISION "\n");
361 printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
362
363 /* Only POLL mode supported so far */
364 edac_op_state = EDAC_OPSTATE_POLL;
365
366 return pci_register_driver(&amd8131_edac_driver);
367}
368
369static void __exit amd8131_edac_exit(void)
370{
371 pci_unregister_driver(&amd8131_edac_driver);
372}
373
374module_init(amd8131_edac_init);
375module_exit(amd8131_edac_exit);
376
377MODULE_LICENSE("GPL");
378MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
379MODULE_DESCRIPTION("AMD8131 HyperTransport PCI-X Tunnel EDAC kernel module");
diff --git a/drivers/edac/amd8131_edac.h b/drivers/edac/amd8131_edac.h
new file mode 100644
index 000000000000..60e0d1c72dee
--- /dev/null
+++ b/drivers/edac/amd8131_edac.h
@@ -0,0 +1,119 @@
1/*
2 * amd8131_edac.h, EDAC defs for AMD8131 hypertransport chip
3 *
4 * Copyright (c) 2008 Wind River Systems, Inc.
5 *
6 * Authors: Cao Qingtao <qingtao.cao@windriver.com>
7 * Benjamin Walsh <benjamin.walsh@windriver.com>
8 * Hu Yongqi <yongqi.hu@windriver.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef _AMD8131_EDAC_H_
25#define _AMD8131_EDAC_H_
26
27#define DEVFN_PCIX_BRIDGE_NORTH_A 8
28#define DEVFN_PCIX_BRIDGE_NORTH_B 16
29#define DEVFN_PCIX_BRIDGE_SOUTH_A 24
30#define DEVFN_PCIX_BRIDGE_SOUTH_B 32
31
32/************************************************************
33 * PCI-X Bridge Status and Command Register, DevA:0x04
34 ************************************************************/
35#define REG_STS_CMD 0x04
36enum sts_cmd_bits {
37 STS_CMD_SSE = BIT(30),
38 STS_CMD_SERREN = BIT(8)
39};
40
41/************************************************************
42 * PCI-X Bridge Interrupt and Bridge Control Register,
43 ************************************************************/
44#define REG_INT_CTLR 0x3c
45enum int_ctlr_bits {
46 INT_CTLR_DTSE = BIT(27),
47 INT_CTLR_DTS = BIT(26),
48 INT_CTLR_SERR = BIT(17),
49 INT_CTLR_PERR = BIT(16)
50};
51
52/************************************************************
53 * PCI-X Bridge Memory Base-Limit Register, DevA:0x1C
54 ************************************************************/
55#define REG_MEM_LIM 0x1c
56enum mem_limit_bits {
57 MEM_LIMIT_DPE = BIT(31),
58 MEM_LIMIT_RSE = BIT(30),
59 MEM_LIMIT_RMA = BIT(29),
60 MEM_LIMIT_RTA = BIT(28),
61 MEM_LIMIT_STA = BIT(27),
62 MEM_LIMIT_MDPE = BIT(24),
63 MEM_LIMIT_MASK = MEM_LIMIT_DPE|MEM_LIMIT_RSE|MEM_LIMIT_RMA|
64 MEM_LIMIT_RTA|MEM_LIMIT_STA|MEM_LIMIT_MDPE
65};
66
67/************************************************************
68 * Link Configuration And Control Register, side A
69 ************************************************************/
70#define REG_LNK_CTRL_A 0xc4
71
72/************************************************************
73 * Link Configuration And Control Register, side B
74 ************************************************************/
75#define REG_LNK_CTRL_B 0xc8
76
77enum lnk_ctrl_bits {
78 LNK_CTRL_CRCERR_A = BIT(9),
79 LNK_CTRL_CRCERR_B = BIT(8),
80 LNK_CTRL_CRCFEN = BIT(1)
81};
82
83enum pcix_bridge_inst {
84 NORTH_A = 0,
85 NORTH_B = 1,
86 SOUTH_A = 2,
87 SOUTH_B = 3,
88 NO_BRIDGE = 4
89};
90
91struct amd8131_dev_info {
92 int devfn;
93 enum pcix_bridge_inst inst;
94 struct pci_dev *dev;
95 int edac_idx; /* pci device index */
96 char *ctl_name;
97 struct edac_pci_ctl_info *edac_dev;
98};
99
100/*
101 * AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
102 * Controler, and ATCA-6101 has two AMD8131 chipsets, so there are
103 * four PCIX Bridges on ATCA-6101 altogether.
104 *
105 * These PCIX Bridges share the same PCI Device ID and are all of
106 * Function Zero, they could be discrimated by their pci_dev->devfn.
107 * They share the same set of init/check/exit methods, and their
108 * private structures are collected in the devices[] array.
109 */
110struct amd8131_info {
111 u16 err_dev; /* PCI Device ID for AMD8131 APIC*/
112 struct amd8131_dev_info *devices;
113 void (*init)(struct amd8131_dev_info *dev_info);
114 void (*exit)(struct amd8131_dev_info *dev_info);
115 void (*check)(struct edac_pci_ctl_info *edac_dev);
116};
117
118#endif /* _AMD8131_EDAC_H_ */
119
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h
index 4b55ec607a88..28f2c3f959b5 100644
--- a/drivers/edac/edac_core.h
+++ b/drivers/edac/edac_core.h
@@ -49,6 +49,10 @@
49#define edac_printk(level, prefix, fmt, arg...) \ 49#define edac_printk(level, prefix, fmt, arg...) \
50 printk(level "EDAC " prefix ": " fmt, ##arg) 50 printk(level "EDAC " prefix ": " fmt, ##arg)
51 51
52#define edac_printk_verbose(level, prefix, fmt, arg...) \
53 printk(level "EDAC " prefix ": " "in %s, line at %d: " fmt, \
54 __FILE__, __LINE__, ##arg)
55
52#define edac_mc_printk(mci, level, fmt, arg...) \ 56#define edac_mc_printk(mci, level, fmt, arg...) \
53 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg) 57 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
54 58
@@ -71,11 +75,20 @@
71#ifdef CONFIG_EDAC_DEBUG 75#ifdef CONFIG_EDAC_DEBUG
72extern int edac_debug_level; 76extern int edac_debug_level;
73 77
78#ifndef CONFIG_EDAC_DEBUG_VERBOSE
74#define edac_debug_printk(level, fmt, arg...) \ 79#define edac_debug_printk(level, fmt, arg...) \
75 do { \ 80 do { \
76 if (level <= edac_debug_level) \ 81 if (level <= edac_debug_level) \
77 edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \ 82 edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
78 } while(0) 83 } while (0)
84#else /* CONFIG_EDAC_DEBUG_VERBOSE */
85#define edac_debug_printk(level, fmt, arg...) \
86 do { \
87 if (level <= edac_debug_level) \
88 edac_printk_verbose(KERN_DEBUG, EDAC_DEBUG, fmt, \
89 ##arg); \
90 } while (0)
91#endif
79 92
80#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ ) 93#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
81#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ ) 94#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
@@ -831,6 +844,7 @@ extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
831extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci, 844extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
832 unsigned long value); 845 unsigned long value);
833 846
847extern int edac_pci_alloc_index(void);
834extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx); 848extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
835extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev); 849extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
836 850
diff --git a/drivers/edac/edac_pci.c b/drivers/edac/edac_pci.c
index 5d3c8083a40e..5b150aea703a 100644
--- a/drivers/edac/edac_pci.c
+++ b/drivers/edac/edac_pci.c
@@ -30,6 +30,7 @@
30 30
31static DEFINE_MUTEX(edac_pci_ctls_mutex); 31static DEFINE_MUTEX(edac_pci_ctls_mutex);
32static LIST_HEAD(edac_pci_list); 32static LIST_HEAD(edac_pci_list);
33static atomic_t pci_indexes = ATOMIC_INIT(0);
33 34
34/* 35/*
35 * edac_pci_alloc_ctl_info 36 * edac_pci_alloc_ctl_info
@@ -318,6 +319,19 @@ void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
318EXPORT_SYMBOL_GPL(edac_pci_reset_delay_period); 319EXPORT_SYMBOL_GPL(edac_pci_reset_delay_period);
319 320
320/* 321/*
322 * edac_pci_alloc_index: Allocate a unique PCI index number
323 *
324 * Return:
325 * allocated index number
326 *
327 */
328int edac_pci_alloc_index(void)
329{
330 return atomic_inc_return(&pci_indexes) - 1;
331}
332EXPORT_SYMBOL_GPL(edac_pci_alloc_index);
333
334/*
321 * edac_pci_add_device: Insert the 'edac_dev' structure into the 335 * edac_pci_add_device: Insert the 'edac_dev' structure into the
322 * edac_pci global list and create sysfs entries associated with 336 * edac_pci global list and create sysfs entries associated with
323 * edac_pci structure. 337 * edac_pci structure.
diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c
new file mode 100644
index 000000000000..11f2172aa1e6
--- /dev/null
+++ b/drivers/edac/ppc4xx_edac.c
@@ -0,0 +1,1448 @@
1/*
2 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; version 2 of the
8 * License.
9 *
10 */
11
12#include <linux/edac.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/of_platform.h>
20#include <linux/types.h>
21
22#include <asm/dcr.h>
23
24#include "edac_core.h"
25#include "ppc4xx_edac.h"
26
27/*
28 * This file implements a driver for monitoring and handling events
29 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
30 * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
31 *
32 * As realized in the 405EX[r], this controller features:
33 *
34 * - Support for registered- and non-registered DDR1 and DDR2 memory.
35 * - 32-bit or 16-bit memory interface with optional ECC.
36 *
37 * o ECC support includes:
38 *
39 * - 4-bit SEC/DED
40 * - Aligned-nibble error detect
41 * - Bypass mode
42 *
43 * - Two (2) memory banks/ranks.
44 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
45 * bank/rank in 16-bit mode.
46 *
47 * As realized in the 440SP and 440SPe, this controller changes/adds:
48 *
49 * - 64-bit or 32-bit memory interface with optional ECC.
50 *
51 * o ECC support includes:
52 *
53 * - 8-bit SEC/DED
54 * - Aligned-nibble error detect
55 * - Bypass mode
56 *
57 * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
58 * per bank/rank in 32-bit mode.
59 *
60 * As realized in the 460EX and 460GT, this controller changes/adds:
61 *
62 * - 64-bit or 32-bit memory interface with optional ECC.
63 *
64 * o ECC support includes:
65 *
66 * - 8-bit SEC/DED
67 * - Aligned-nibble error detect
68 * - Bypass mode
69 *
70 * - Four (4) memory banks/ranks.
71 * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
72 * per bank/rank in 32-bit mode.
73 *
74 * At present, this driver has ONLY been tested against the controller
75 * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
76 * boards (256 MiB w/o ECC memory soldered onto the board) and a
77 * proprietary board based on those designs (128 MiB ECC memory, also
78 * soldered onto the board).
79 *
80 * Dynamic feature detection and handling needs to be added for the
81 * other realizations of this controller listed above.
82 *
83 * Eventually, this driver will likely be adapted to the above variant
84 * realizations of this controller as well as broken apart to handle
85 * the other known ECC-capable controllers prevalent in other 4xx
86 * processors:
87 *
88 * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
89 * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
90 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
91 *
92 * For this controller, unfortunately, correctable errors report
93 * nothing more than the beat/cycle and byte/lane the correction
94 * occurred on and the check bit group that covered the error.
95 *
96 * In contrast, uncorrectable errors also report the failing address,
97 * the bus master and the transaction direction (i.e. read or write)
98 *
99 * Regardless of whether the error is a CE or a UE, we report the
100 * following pieces of information in the driver-unique message to the
101 * EDAC subsystem:
102 *
103 * - Device tree path
104 * - Bank(s)
105 * - Check bit error group
106 * - Beat(s)/lane(s)
107 */
108
109/* Preprocessor Definitions */
110
111#define EDAC_OPSTATE_INT_STR "interrupt"
112#define EDAC_OPSTATE_POLL_STR "polled"
113#define EDAC_OPSTATE_UNKNOWN_STR "unknown"
114
115#define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac"
116#define PPC4XX_EDAC_MODULE_REVISION "v1.0.0 " __DATE__
117
118#define PPC4XX_EDAC_MESSAGE_SIZE 256
119
120/*
121 * Kernel logging without an EDAC instance
122 */
123#define ppc4xx_edac_printk(level, fmt, arg...) \
124 edac_printk(level, "PPC4xx MC", fmt, ##arg)
125
126/*
127 * Kernel logging with an EDAC instance
128 */
129#define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
130 edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
131
132/*
133 * Macros to convert bank configuration size enumerations into MiB and
134 * page values.
135 */
136#define SDRAM_MBCF_SZ_MiB_MIN 4
137#define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \
138 << (SDRAM_MBCF_SZ_DECODE(n)))
139#define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \
140 << (20 - PAGE_SHIFT + \
141 SDRAM_MBCF_SZ_DECODE(n)))
142
143/*
144 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
145 * indirectly acccessed and have a base and length defined by the
146 * device tree. The base can be anything; however, we expect the
147 * length to be precisely two registers, the first for the address
148 * window and the second for the data window.
149 */
150#define SDRAM_DCR_RESOURCE_LEN 2
151#define SDRAM_DCR_ADDR_OFFSET 0
152#define SDRAM_DCR_DATA_OFFSET 1
153
154/*
155 * Device tree interrupt indices
156 */
157#define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
158#define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
159
160/* Type Definitions */
161
162/*
163 * PPC4xx SDRAM memory controller private instance data
164 */
165struct ppc4xx_edac_pdata {
166 dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */
167 struct {
168 int sec; /* Single-bit correctable error IRQ assigned */
169 int ded; /* Double-bit detectable error IRQ assigned */
170 } irqs;
171};
172
173/*
174 * Various status data gathered and manipulated when checking and
175 * reporting ECC status.
176 */
177struct ppc4xx_ecc_status {
178 u32 ecces;
179 u32 besr;
180 u32 bearh;
181 u32 bearl;
182 u32 wmirq;
183};
184
185/* Function Prototypes */
186
187static int ppc4xx_edac_probe(struct of_device *device,
188 const struct of_device_id *device_id);
189static int ppc4xx_edac_remove(struct of_device *device);
190
191/* Global Variables */
192
193/*
194 * Device tree node type and compatible tuples this driver can match
195 * on.
196 */
197static struct of_device_id ppc4xx_edac_match[] = {
198 {
199 .compatible = "ibm,sdram-4xx-ddr2"
200 },
201 { }
202};
203
204static struct of_platform_driver ppc4xx_edac_driver = {
205 .match_table = ppc4xx_edac_match,
206 .probe = ppc4xx_edac_probe,
207 .remove = ppc4xx_edac_remove,
208 .driver = {
209 .owner = THIS_MODULE,
210 .name = PPC4XX_EDAC_MODULE_NAME
211 }
212};
213
214/*
215 * TODO: The row and channel parameters likely need to be dynamically
216 * set based on the aforementioned variant controller realizations.
217 */
218static const unsigned ppc4xx_edac_nr_csrows = 2;
219static const unsigned ppc4xx_edac_nr_chans = 1;
220
221/*
222 * Strings associated with PLB master IDs capable of being posted in
223 * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors.
224 */
225static const char * const ppc4xx_plb_masters[9] = {
226 [SDRAM_PLB_M0ID_ICU] = "ICU",
227 [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
228 [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
229 [SDRAM_PLB_M0ID_DMA] = "DMA",
230 [SDRAM_PLB_M0ID_DCU] = "DCU",
231 [SDRAM_PLB_M0ID_OPB] = "OPB",
232 [SDRAM_PLB_M0ID_MAL] = "MAL",
233 [SDRAM_PLB_M0ID_SEC] = "SEC",
234 [SDRAM_PLB_M0ID_AHB] = "AHB"
235};
236
237/**
238 * mfsdram - read and return controller register data
239 * @dcr_host: A pointer to the DCR mapping.
240 * @idcr_n: The indirect DCR register to read.
241 *
242 * This routine reads and returns the data associated with the
243 * controller's specified indirect DCR register.
244 *
245 * Returns the read data.
246 */
247static inline u32
248mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n)
249{
250 return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
251 dcr_host->base + SDRAM_DCR_DATA_OFFSET,
252 idcr_n);
253}
254
255/**
256 * mtsdram - write controller register data
257 * @dcr_host: A pointer to the DCR mapping.
258 * @idcr_n: The indirect DCR register to write.
259 * @value: The data to write.
260 *
261 * This routine writes the provided data to the controller's specified
262 * indirect DCR register.
263 */
264static inline void
265mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value)
266{
267 return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
268 dcr_host->base + SDRAM_DCR_DATA_OFFSET,
269 idcr_n,
270 value);
271}
272
273/**
274 * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
275 * @status: A pointer to the ECC status structure to check for an
276 * ECC bank error.
277 * @bank: The bank to check for an ECC error.
278 *
279 * This routine determines whether the specified bank has an ECC
280 * error.
281 *
282 * Returns true if the specified bank has an ECC error; otherwise,
283 * false.
284 */
285static bool
286ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status,
287 unsigned int bank)
288{
289 switch (bank) {
290 case 0:
291 return status->ecces & SDRAM_ECCES_BK0ER;
292 case 1:
293 return status->ecces & SDRAM_ECCES_BK1ER;
294 default:
295 return false;
296 }
297}
298
299/**
300 * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
301 * @mci: A pointer to the EDAC memory controller instance associated
302 * with the bank message being generated.
303 * @status: A pointer to the ECC status structure to generate the
304 * message from.
305 * @buffer: A pointer to the buffer in which to generate the
306 * message.
307 * @size: The size, in bytes, of space available in buffer.
308 *
309 * This routine generates to the provided buffer the portion of the
310 * driver-unique report message associated with the ECCESS[BKNER]
311 * field of the specified ECC status.
312 *
313 * Returns the number of characters generated on success; otherwise, <
314 * 0 on error.
315 */
316static int
317ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
318 const struct ppc4xx_ecc_status *status,
319 char *buffer,
320 size_t size)
321{
322 int n, total = 0;
323 unsigned int row, rows;
324
325 n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name);
326
327 if (n < 0 || n >= size)
328 goto fail;
329
330 buffer += n;
331 size -= n;
332 total += n;
333
334 for (rows = 0, row = 0; row < mci->nr_csrows; row++) {
335 if (ppc4xx_edac_check_bank_error(status, row)) {
336 n = snprintf(buffer, size, "%s%u",
337 (rows++ ? ", " : ""), row);
338
339 if (n < 0 || n >= size)
340 goto fail;
341
342 buffer += n;
343 size -= n;
344 total += n;
345 }
346 }
347
348 n = snprintf(buffer, size, "%s; ", rows ? "" : "None");
349
350 if (n < 0 || n >= size)
351 goto fail;
352
353 buffer += n;
354 size -= n;
355 total += n;
356
357 fail:
358 return total;
359}
360
361/**
362 * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
363 * @mci: A pointer to the EDAC memory controller instance associated
364 * with the checkbit message being generated.
365 * @status: A pointer to the ECC status structure to generate the
366 * message from.
367 * @buffer: A pointer to the buffer in which to generate the
368 * message.
369 * @size: The size, in bytes, of space available in buffer.
370 *
371 * This routine generates to the provided buffer the portion of the
372 * driver-unique report message associated with the ECCESS[CKBER]
373 * field of the specified ECC status.
374 *
375 * Returns the number of characters generated on success; otherwise, <
376 * 0 on error.
377 */
378static int
379ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci,
380 const struct ppc4xx_ecc_status *status,
381 char *buffer,
382 size_t size)
383{
384 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
385 const char *ckber = NULL;
386
387 switch (status->ecces & SDRAM_ECCES_CKBER_MASK) {
388 case SDRAM_ECCES_CKBER_NONE:
389 ckber = "None";
390 break;
391 case SDRAM_ECCES_CKBER_32_ECC_0_3:
392 ckber = "ECC0:3";
393 break;
394 case SDRAM_ECCES_CKBER_32_ECC_4_8:
395 switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) &
396 SDRAM_MCOPT1_WDTH_MASK) {
397 case SDRAM_MCOPT1_WDTH_16:
398 ckber = "ECC0:3";
399 break;
400 case SDRAM_MCOPT1_WDTH_32:
401 ckber = "ECC4:8";
402 break;
403 default:
404 ckber = "Unknown";
405 break;
406 }
407 break;
408 case SDRAM_ECCES_CKBER_32_ECC_0_8:
409 ckber = "ECC0:8";
410 break;
411 default:
412 ckber = "Unknown";
413 break;
414 }
415
416 return snprintf(buffer, size, "Checkbit Error: %s", ckber);
417}
418
419/**
420 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
421 * @mci: A pointer to the EDAC memory controller instance associated
422 * with the byte lane message being generated.
423 * @status: A pointer to the ECC status structure to generate the
424 * message from.
425 * @buffer: A pointer to the buffer in which to generate the
426 * message.
427 * @size: The size, in bytes, of space available in buffer.
428 *
429 * This routine generates to the provided buffer the portion of the
430 * driver-unique report message associated with the ECCESS[BNCE]
431 * field of the specified ECC status.
432 *
433 * Returns the number of characters generated on success; otherwise, <
434 * 0 on error.
435 */
436static int
437ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci,
438 const struct ppc4xx_ecc_status *status,
439 char *buffer,
440 size_t size)
441{
442 int n, total = 0;
443 unsigned int lane, lanes;
444 const unsigned int first_lane = 0;
445 const unsigned int lane_count = 16;
446
447 n = snprintf(buffer, size, "; Byte Lane Errors: ");
448
449 if (n < 0 || n >= size)
450 goto fail;
451
452 buffer += n;
453 size -= n;
454 total += n;
455
456 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
457 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
458 n = snprintf(buffer, size,
459 "%s%u",
460 (lanes++ ? ", " : ""), lane);
461
462 if (n < 0 || n >= size)
463 goto fail;
464
465 buffer += n;
466 size -= n;
467 total += n;
468 }
469 }
470
471 n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
472
473 if (n < 0 || n >= size)
474 goto fail;
475
476 buffer += n;
477 size -= n;
478 total += n;
479
480 fail:
481 return total;
482}
483
484/**
485 * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
486 * @mci: A pointer to the EDAC memory controller instance associated
487 * with the ECCES message being generated.
488 * @status: A pointer to the ECC status structure to generate the
489 * message from.
490 * @buffer: A pointer to the buffer in which to generate the
491 * message.
492 * @size: The size, in bytes, of space available in buffer.
493 *
494 * This routine generates to the provided buffer the portion of the
495 * driver-unique report message associated with the ECCESS register of
496 * the specified ECC status.
497 *
498 * Returns the number of characters generated on success; otherwise, <
499 * 0 on error.
500 */
501static int
502ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci,
503 const struct ppc4xx_ecc_status *status,
504 char *buffer,
505 size_t size)
506{
507 int n, total = 0;
508
509 n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size);
510
511 if (n < 0 || n >= size)
512 goto fail;
513
514 buffer += n;
515 size -= n;
516 total += n;
517
518 n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size);
519
520 if (n < 0 || n >= size)
521 goto fail;
522
523 buffer += n;
524 size -= n;
525 total += n;
526
527 n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size);
528
529 if (n < 0 || n >= size)
530 goto fail;
531
532 buffer += n;
533 size -= n;
534 total += n;
535
536 fail:
537 return total;
538}
539
540/**
541 * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
542 * @mci: A pointer to the EDAC memory controller instance associated
543 * with the PLB message being generated.
544 * @status: A pointer to the ECC status structure to generate the
545 * message from.
546 * @buffer: A pointer to the buffer in which to generate the
547 * message.
548 * @size: The size, in bytes, of space available in buffer.
549 *
550 * This routine generates to the provided buffer the portion of the
551 * driver-unique report message associated with the PLB-related BESR
552 * and/or WMIRQ registers of the specified ECC status.
553 *
554 * Returns the number of characters generated on success; otherwise, <
555 * 0 on error.
556 */
557static int
558ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci,
559 const struct ppc4xx_ecc_status *status,
560 char *buffer,
561 size_t size)
562{
563 unsigned int master;
564 bool read;
565
566 if ((status->besr & SDRAM_BESR_MASK) == 0)
567 return 0;
568
569 if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE)
570 return 0;
571
572 read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ);
573
574 master = SDRAM_BESR_M0ID_DECODE(status->besr);
575
576 return snprintf(buffer, size,
577 "%s error w/ PLB master %u \"%s\"; ",
578 (read ? "Read" : "Write"),
579 master,
580 (((master >= SDRAM_PLB_M0ID_FIRST) &&
581 (master <= SDRAM_PLB_M0ID_LAST)) ?
582 ppc4xx_plb_masters[master] : "UNKNOWN"));
583}
584
585/**
586 * ppc4xx_edac_generate_message - generate interpretted status message
587 * @mci: A pointer to the EDAC memory controller instance associated
588 * with the driver-unique message being generated.
589 * @status: A pointer to the ECC status structure to generate the
590 * message from.
591 * @buffer: A pointer to the buffer in which to generate the
592 * message.
593 * @size: The size, in bytes, of space available in buffer.
594 *
595 * This routine generates to the provided buffer the driver-unique
596 * EDAC report message from the specified ECC status.
597 */
598static void
599ppc4xx_edac_generate_message(const struct mem_ctl_info *mci,
600 const struct ppc4xx_ecc_status *status,
601 char *buffer,
602 size_t size)
603{
604 int n;
605
606 if (buffer == NULL || size == 0)
607 return;
608
609 n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size);
610
611 if (n < 0 || n >= size)
612 return;
613
614 buffer += n;
615 size -= n;
616
617 ppc4xx_edac_generate_plb_message(mci, status, buffer, size);
618}
619
620#ifdef DEBUG
621/**
622 * ppc4xx_ecc_dump_status - dump controller ECC status registers
623 * @mci: A pointer to the EDAC memory controller instance
624 * associated with the status being dumped.
625 * @status: A pointer to the ECC status structure to generate the
626 * dump from.
627 *
628 * This routine dumps to the kernel log buffer the raw and
629 * interpretted specified ECC status.
630 */
631static void
632ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci,
633 const struct ppc4xx_ecc_status *status)
634{
635 char message[PPC4XX_EDAC_MESSAGE_SIZE];
636
637 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
638
639 ppc4xx_edac_mc_printk(KERN_INFO, mci,
640 "\n"
641 "\tECCES: 0x%08x\n"
642 "\tWMIRQ: 0x%08x\n"
643 "\tBESR: 0x%08x\n"
644 "\tBEAR: 0x%08x%08x\n"
645 "\t%s\n",
646 status->ecces,
647 status->wmirq,
648 status->besr,
649 status->bearh,
650 status->bearl,
651 message);
652}
653#endif /* DEBUG */
654
655/**
656 * ppc4xx_ecc_get_status - get controller ECC status
657 * @mci: A pointer to the EDAC memory controller instance
658 * associated with the status being retrieved.
659 * @status: A pointer to the ECC status structure to populate the
660 * ECC status with.
661 *
662 * This routine reads and masks, as appropriate, all the relevant
663 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
664 * While we read all of them, for correctable errors, we only expect
665 * to deal with ECCES. For uncorrectable errors, we expect to deal
666 * with all of them.
667 */
668static void
669ppc4xx_ecc_get_status(const struct mem_ctl_info *mci,
670 struct ppc4xx_ecc_status *status)
671{
672 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
673 const dcr_host_t *dcr_host = &pdata->dcr_host;
674
675 status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK;
676 status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK;
677 status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK;
678 status->bearl = mfsdram(dcr_host, SDRAM_BEARL);
679 status->bearh = mfsdram(dcr_host, SDRAM_BEARH);
680}
681
682/**
683 * ppc4xx_ecc_clear_status - clear controller ECC status
684 * @mci: A pointer to the EDAC memory controller instance
685 * associated with the status being cleared.
686 * @status: A pointer to the ECC status structure containing the
687 * values to write to clear the ECC status.
688 *
689 * This routine clears--by writing the masked (as appropriate) status
690 * values back to--the status registers that deal with
691 * ibm,sdram-4xx-ddr2 ECC errors.
692 */
693static void
694ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci,
695 const struct ppc4xx_ecc_status *status)
696{
697 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
698 const dcr_host_t *dcr_host = &pdata->dcr_host;
699
700 mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK);
701 mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK);
702 mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK);
703 mtsdram(dcr_host, SDRAM_BEARL, 0);
704 mtsdram(dcr_host, SDRAM_BEARH, 0);
705}
706
707/**
708 * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
709 * @mci: A pointer to the EDAC memory controller instance
710 * associated with the correctable error being handled and reported.
711 * @status: A pointer to the ECC status structure associated with
712 * the correctable error being handled and reported.
713 *
714 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
715 * correctable error. Per the aforementioned discussion, there's not
716 * enough status available to use the full EDAC correctable error
717 * interface, so we just pass driver-unique message to the "no info"
718 * interface.
719 */
720static void
721ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
722 const struct ppc4xx_ecc_status *status)
723{
724 int row;
725 char message[PPC4XX_EDAC_MESSAGE_SIZE];
726
727 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
728
729 for (row = 0; row < mci->nr_csrows; row++)
730 if (ppc4xx_edac_check_bank_error(status, row))
731 edac_mc_handle_ce_no_info(mci, message);
732}
733
734/**
735 * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
736 * @mci: A pointer to the EDAC memory controller instance
737 * associated with the uncorrectable error being handled and
738 * reported.
739 * @status: A pointer to the ECC status structure associated with
740 * the uncorrectable error being handled and reported.
741 *
742 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
743 * uncorrectable error.
744 */
745static void
746ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
747 const struct ppc4xx_ecc_status *status)
748{
749 const u64 bear = ((u64)status->bearh << 32 | status->bearl);
750 const unsigned long page = bear >> PAGE_SHIFT;
751 const unsigned long offset = bear & ~PAGE_MASK;
752 int row;
753 char message[PPC4XX_EDAC_MESSAGE_SIZE];
754
755 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
756
757 for (row = 0; row < mci->nr_csrows; row++)
758 if (ppc4xx_edac_check_bank_error(status, row))
759 edac_mc_handle_ue(mci, page, offset, row, message);
760}
761
762/**
763 * ppc4xx_edac_check - check controller for ECC errors
764 * @mci: A pointer to the EDAC memory controller instance
765 * associated with the ibm,sdram-4xx-ddr2 controller being
766 * checked.
767 *
768 * This routine is used to check and post ECC errors and is called by
769 * both the EDAC polling thread and this driver's CE and UE interrupt
770 * handler.
771 */
772static void
773ppc4xx_edac_check(struct mem_ctl_info *mci)
774{
775#ifdef DEBUG
776 static unsigned int count;
777#endif
778 struct ppc4xx_ecc_status status;
779
780 ppc4xx_ecc_get_status(mci, &status);
781
782#ifdef DEBUG
783 if (count++ % 30 == 0)
784 ppc4xx_ecc_dump_status(mci, &status);
785#endif
786
787 if (status.ecces & SDRAM_ECCES_UE)
788 ppc4xx_edac_handle_ue(mci, &status);
789
790 if (status.ecces & SDRAM_ECCES_CE)
791 ppc4xx_edac_handle_ce(mci, &status);
792
793 ppc4xx_ecc_clear_status(mci, &status);
794}
795
796/**
797 * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
798 * @irq: The virtual interrupt number being serviced.
799 * @dev_id: A pointer to the EDAC memory controller instance
800 * associated with the interrupt being handled.
801 *
802 * This routine implements the interrupt handler for both correctable
803 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
804 * controller. It simply calls through to the same routine used during
805 * polling to check, report and clear the ECC status.
806 *
807 * Unconditionally returns IRQ_HANDLED.
808 */
809static irqreturn_t
810ppc4xx_edac_isr(int irq, void *dev_id)
811{
812 struct mem_ctl_info *mci = dev_id;
813
814 ppc4xx_edac_check(mci);
815
816 return IRQ_HANDLED;
817}
818
819/**
820 * ppc4xx_edac_get_dtype - return the controller memory width
821 * @mcopt1: The 32-bit Memory Controller Option 1 register value
822 * currently set for the controller, from which the width
823 * is derived.
824 *
825 * This routine returns the EDAC device type width appropriate for the
826 * current controller configuration.
827 *
828 * TODO: This needs to be conditioned dynamically through feature
829 * flags or some such when other controller variants are supported as
830 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
831 * 16- and 64-bit field definition/value/enumeration (b1) overloaded
832 * among them.
833 *
834 * Returns a device type width enumeration.
835 */
836static enum dev_type __devinit
837ppc4xx_edac_get_dtype(u32 mcopt1)
838{
839 switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) {
840 case SDRAM_MCOPT1_WDTH_16:
841 return DEV_X2;
842 case SDRAM_MCOPT1_WDTH_32:
843 return DEV_X4;
844 default:
845 return DEV_UNKNOWN;
846 }
847}
848
849/**
850 * ppc4xx_edac_get_mtype - return controller memory type
851 * @mcopt1: The 32-bit Memory Controller Option 1 register value
852 * currently set for the controller, from which the memory type
853 * is derived.
854 *
855 * This routine returns the EDAC memory type appropriate for the
856 * current controller configuration.
857 *
858 * Returns a memory type enumeration.
859 */
860static enum mem_type __devinit
861ppc4xx_edac_get_mtype(u32 mcopt1)
862{
863 bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN);
864
865 switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) {
866 case SDRAM_MCOPT1_DDR2_TYPE:
867 return rden ? MEM_RDDR2 : MEM_DDR2;
868 case SDRAM_MCOPT1_DDR1_TYPE:
869 return rden ? MEM_RDDR : MEM_DDR;
870 default:
871 return MEM_UNKNOWN;
872 }
873}
874
875/**
876 * ppc4xx_edac_init_csrows - intialize driver instance rows
877 * @mci: A pointer to the EDAC memory controller instance
878 * associated with the ibm,sdram-4xx-ddr2 controller for which
879 * the csrows (i.e. banks/ranks) are being initialized.
880 * @mcopt1: The 32-bit Memory Controller Option 1 register value
881 * currently set for the controller, from which bank width
882 * and memory typ information is derived.
883 *
884 * This routine intializes the virtual "chip select rows" associated
885 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
886 * controller bank/rank is mapped to a row.
887 *
888 * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
889 * configuration cannot be determined.
890 */
891static int __devinit
892ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
893{
894 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
895 int status = 0;
896 enum mem_type mtype;
897 enum dev_type dtype;
898 enum edac_type edac_mode;
899 int row;
900 u32 mbxcf, size;
901 static u32 ppc4xx_last_page;
902
903 /* Establish the memory type and width */
904
905 mtype = ppc4xx_edac_get_mtype(mcopt1);
906 dtype = ppc4xx_edac_get_dtype(mcopt1);
907
908 /* Establish EDAC mode */
909
910 if (mci->edac_cap & EDAC_FLAG_SECDED)
911 edac_mode = EDAC_SECDED;
912 else if (mci->edac_cap & EDAC_FLAG_EC)
913 edac_mode = EDAC_EC;
914 else
915 edac_mode = EDAC_NONE;
916
917 /*
918 * Initialize each chip select row structure which correspond
919 * 1:1 with a controller bank/rank.
920 */
921
922 for (row = 0; row < mci->nr_csrows; row++) {
923 struct csrow_info *csi = &mci->csrows[row];
924
925 /*
926 * Get the configuration settings for this
927 * row/bank/rank and skip disabled banks.
928 */
929
930 mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row));
931
932 if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE)
933 continue;
934
935 /* Map the bank configuration size setting to pages. */
936
937 size = mbxcf & SDRAM_MBCF_SZ_MASK;
938
939 switch (size) {
940 case SDRAM_MBCF_SZ_4MB:
941 case SDRAM_MBCF_SZ_8MB:
942 case SDRAM_MBCF_SZ_16MB:
943 case SDRAM_MBCF_SZ_32MB:
944 case SDRAM_MBCF_SZ_64MB:
945 case SDRAM_MBCF_SZ_128MB:
946 case SDRAM_MBCF_SZ_256MB:
947 case SDRAM_MBCF_SZ_512MB:
948 case SDRAM_MBCF_SZ_1GB:
949 case SDRAM_MBCF_SZ_2GB:
950 case SDRAM_MBCF_SZ_4GB:
951 case SDRAM_MBCF_SZ_8GB:
952 csi->nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
953 break;
954 default:
955 ppc4xx_edac_mc_printk(KERN_ERR, mci,
956 "Unrecognized memory bank %d "
957 "size 0x%08x\n",
958 row, SDRAM_MBCF_SZ_DECODE(size));
959 status = -EINVAL;
960 goto done;
961 }
962
963 csi->first_page = ppc4xx_last_page;
964 csi->last_page = csi->first_page + csi->nr_pages - 1;
965 csi->page_mask = 0;
966
967 /*
968 * It's unclear exactly what grain should be set to
969 * here. The SDRAM_ECCES register allows resolution of
970 * an error down to a nibble which would potentially
971 * argue for a grain of '1' byte, even though we only
972 * know the associated address for uncorrectable
973 * errors. This value is not used at present for
974 * anything other than error reporting so getting it
975 * wrong should be of little consequence. Other
976 * possible values would be the PLB width (16), the
977 * page size (PAGE_SIZE) or the memory width (2 or 4).
978 */
979
980 csi->grain = 1;
981
982 csi->mtype = mtype;
983 csi->dtype = dtype;
984
985 csi->edac_mode = edac_mode;
986
987 ppc4xx_last_page += csi->nr_pages;
988 }
989
990 done:
991 return status;
992}
993
994/**
995 * ppc4xx_edac_mc_init - intialize driver instance
996 * @mci: A pointer to the EDAC memory controller instance being
997 * initialized.
998 * @op: A pointer to the OpenFirmware device tree node associated
999 * with the controller this EDAC instance is bound to.
1000 * @match: A pointer to the OpenFirmware device tree match
1001 * information associated with the controller this EDAC instance
1002 * is bound to.
1003 * @dcr_host: A pointer to the DCR data containing the DCR mapping
1004 * for this controller instance.
1005 * @mcopt1: The 32-bit Memory Controller Option 1 register value
1006 * currently set for the controller, from which ECC capabilities
1007 * and scrub mode are derived.
1008 *
1009 * This routine performs initialization of the EDAC memory controller
1010 * instance and related driver-private data associated with the
1011 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
1012 *
1013 * Returns 0 if OK; otherwise, < 0 on error.
1014 */
1015static int __devinit
1016ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
1017 struct of_device *op,
1018 const struct of_device_id *match,
1019 const dcr_host_t *dcr_host,
1020 u32 mcopt1)
1021{
1022 int status = 0;
1023 const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1024 struct ppc4xx_edac_pdata *pdata = NULL;
1025 const struct device_node *np = op->node;
1026
1027 if (match == NULL)
1028 return -EINVAL;
1029
1030 /* Initial driver pointers and private data */
1031
1032 mci->dev = &op->dev;
1033
1034 dev_set_drvdata(mci->dev, mci);
1035
1036 pdata = mci->pvt_info;
1037
1038 pdata->dcr_host = *dcr_host;
1039 pdata->irqs.sec = NO_IRQ;
1040 pdata->irqs.ded = NO_IRQ;
1041
1042 /* Initialize controller capabilities and configuration */
1043
1044 mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR |
1045 MEM_FLAG_DDR2 | MEM_FLAG_RDDR2);
1046
1047 mci->edac_ctl_cap = (EDAC_FLAG_NONE |
1048 EDAC_FLAG_EC |
1049 EDAC_FLAG_SECDED);
1050
1051 mci->scrub_cap = SCRUB_NONE;
1052 mci->scrub_mode = SCRUB_NONE;
1053
1054 /*
1055 * Update the actual capabilites based on the MCOPT1[MCHK]
1056 * settings. Scrubbing is only useful if reporting is enabled.
1057 */
1058
1059 switch (memcheck) {
1060 case SDRAM_MCOPT1_MCHK_CHK:
1061 mci->edac_cap = EDAC_FLAG_EC;
1062 break;
1063 case SDRAM_MCOPT1_MCHK_CHK_REP:
1064 mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED);
1065 mci->scrub_mode = SCRUB_SW_SRC;
1066 break;
1067 default:
1068 mci->edac_cap = EDAC_FLAG_NONE;
1069 break;
1070 }
1071
1072 /* Initialize strings */
1073
1074 mci->mod_name = PPC4XX_EDAC_MODULE_NAME;
1075 mci->mod_ver = PPC4XX_EDAC_MODULE_REVISION;
1076 mci->ctl_name = match->compatible,
1077 mci->dev_name = np->full_name;
1078
1079 /* Initialize callbacks */
1080
1081 mci->edac_check = ppc4xx_edac_check;
1082 mci->ctl_page_to_phys = NULL;
1083
1084 /* Initialize chip select rows */
1085
1086 status = ppc4xx_edac_init_csrows(mci, mcopt1);
1087
1088 if (status)
1089 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1090 "Failed to initialize rows!\n");
1091
1092 return status;
1093}
1094
1095/**
1096 * ppc4xx_edac_register_irq - setup and register controller interrupts
1097 * @op: A pointer to the OpenFirmware device tree node associated
1098 * with the controller this EDAC instance is bound to.
1099 * @mci: A pointer to the EDAC memory controller instance
1100 * associated with the ibm,sdram-4xx-ddr2 controller for which
1101 * interrupts are being registered.
1102 *
1103 * This routine parses the correctable (CE) and uncorrectable error (UE)
1104 * interrupts from the device tree node and maps and assigns them to
1105 * the associated EDAC memory controller instance.
1106 *
1107 * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1108 * mapped and assigned.
1109 */
1110static int __devinit
1111ppc4xx_edac_register_irq(struct of_device *op, struct mem_ctl_info *mci)
1112{
1113 int status = 0;
1114 int ded_irq, sec_irq;
1115 struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1116 struct device_node *np = op->node;
1117
1118 ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX);
1119 sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX);
1120
1121 if (ded_irq == NO_IRQ || sec_irq == NO_IRQ) {
1122 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1123 "Unable to map interrupts.\n");
1124 status = -ENODEV;
1125 goto fail;
1126 }
1127
1128 status = request_irq(ded_irq,
1129 ppc4xx_edac_isr,
1130 IRQF_DISABLED,
1131 "[EDAC] MC ECCDED",
1132 mci);
1133
1134 if (status < 0) {
1135 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1136 "Unable to request irq %d for ECC DED",
1137 ded_irq);
1138 status = -ENODEV;
1139 goto fail1;
1140 }
1141
1142 status = request_irq(sec_irq,
1143 ppc4xx_edac_isr,
1144 IRQF_DISABLED,
1145 "[EDAC] MC ECCSEC",
1146 mci);
1147
1148 if (status < 0) {
1149 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1150 "Unable to request irq %d for ECC SEC",
1151 sec_irq);
1152 status = -ENODEV;
1153 goto fail2;
1154 }
1155
1156 ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq);
1157 ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq);
1158
1159 pdata->irqs.ded = ded_irq;
1160 pdata->irqs.sec = sec_irq;
1161
1162 return 0;
1163
1164 fail2:
1165 free_irq(sec_irq, mci);
1166
1167 fail1:
1168 free_irq(ded_irq, mci);
1169
1170 fail:
1171 return status;
1172}
1173
1174/**
1175 * ppc4xx_edac_map_dcrs - locate and map controller registers
1176 * @np: A pointer to the device tree node containing the DCR
1177 * resources to map.
1178 * @dcr_host: A pointer to the DCR data to populate with the
1179 * DCR mapping.
1180 *
1181 * This routine attempts to locate in the device tree and map the DCR
1182 * register resources associated with the controller's indirect DCR
1183 * address and data windows.
1184 *
1185 * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on
1186 * error.
1187 */
1188static int __devinit
1189ppc4xx_edac_map_dcrs(const struct device_node *np, dcr_host_t *dcr_host)
1190{
1191 unsigned int dcr_base, dcr_len;
1192
1193 if (np == NULL || dcr_host == NULL)
1194 return -EINVAL;
1195
1196 /* Get the DCR resource extent and sanity check the values. */
1197
1198 dcr_base = dcr_resource_start(np, 0);
1199 dcr_len = dcr_resource_len(np, 0);
1200
1201 if (dcr_base == 0 || dcr_len == 0) {
1202 ppc4xx_edac_printk(KERN_ERR,
1203 "Failed to obtain DCR property.\n");
1204 return -ENODEV;
1205 }
1206
1207 if (dcr_len != SDRAM_DCR_RESOURCE_LEN) {
1208 ppc4xx_edac_printk(KERN_ERR,
1209 "Unexpected DCR length %d, expected %d.\n",
1210 dcr_len, SDRAM_DCR_RESOURCE_LEN);
1211 return -ENODEV;
1212 }
1213
1214 /* Attempt to map the DCR extent. */
1215
1216 *dcr_host = dcr_map(np, dcr_base, dcr_len);
1217
1218 if (!DCR_MAP_OK(*dcr_host)) {
1219 ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n");
1220 return -ENODEV;
1221 }
1222
1223 return 0;
1224}
1225
1226/**
1227 * ppc4xx_edac_probe - check controller and bind driver
1228 * @op: A pointer to the OpenFirmware device tree node associated
1229 * with the controller being probed for driver binding.
1230 * @match: A pointer to the OpenFirmware device tree match
1231 * information associated with the controller being probed
1232 * for driver binding.
1233 *
1234 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1235 * instance for binding with the driver.
1236 *
1237 * Returns 0 if the controller instance was successfully bound to the
1238 * driver; otherwise, < 0 on error.
1239 */
1240static int __devinit
1241ppc4xx_edac_probe(struct of_device *op, const struct of_device_id *match)
1242{
1243 int status = 0;
1244 u32 mcopt1, memcheck;
1245 dcr_host_t dcr_host;
1246 const struct device_node *np = op->node;
1247 struct mem_ctl_info *mci = NULL;
1248 static int ppc4xx_edac_instance;
1249
1250 /*
1251 * At this point, we only support the controller realized on
1252 * the AMCC PPC 405EX[r]. Reject anything else.
1253 */
1254
1255 if (!of_device_is_compatible(np, "ibm,sdram-405ex") &&
1256 !of_device_is_compatible(np, "ibm,sdram-405exr")) {
1257 ppc4xx_edac_printk(KERN_NOTICE,
1258 "Only the PPC405EX[r] is supported.\n");
1259 return -ENODEV;
1260 }
1261
1262 /*
1263 * Next, get the DCR property and attempt to map it so that we
1264 * can probe the controller.
1265 */
1266
1267 status = ppc4xx_edac_map_dcrs(np, &dcr_host);
1268
1269 if (status)
1270 return status;
1271
1272 /*
1273 * First determine whether ECC is enabled at all. If not,
1274 * there is no useful checking or monitoring that can be done
1275 * for this controller.
1276 */
1277
1278 mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1);
1279 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1280
1281 if (memcheck == SDRAM_MCOPT1_MCHK_NON) {
1282 ppc4xx_edac_printk(KERN_INFO, "%s: No ECC memory detected or "
1283 "ECC is disabled.\n", np->full_name);
1284 status = -ENODEV;
1285 goto done;
1286 }
1287
1288 /*
1289 * At this point, we know ECC is enabled, allocate an EDAC
1290 * controller instance and perform the appropriate
1291 * initialization.
1292 */
1293
1294 mci = edac_mc_alloc(sizeof(struct ppc4xx_edac_pdata),
1295 ppc4xx_edac_nr_csrows,
1296 ppc4xx_edac_nr_chans,
1297 ppc4xx_edac_instance);
1298
1299 if (mci == NULL) {
1300 ppc4xx_edac_printk(KERN_ERR, "%s: "
1301 "Failed to allocate EDAC MC instance!\n",
1302 np->full_name);
1303 status = -ENOMEM;
1304 goto done;
1305 }
1306
1307 status = ppc4xx_edac_mc_init(mci, op, match, &dcr_host, mcopt1);
1308
1309 if (status) {
1310 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1311 "Failed to initialize instance!\n");
1312 goto fail;
1313 }
1314
1315 /*
1316 * We have a valid, initialized EDAC instance bound to the
1317 * controller. Attempt to register it with the EDAC subsystem
1318 * and, if necessary, register interrupts.
1319 */
1320
1321 if (edac_mc_add_mc(mci)) {
1322 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1323 "Failed to add instance!\n");
1324 status = -ENODEV;
1325 goto fail;
1326 }
1327
1328 if (edac_op_state == EDAC_OPSTATE_INT) {
1329 status = ppc4xx_edac_register_irq(op, mci);
1330
1331 if (status)
1332 goto fail1;
1333 }
1334
1335 ppc4xx_edac_instance++;
1336
1337 return 0;
1338
1339 fail1:
1340 edac_mc_del_mc(mci->dev);
1341
1342 fail:
1343 edac_mc_free(mci);
1344
1345 done:
1346 return status;
1347}
1348
1349/**
1350 * ppc4xx_edac_remove - unbind driver from controller
1351 * @op: A pointer to the OpenFirmware device tree node associated
1352 * with the controller this EDAC instance is to be unbound/removed
1353 * from.
1354 *
1355 * This routine unbinds the EDAC memory controller instance associated
1356 * with the specified ibm,sdram-4xx-ddr2 controller described by the
1357 * OpenFirmware device tree node passed as a parameter.
1358 *
1359 * Unconditionally returns 0.
1360 */
1361static int
1362ppc4xx_edac_remove(struct of_device *op)
1363{
1364 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1365 struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1366
1367 if (edac_op_state == EDAC_OPSTATE_INT) {
1368 free_irq(pdata->irqs.sec, mci);
1369 free_irq(pdata->irqs.ded, mci);
1370 }
1371
1372 dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN);
1373
1374 edac_mc_del_mc(mci->dev);
1375 edac_mc_free(mci);
1376
1377 return 0;
1378}
1379
1380/**
1381 * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1382 *
1383 * This routine ensures that the EDAC memory controller reporting
1384 * method is mapped to a sane value as the EDAC core defines the value
1385 * to EDAC_OPSTATE_INVAL by default. We don't call the global
1386 * opstate_init as that defaults to polling and we want interrupt as
1387 * the default.
1388 */
1389static inline void __init
1390ppc4xx_edac_opstate_init(void)
1391{
1392 switch (edac_op_state) {
1393 case EDAC_OPSTATE_POLL:
1394 case EDAC_OPSTATE_INT:
1395 break;
1396 default:
1397 edac_op_state = EDAC_OPSTATE_INT;
1398 break;
1399 }
1400
1401 ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n",
1402 ((edac_op_state == EDAC_OPSTATE_POLL) ?
1403 EDAC_OPSTATE_POLL_STR :
1404 ((edac_op_state == EDAC_OPSTATE_INT) ?
1405 EDAC_OPSTATE_INT_STR :
1406 EDAC_OPSTATE_UNKNOWN_STR)));
1407}
1408
1409/**
1410 * ppc4xx_edac_init - driver/module insertion entry point
1411 *
1412 * This routine is the driver/module insertion entry point. It
1413 * initializes the EDAC memory controller reporting state and
1414 * registers the driver as an OpenFirmware device tree platform
1415 * driver.
1416 */
1417static int __init
1418ppc4xx_edac_init(void)
1419{
1420 ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n");
1421
1422 ppc4xx_edac_opstate_init();
1423
1424 return of_register_platform_driver(&ppc4xx_edac_driver);
1425}
1426
1427/**
1428 * ppc4xx_edac_exit - driver/module removal entry point
1429 *
1430 * This routine is the driver/module removal entry point. It
1431 * unregisters the driver as an OpenFirmware device tree platform
1432 * driver.
1433 */
1434static void __exit
1435ppc4xx_edac_exit(void)
1436{
1437 of_unregister_platform_driver(&ppc4xx_edac_driver);
1438}
1439
1440module_init(ppc4xx_edac_init);
1441module_exit(ppc4xx_edac_exit);
1442
1443MODULE_LICENSE("GPL v2");
1444MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
1445MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
1446module_param(edac_op_state, int, 0444);
1447MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: "
1448 "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);
diff --git a/drivers/edac/ppc4xx_edac.h b/drivers/edac/ppc4xx_edac.h
new file mode 100644
index 000000000000..d3154764c449
--- /dev/null
+++ b/drivers/edac/ppc4xx_edac.h
@@ -0,0 +1,172 @@
1/*
2 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
4 *
5 * This file defines processor mnemonics for accessing and managing
6 * the IBM DDR1/DDR2 ECC controller found in the 405EX[r], 440SP,
7 * 440SPe, 460EX, 460GT and 460SX.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 */
15
16#ifndef __PPC4XX_EDAC_H
17#define __PPC4XX_EDAC_H
18
19#include <linux/types.h>
20
21/*
22 * Macro for generating register field mnemonics
23 */
24#define PPC_REG_BITS 32
25#define PPC_REG_VAL(bit, val) ((val) << ((PPC_REG_BITS - 1) - (bit)))
26#define PPC_REG_DECODE(bit, val) ((val) >> ((PPC_REG_BITS - 1) - (bit)))
27
28/*
29 * IBM 4xx DDR1/DDR2 SDRAM memory controller registers (at least those
30 * relevant to ECC)
31 */
32#define SDRAM_BESR 0x00 /* Error status (read/clear) */
33#define SDRAM_BESRT 0x01 /* Error statuss (test/set) */
34#define SDRAM_BEARL 0x02 /* Error address low */
35#define SDRAM_BEARH 0x03 /* Error address high */
36#define SDRAM_WMIRQ 0x06 /* Write master (read/clear) */
37#define SDRAM_WMIRQT 0x07 /* Write master (test/set) */
38#define SDRAM_MCOPT1 0x20 /* Controller options 1 */
39#define SDRAM_MBXCF_BASE 0x40 /* Bank n configuration base */
40#define SDRAM_MBXCF(n) (SDRAM_MBXCF_BASE + (4 * (n)))
41#define SDRAM_MB0CF SDRAM_MBXCF(0)
42#define SDRAM_MB1CF SDRAM_MBXCF(1)
43#define SDRAM_MB2CF SDRAM_MBXCF(2)
44#define SDRAM_MB3CF SDRAM_MBXCF(3)
45#define SDRAM_ECCCR 0x98 /* ECC error status */
46#define SDRAM_ECCES SDRAM_ECCCR
47
48/*
49 * PLB Master IDs
50 */
51#define SDRAM_PLB_M0ID_FIRST 0
52#define SDRAM_PLB_M0ID_ICU SDRAM_PLB_M0ID_FIRST
53#define SDRAM_PLB_M0ID_PCIE0 1
54#define SDRAM_PLB_M0ID_PCIE1 2
55#define SDRAM_PLB_M0ID_DMA 3
56#define SDRAM_PLB_M0ID_DCU 4
57#define SDRAM_PLB_M0ID_OPB 5
58#define SDRAM_PLB_M0ID_MAL 6
59#define SDRAM_PLB_M0ID_SEC 7
60#define SDRAM_PLB_M0ID_AHB 8
61#define SDRAM_PLB_M0ID_LAST SDRAM_PLB_M0ID_AHB
62#define SDRAM_PLB_M0ID_COUNT (SDRAM_PLB_M0ID_LAST - \
63 SDRAM_PLB_M0ID_FIRST + 1)
64
65/*
66 * Memory Controller Bus Error Status Register
67 */
68#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
69#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
70#define SDRAM_BESR_M0ID_DECODE(n) PPC_REG_DECODE(3, n)
71#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, SDRAM_PLB_M0ID_ICU)
72#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE0)
73#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE1)
74#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, SDRAM_PLB_M0ID_DMA)
75#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, SDRAM_PLB_M0ID_DCU)
76#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, SDRAM_PLB_M0ID_OPB)
77#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, SDRAM_PLB_M0ID_MAL)
78#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, SDRAM_PLB_M0ID_SEC)
79#define SDRAM_BESR_M0ID_AHB PPC_REG_VAL(3, SDRAM_PLB_M0ID_AHB)
80#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
81#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0)
82#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 1)
83#define SDRAM_BESR_M0RW_MASK PPC_REG_VAL(7, 1)
84#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
85#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(7, 1)
86
87/*
88 * Memory Controller PLB Write Master Interrupt Register
89 */
90#define SDRAM_WMIRQ_MASK PPC_REG_VAL(8, 0x1FF)
91#define SDRAM_WMIRQ_ENCODE(id) PPC_REG_VAL((id % \
92 SDRAM_PLB_M0ID_COUNT), 1)
93#define SDRAM_WMIRQ_ICU PPC_REG_VAL(SDRAM_PLB_M0ID_ICU, 1)
94#define SDRAM_WMIRQ_PCIE0 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE0, 1)
95#define SDRAM_WMIRQ_PCIE1 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE1, 1)
96#define SDRAM_WMIRQ_DMA PPC_REG_VAL(SDRAM_PLB_M0ID_DMA, 1)
97#define SDRAM_WMIRQ_DCU PPC_REG_VAL(SDRAM_PLB_M0ID_DCU, 1)
98#define SDRAM_WMIRQ_OPB PPC_REG_VAL(SDRAM_PLB_M0ID_OPB, 1)
99#define SDRAM_WMIRQ_MAL PPC_REG_VAL(SDRAM_PLB_M0ID_MAL, 1)
100#define SDRAM_WMIRQ_SEC PPC_REG_VAL(SDRAM_PLB_M0ID_SEC, 1)
101#define SDRAM_WMIRQ_AHB PPC_REG_VAL(SDRAM_PLB_M0ID_AHB, 1)
102
103/*
104 * Memory Controller Options 1 Register
105 */
106#define SDRAM_MCOPT1_MCHK_MASK PPC_REG_VAL(3, 0x3) /* ECC mask */
107#define SDRAM_MCOPT1_MCHK_NON PPC_REG_VAL(3, 0x0) /* No ECC gen */
108#define SDRAM_MCOPT1_MCHK_GEN PPC_REG_VAL(3, 0x2) /* ECC gen */
109#define SDRAM_MCOPT1_MCHK_CHK PPC_REG_VAL(3, 0x1) /* ECC gen and chk */
110#define SDRAM_MCOPT1_MCHK_CHK_REP PPC_REG_VAL(3, 0x3) /* ECC gen/chk/rpt */
111#define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3)
112#define SDRAM_MCOPT1_RDEN_MASK PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM mask */
113#define SDRAM_MCOPT1_RDEN PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM enbl */
114#define SDRAM_MCOPT1_WDTH_MASK PPC_REG_VAL(7, 0x1) /* Width mask */
115#define SDRAM_MCOPT1_WDTH_32 PPC_REG_VAL(7, 0x0) /* 32 bits */
116#define SDRAM_MCOPT1_WDTH_16 PPC_REG_VAL(7, 0x1) /* 16 bits */
117#define SDRAM_MCOPT1_DDR_TYPE_MASK PPC_REG_VAL(11, 0x1) /* DDR type mask */
118#define SDRAM_MCOPT1_DDR1_TYPE PPC_REG_VAL(11, 0x0) /* DDR1 type */
119#define SDRAM_MCOPT1_DDR2_TYPE PPC_REG_VAL(11, 0x1) /* DDR2 type */
120
121/*
122 * Memory Bank 0 - n Configuration Register
123 */
124#define SDRAM_MBCF_BA_MASK PPC_REG_VAL(12, 0x1FFF)
125#define SDRAM_MBCF_SZ_MASK PPC_REG_VAL(19, 0xF)
126#define SDRAM_MBCF_SZ_DECODE(mbxcf) PPC_REG_DECODE(19, mbxcf)
127#define SDRAM_MBCF_SZ_4MB PPC_REG_VAL(19, 0x0)
128#define SDRAM_MBCF_SZ_8MB PPC_REG_VAL(19, 0x1)
129#define SDRAM_MBCF_SZ_16MB PPC_REG_VAL(19, 0x2)
130#define SDRAM_MBCF_SZ_32MB PPC_REG_VAL(19, 0x3)
131#define SDRAM_MBCF_SZ_64MB PPC_REG_VAL(19, 0x4)
132#define SDRAM_MBCF_SZ_128MB PPC_REG_VAL(19, 0x5)
133#define SDRAM_MBCF_SZ_256MB PPC_REG_VAL(19, 0x6)
134#define SDRAM_MBCF_SZ_512MB PPC_REG_VAL(19, 0x7)
135#define SDRAM_MBCF_SZ_1GB PPC_REG_VAL(19, 0x8)
136#define SDRAM_MBCF_SZ_2GB PPC_REG_VAL(19, 0x9)
137#define SDRAM_MBCF_SZ_4GB PPC_REG_VAL(19, 0xA)
138#define SDRAM_MBCF_SZ_8GB PPC_REG_VAL(19, 0xB)
139#define SDRAM_MBCF_AM_MASK PPC_REG_VAL(23, 0xF)
140#define SDRAM_MBCF_AM_MODE0 PPC_REG_VAL(23, 0x0)
141#define SDRAM_MBCF_AM_MODE1 PPC_REG_VAL(23, 0x1)
142#define SDRAM_MBCF_AM_MODE2 PPC_REG_VAL(23, 0x2)
143#define SDRAM_MBCF_AM_MODE3 PPC_REG_VAL(23, 0x3)
144#define SDRAM_MBCF_AM_MODE4 PPC_REG_VAL(23, 0x4)
145#define SDRAM_MBCF_AM_MODE5 PPC_REG_VAL(23, 0x5)
146#define SDRAM_MBCF_AM_MODE6 PPC_REG_VAL(23, 0x6)
147#define SDRAM_MBCF_AM_MODE7 PPC_REG_VAL(23, 0x7)
148#define SDRAM_MBCF_AM_MODE8 PPC_REG_VAL(23, 0x8)
149#define SDRAM_MBCF_AM_MODE9 PPC_REG_VAL(23, 0x9)
150#define SDRAM_MBCF_BE_MASK PPC_REG_VAL(31, 0x1)
151#define SDRAM_MBCF_BE_DISABLE PPC_REG_VAL(31, 0x0)
152#define SDRAM_MBCF_BE_ENABLE PPC_REG_VAL(31, 0x1)
153
154/*
155 * ECC Error Status
156 */
157#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
158#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
159#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
160#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
161#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
162#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2)
163#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1)
164#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2)
165#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3)
166#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1)
167#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
168#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
169#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1)
170#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1)
171
172#endif /* __PPC4XX_EDAC_H */
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