4 files changed, 40 insertions, 72 deletions

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 4f4ac82382f7..a38831c82649 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1122,7 +1122,7 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
                 debugf0("Reading K8_DRAM_BASE_LOW failed\n");
 
         /* Extract parts into separate data entries */
-        pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 24;
+        pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
         pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
         pvt->dram_rw_en[dram] = (low & 0x3);
 
@@ -1135,7 +1135,7 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
          * Extract parts into separate data entries. Limit is the HIGHEST memory
          * location of the region, so lower 24 bits need to be all ones
          */
-        pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 24) | 0x00FFFFFF;
+        pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
         pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
         pvt->dram_DstNode[dram] = (low & 0x7);
 }
@@ -1369,7 +1369,7 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
         pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
 
         pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) |
-                               (((u64)low_base  & 0xFFFF0000) << 24);
+                               (((u64)low_base  & 0xFFFF0000) << 8);
 
         low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
         high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
@@ -1391,7 +1391,7 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
          * memory location of the region, so low 24 bits need to be all ones.
          */
         pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) |
-                                (((u64) low_limit & 0xFFFF0000) << 24) |
+                                (((u64) low_limit & 0xFFFF0000) << 8) |
                                 0x00FFFFFF;
 }
 
@@ -2254,7 +2254,7 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
 {
         u32 ec  = ERROR_CODE(info->nbsl);
         u32 xec = EXT_ERROR_CODE(info->nbsl);
-        int ecc_type = info->nbsh & (0x3 << 13);
+        int ecc_type = (info->nbsh >> 13) & 0x3;
 
         /* Bail early out if this was an 'observed' error */
         if (PP(ec) == K8_NBSL_PP_OBS)
@@ -3163,7 +3163,7 @@ static int __init amd64_edac_init(void)
         opstate_init();
 
         if (cache_k8_northbridges() < 0)
-                goto err_exit;
+                return err;
 
         err = pci_register_driver(&amd64_pci_driver);
         if (err)
@@ -3189,8 +3189,6 @@ static int __init amd64_edac_init(void)
 
 err_2nd_stage:
         debugf0("2nd stage failed\n");
-
-err_exit:
         pci_unregister_driver(&amd64_pci_driver);
 
         return err;
diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c
index d335086f4a26..77a9579d7167 100644
--- a/drivers/edac/i5000_edac.c
+++ b/drivers/edac/i5000_edac.c
@@ -1173,7 +1173,7 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
                         pci_read_config_word(pvt->branch_1, where,
                                         &pvt->b1_mtr[slot_row]);
                         debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
-                                where, pvt->b0_mtr[slot_row]);
+                                where, pvt->b1_mtr[slot_row]);
                 } else {
                         pvt->b1_mtr[slot_row] = 0;
                 }
@@ -1232,7 +1232,7 @@ static int i5000_init_csrows(struct mem_ctl_info *mci)
         struct csrow_info *p_csrow;
         int empty, channel_count;
         int max_csrows;
-        int mtr;
+        int mtr, mtr1;
         int csrow_megs;
         int channel;
         int csrow;
@@ -1251,9 +1251,10 @@ static int i5000_init_csrows(struct mem_ctl_info *mci)
 
                 /* use branch 0 for the basis */
                 mtr = pvt->b0_mtr[csrow >> 1];
+                mtr1 = pvt->b1_mtr[csrow >> 1];
 
                 /* if no DIMMS on this row, continue */
-                if (!MTR_DIMMS_PRESENT(mtr))
+                if (!MTR_DIMMS_PRESENT(mtr) && !MTR_DIMMS_PRESENT(mtr1))
                         continue;
 
                 /* FAKE OUT VALUES, FIXME */
diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c
index b08b6d8e2dc7..f99d10655ed4 100644
--- a/drivers/edac/i5400_edac.c
+++ b/drivers/edac/i5400_edac.c
@@ -46,9 +46,10 @@
 /* Limits for i5400 */
 #define NUM_MTRS_PER_BRANCH     4
 #define CHANNELS_PER_BRANCH     2
+#define MAX_DIMMS_PER_CHANNEL   NUM_MTRS_PER_BRANCH
 #define MAX_CHANNELS            4
-#define MAX_DIMMS               (MAX_CHANNELS * 4)      /* Up to 4 DIMM's per channel */
-#define MAX_CSROWS              (MAX_DIMMS * 2)         /* max possible csrows per channel */
+/* max possible csrows per channel */
+#define MAX_CSROWS              (MAX_DIMMS_PER_CHANNEL)
 
 /* Device 16,
  * Function 0: System Address
@@ -331,7 +332,6 @@ static const struct i5400_dev_info i5400_devs[] = {
 
 struct i5400_dimm_info {
         int megabytes;          /* size, 0 means not present  */
-        int dual_rank;
 };
 
 /* driver private data structure */
@@ -849,11 +849,9 @@ static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
         int n;
 
         /* There is one MTR for each slot pair of FB-DIMMs,
-           Each slot may have one or two ranks (2 csrows),
            Each slot pair may be at branch 0 or branch 1.
-           So, csrow should be divided by eight
          */
-        n = csrow >> 3;
+        n = csrow;
 
         if (n >= NUM_MTRS_PER_BRANCH) {
                 debugf0("ERROR: trying to access an invalid csrow: %d\n",
@@ -905,25 +903,22 @@ static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel,
                 amb_present_reg = determine_amb_present_reg(pvt, channel);
 
                 /* Determine if there is a DIMM present in this DIMM slot */
-                if (amb_present_reg & (1 << (csrow >> 1))) {
-                        dinfo->dual_rank = MTR_DIMM_RANK(mtr);
-
-                        if (!((dinfo->dual_rank == 0) &&
-                                ((csrow & 0x1) == 0x1))) {
-                                /* Start with the number of bits for a Bank
-                                 * on the DRAM */
-                                addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
-                                /* Add thenumber of ROW bits */
-                                addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
-                                /* add the number of COLUMN bits */
-                                addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
-
-                                addrBits += 6;  /* add 64 bits per DIMM */
-                                addrBits -= 20; /* divide by 2^^20 */
-                                addrBits -= 3;  /* 8 bits per bytes */
-
-                                dinfo->megabytes = 1 << addrBits;
-                        }
+                if (amb_present_reg & (1 << csrow)) {
+                        /* Start with the number of bits for a Bank
+                         * on the DRAM */
+                        addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
+                        /* Add thenumber of ROW bits */
+                        addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
+                        /* add the number of COLUMN bits */
+                        addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
+                        /* add the number of RANK bits */
+                        addrBits += MTR_DIMM_RANK(mtr);
+
+                        addrBits += 6;  /* add 64 bits per DIMM */
+                        addrBits -= 20; /* divide by 2^^20 */
+                        addrBits -= 3;  /* 8 bits per bytes */
+
+                        dinfo->megabytes = 1 << addrBits;
                 }
         }
 }
@@ -951,12 +946,12 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
                 return;
         }
 
-        /* Scan all the actual CSROWS (which is # of DIMMS * 2)
+        /* Scan all the actual CSROWS
          * and calculate the information for each DIMM
          * Start with the highest csrow first, to display it first
          * and work toward the 0th csrow
          */
-        max_csrows = pvt->maxdimmperch * 2;
+        max_csrows = pvt->maxdimmperch;
         for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
 
                 /* on an odd csrow, first output a 'boundary' marker,
@@ -1064,7 +1059,7 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
 
         /* Get the set of MTR[0-3] regs by each branch */
         for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++) {
-                int where = MTR0 + (slot_row * sizeof(u32));
+                int where = MTR0 + (slot_row * sizeof(u16));
 
                 /* Branch 0 set of MTR registers */
                 pci_read_config_word(pvt->branch_0, where,
@@ -1146,7 +1141,7 @@ static int i5400_init_csrows(struct mem_ctl_info *mci)
         pvt = mci->pvt_info;
 
         channel_count = pvt->maxch;
-        max_csrows = pvt->maxdimmperch * 2;
+        max_csrows = pvt->maxdimmperch;
 
         empty = 1;              /* Assume NO memory */
 
@@ -1215,28 +1210,6 @@ static void i5400_enable_error_reporting(struct mem_ctl_info *mci)
 }
 
 /*
- * i5400_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
- *
- *      ask the device how many channels are present and how many CSROWS
- *       as well
- */
-static void i5400_get_dimm_and_channel_counts(struct pci_dev *pdev,
-                                        int *num_dimms_per_channel,
-                                        int *num_channels)
-{
-        u8 value;
-
-        /* Need to retrieve just how many channels and dimms per channel are
-         * supported on this memory controller
-         */
-        pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
-        *num_dimms_per_channel = (int)value * 2;
-
-        pci_read_config_byte(pdev, MAXCH, &value);
-        *num_channels = (int)value;
-}
-
-/*
  *      i5400_probe1    Probe for ONE instance of device to see if it is
  *                      present.
  *      return:
@@ -1263,22 +1236,16 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
         if (PCI_FUNC(pdev->devfn) != 0)
                 return -ENODEV;
 
-        /* Ask the devices for the number of CSROWS and CHANNELS so
-         * that we can calculate the memory resources, etc
-         *
-         * The Chipset will report what it can handle which will be greater
-         * or equal to what the motherboard manufacturer will implement.
-         *
-         * As we don't have a motherboard identification routine to determine
+        /* As we don't have a motherboard identification routine to determine
          * actual number of slots/dimms per channel, we thus utilize the
          * resource as specified by the chipset. Thus, we might have
          * have more DIMMs per channel than actually on the mobo, but this
          * allows the driver to support upto the chipset max, without
          * some fancy mobo determination.
          */
-        i5400_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
-                                        &num_channels);
-        num_csrows = num_dimms_per_channel * 2;
+        num_dimms_per_channel = MAX_DIMMS_PER_CHANNEL;
+        num_channels = MAX_CHANNELS;
+        num_csrows = num_dimms_per_channel;
 
         debugf0("MC: %s(): Number of - Channels= %d  DIMMS= %d  CSROWS= %d\n",
                 __func__, num_channels, num_dimms_per_channel, num_csrows);
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index 157f6504f25e..cf27402af97b 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -26,7 +26,9 @@
 #include "mpc85xx_edac.h"
 
 static int edac_dev_idx;
+#ifdef CONFIG_PCI
 static int edac_pci_idx;
+#endif
 static int edac_mc_idx;
 
 static u32 orig_ddr_err_disable;