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-rw-r--r--drivers/edac/i7core_edac.c43
1 files changed, 30 insertions, 13 deletions
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 62ae472c4e27..a6e798349e93 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -359,21 +359,18 @@ static int get_dimm_config(struct mem_ctl_info *mci)
359{ 359{
360 struct i7core_pvt *pvt = mci->pvt_info; 360 struct i7core_pvt *pvt = mci->pvt_info;
361 struct csrow_info *csr; 361 struct csrow_info *csr;
362 int i, csrow = 0; 362 struct pci_dev *pdev = pvt->pci_mcr[0];
363 int i, j, csrow = 0;
363 enum edac_type mode; 364 enum edac_type mode;
364 365
365 if (!pvt->pci_mcr[0]) 366 if (!pdev)
366 return -ENODEV; 367 return -ENODEV;
367 368
368 /* Device 3 function 0 reads */ 369 /* Device 3 function 0 reads */
369 pci_read_config_dword(pvt->pci_mcr[0], MC_CONTROL, 370 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
370 &pvt->info.mc_control); 371 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
371 pci_read_config_dword(pvt->pci_mcr[0], MC_STATUS, 372 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
372 &pvt->info.mc_status); 373 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
373 pci_read_config_dword(pvt->pci_mcr[0], MC_MAX_DOD,
374 &pvt->info.max_dod);
375 pci_read_config_dword(pvt->pci_mcr[0], MC_CHANNEL_MAPPER,
376 &pvt->info.ch_map);
377 374
378 debugf0("MC control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n", 375 debugf0("MC control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
379 pvt->info.mc_control, pvt->info.mc_status, 376 pvt->info.mc_control, pvt->info.mc_status,
@@ -399,7 +396,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
399 debugf0("Memory channel configuration:\n"); 396 debugf0("Memory channel configuration:\n");
400 397
401 for (i = 0; i < NUM_CHANS; i++) { 398 for (i = 0; i < NUM_CHANS; i++) {
402 u32 data; 399 u32 data, value[8];
403 400
404 if (!CH_ACTIVE(pvt, i)) { 401 if (!CH_ACTIVE(pvt, i)) {
405 debugf0("Channel %i is not active\n", i); 402 debugf0("Channel %i is not active\n", i);
@@ -424,13 +421,33 @@ static int get_dimm_config(struct mem_ctl_info *mci)
424 pvt->channel[i].dimms = 2; 421 pvt->channel[i].dimms = 2;
425 422
426 debugf0("Ch%d phy rd%d, wr%d (0x%08x): " 423 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
427 "%d ranks, %d %cDIMMs, offset = %d\n", 424 "%d ranks, %d %cDIMMs, offset = %d\n\t"
425 "present: %i, numbank: %#x, numrank: %#x, "
426 "numrow: %#x, numcol: %#x\n",
428 i, 427 i,
429 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), 428 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
430 data, 429 data,
431 pvt->channel[i].ranks, pvt->channel[i].dimms, 430 pvt->channel[i].ranks, pvt->channel[i].dimms,
432 (data & REGISTERED_DIMM)? 'R' : 'U', 431 (data & REGISTERED_DIMM)? 'R' : 'U',
433 RANKOFFSET(data)); 432 RANKOFFSET(data),
433 DIMM_PRESENT(data),
434 NUMBANK(data), NUMRANK(data),
435 NUMROW(data), NUMCOL(data));
436
437 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
438 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
439 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
440 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
441 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
442 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
443 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
444 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
445 printk("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
446 for (j = 0; j < 8; j++)
447 printk("\t\t%#x\t%#x\t%#x\n",
448 (value[j] >> 27) & 0x1,
449 (value[j] >> 24) & 0x7,
450 (value[j] && ((1 << 24) - 1)));
434 451
435 csr = &mci->csrows[csrow]; 452 csr = &mci->csrows[csrow];
436 csr->first_page = 0; 453 csr->first_page = 0;